Madan Mohan Malaviya Univ.

of Technology, Gorakhpur

(BEC-41)
VLSI Design
(Unit-1, Lecture-2)

Side 1
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Outcomes
▪ Trends & Projections in VLSI Circuits
▪ Flow diagram of VLSI Circuit Design
▪ VLSI Design issues
▪ Y-Chart

07-09-2021 Side 2
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

The ordering of topics covered in a typical

digital integrated circuits course

07-09-2021 Side 3
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Evolution of minimum feature size in integrated

circuits over time

07-09-2021 Side 4
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Level of integration versus time for memory

chips and logic chips

07-09-2021 Side 5
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design Flow

• Specifications comes first, they describe abstractly, the
functionality, interface, and the architecture of the
digital IC circuit to be designed.

• Behavioral description is then created to analyze the

design in terms of functionality, performance,
compliance to given standards, and other
specifications.

• RTL description is done using HDLs. This RTL

description is simulated to test functionality. From here
onwards we need the help of EDA tools.

• RTL description is then converted to a gate-level netlist

using logic synthesis tools. A gate level netlist is a
description of the circuit in terms of gates and
connections between them, which are made in such a
way that they meet the timing, power and area
specifications.

• Finally, a physical layout is made, which will be verified

and then sent to fabrication.

07-09-2021 Side 6
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Y-Chart • The Gajski-Kuhn Y-chart is a

model, which captures the
considerations in designing
semiconductor devices.

• The three domains of the Gajski-

Kuhn Y-chart are on radial axes.
Each of the domains can be
divided into levels of abstraction,
using concentric rings.

• At the top level (outer ring), we

consider the architecture of the
chip; at the lower levels (inner
rings), we successively refine the
design into finer detailed
implementation

• Creating a structural description

from a behavioral one is
achieved through the processes
of high-level synthesis or logical
synthesis.

• Creating a physical description

from a structural one is achieved
through layout synthesis.

07-09-2021 Side 7
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Design Hierarchy-Structural
• The design hierarchy involves the principle of "Divide and Conquer." It is nothing but dividing the task
into smaller tasks until it reaches to its simplest level. This process is most suitable because the last
evolution of design has become so simple that its manufacturing becomes easier.

• We can design the given task into the design flow process's domain (Behavioral, Structural, and
Geometrical). To understand this, let’s take an example of designing a 16-bit adder, as shown in the
figure below.

07-09-2021 Side 8
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Concepts of Regularity, Modularity and Locality

The hierarchical design approach reduces the design complexity by dividing the large system
into several sub-modules. Usually, other design concepts and design approaches are also
needed to simplify the process.
• Regularity means that the hierarchical decomposition of a large system should result in not
only simple, but also similar blocks, as much as possible. A good example of regularity is the
design of array structures consisting of identical cells - such as a parallel multiplication array.
• Modularity in design means that the various functional blocks which make up the larger
system must have well-defined functions and interfaces. Modularity allows that each block or
module can be designed relatively independently from each other, since there is no ambiguity
about the function and the signal interface of these blocks. All of the blocks can be combined
with ease at the end of the design process, to form the large system. The concept of
modularity enables the parallelization of the design process. It also allows the use of generic
modules in various designs - the well-defined functionality and signal interface allow plug-
and-play design.
• The concept of locality also ensures that connections are mostly between neighboring
modules, avoiding long-distance connections as much as possible. This last point is
extremely important for avoiding excessive interconnect delays. Time-critical operations
should be performed locally, without the need to access distant modules or signals. If
necessary, the replication of some logic may solve this problem in large system architectures.

07-09-2021 Side 9
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design Style

07-09-2021 Side 10
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Full Custom Design Semi Custom Design

• Geometry & placement of • Pre-optimized components are
every transistor can be directly used from library
optimized individually • Initially high performance but
• High performance level less at final stage
• More opportunity for circuit • Less opportunity for circuit
performance improvement performance improvement
• Better area utilization • Less area utilization
• Larger design time • Shorter design time
• High overall cost • Low overall cost

07-09-2021 Side 11
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Full Custom Design

• For the best use of current technology, chip development time has
to be short enough to allow maturing chip manufacturing and
timely delivery of the product to customers.
• This may cause short of level achievable with current technology.
07-09-2021 Side 12
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

Semi Custom Design

• If the design time is kept long, there is a danger of missing of next

technology window.
• In reality, design cycle of next generation overlaps with production
cycle of the current generation window
07-09-2021 Side 13
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-2)
The Metal Oxide Semiconductor (MOS) structure

• The structure consists of three • The basic properties of the

layer semiconductor
– The metal gate electrode The mass action law:n ⋅ p = ni2
– The insulating oxide (SiO2) Assume the substrate doping concentration N A
layer
ni2
– The p-type bulk then pn0 ≅ , p p0 ≅ N A
semiconductor NA

2
Energy band diagram of a p-type silicon substrate

EF -Ei
The Fermi potential φ F =
q
kT n
For a p-type semiconductor, φ Fp = ln i
q NA
kT N D
For a n-type semiconductor, φ Fn = ln
q ni
The energy required for an electron to move from the
Fermi level int o free space is called the work function
qφs = qχ + (Ec-EF )
3
Energy diagram of the combined MOS system

• The equilibrium Fermi levels of the semiconductor (Si) substrate

and the metal gate are at the same potential
• The bulk Fermi level is not significantly affected by the bending
• The surface Fermi level moves closer to the intrinsic Fermi level

4
Example 1

5
The MOS System under External Bias - accumulation

• A negative voltage VG is applied to the gate electrode.

– The holes in the p-type substrate are attracted to the semiconductor-
oxide surface
– The majority carrier concentration > the equilibrium hole concentration
• The electron concentration (minority carrier) decreases as the negatively
charged electron are pushed deeper into the substrate
– The oxide electric field is directed towards the gate electrode
– Causing the energy bands bend up-ward near the surface

6
The MOS System under External Bias – depletion
• A small positive gate bias VG is applied to the gate
electrode
– The oxide electric field will be directed towards the substrate
– Causing the energy bands to bend downward near the surface
– The majority carrier (hole) will be repelled backed into the
substrate
• Leaving negatively charged fixed acceptor ions behind (depletion
region)
dQ = −q ⋅ N A ⋅dx
dQ q ⋅ N A ⋅ x
d s = −x ⋅ = dx
dx Si

d = xd q ⋅ N A ⋅ x
∫ ∫
s
s
dx
F
0
Si

q ⋅ N A ⋅ xd2
s − F =
Si

2 ⋅ s−
xd = Si F

q⋅NA
Q = −q ⋅ N A ⋅ xd = − 2q ⋅ N A ⋅ Si ⋅ s − F

7
The MOS System under External Bias – inversion
• A further increase in the positive gate bias
– Increasing surface potential the downward bending of the energy bands will increase
– The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface
• The substrate semiconductor in this region become n-type
• The electron density is larger than the majority hole density
• Inversion layer, surface inversion
• Can be utilized for conducting current between two terminal of the MOS transistor
– The surface is said to be inverted
• The density of mobile electrons on the surface becomes equal to the density of holes in the bulk
substrate
• Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi
potential φF
• Further increase gate voltage electron concentration↑ but not to an increase of the depletion
depth

2⋅ ⋅2
xdm =
Si F

q⋅NA

8
The physical structure of a n-channel
enhancement-type MOSFET

• MOS structure
– polysilicon gate, thin oxide layer, semiconductor
• Source, drain n+-region
– The current conducting terminals of the device
• Conducting channel, channel length L, channel width W
– The device structure is completely symmetrical with respect to the drain and source
• The simple operation of this device
– Controlling the current conduction between the source and the drain, using the electric field
generated by the gate voltage as a control variable

9
Circuit symbols for enhancement-type MOSFET

• Enhancement-mode MOSFET
– No conducting region at zero gate bias
• Depletion-mode MOSFET
– A conducting channel already exists at zero gate bias
• The abbreviations used for device terminals are
– G for the gate, D for the drain, S for the source, and B for the substrate
• The small arrow always marks the source terminal

10
Formation of a depletion region
• For small gate voltage level
– The majority carriers (holes) are repelled back into
the substrate
– The surface of the p-type substrate is depleted
– Current conduction between S and D is not possible

11
Formation of an inversion layer

• As the gate-to-source voltage is further increased

– The surface potential reaches -φFp surface inversion will be established conducting
channel between S and D
– Allowing current flow, as log as there is a potential difference between S and D
– VGS<VT0 (threshold voltage)
• Not sufficient to establish an inversion layer
• No current between S and D
– VGS>VT0 (threshold voltage)
• Electrons are attracted to the surface
– Contributing to channel current conduction
– Further increase gate voltage
• Not affect the surface potential and the depletion region depth

12
The threshold voltage
• Four physical components of VT0 • Compared with the p-MOSFET
– The work function difference between – The substrate Fermi potential φF is
gate and the channel negative in NMOS, positive in
• φGC= φF(substrate)- φM for metal gate
pMOS
• φGC= φF(substrate)- φF(gate) for
polysilicon gate – The depletion region charge
– The gate voltage component to change densities QB0 and QB are negative
the surface potential in nMOS, positive in pMOS
• To change the surface potential by -2φF – The substrate bias coefficient γis
– The gate voltage component to offset positive in nMOS, negative in
the depletion region charge pMOS
• -QB/Cox
•
QB = − 2q ⋅ N A ⋅ ⋅−2 +VSB
– The substrate bias voltage VSB is
Si F
positive in nMOS, negative in
Cox = ox
pMOS
tox

– The voltage component to offset the

fixed charge in the gate oxide and in • Threshold voltage adjustment
the silicon-oxide interface – Implanting p-type impurity VT
• -Qox/Cox increased
•V T0 = Φ GC − 2 F −
QB 0 Qox
− (no body effect) – Implanting n-type impurity VT
C ox C ox
decreased
VT = VT 0 + ⋅ −2 + VSB − 2 (with body effect)
F F
– The amount of change in the
2q ⋅ N A ⋅ threshold voltage
where = Si

Cox • Shift qNI/Cox

13
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-3)
MOSFET operation: linear region
• The MOSFET consists
– A MOS capacitor, two pn junction adjacent to the channel
– The channel is controlled to the MOS gate
• The carrier (electron in nMOSFET)
– Entering through source, controlling by gate, leaving through drain
• To ensure that both p-n junctions are reverse-biased initially
– The substrate potential is kept lower than the other three terminal potentials
• When 0<VGS<VT0
– G-S region depleted, G-D region depleted
– No current flow
• When VGS>VT0
– Conduction channel formed
– Capable of carrying the drain current
– As VDS=0
• ID=0
– As VDS>0 and small
• ID proportional to VDS
• Flowing from S to D through the conducting channel
• The channel act as a voltage controlled resistor
• The electron velocity much lower than the drift velocity limit
• As V DS ↑ the inversion layer charge and the channel depth at the drain end start to
decrease

17
MOSFET operation: saturation region
• For VDS=VDSAT
– The inversion charge at the drain is
reduced to zero
– Pitch off point
• For VDS>VDSAT
– A depleted surface region forms
adjacent to the drain
– As further increases VDS this
depletion region grows toward the
source
– The channel-end remains essentially
constant and equal to VDSAT
– The pitch-off (depleted) section
• Absorbing most of the excess voltage
drop, VDS-VDSAT
• A high-field forms between the
channel-end of the drain boundary
– Accelerating electrons, usually
reaching the drift velocity limit

18
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(1)
• Considering linear mode operation
– VS=VB=0, the VGS and VDS are the external parameters controlling the drain
current ID
– VGS > VT0 (assume constant through the channel) to create a conducting inversion layer
– Defining
• X-direction: perpendicular to the surface, pointing down into the substrate
• Y-direction: parallel to the surface
– The y=0 is at the source end of the channel
– Channel voltage with respect to the source, Vc(y)
– Assume the electric field Ey is dominant compared with Ex
• This assumption reduced the current flow in the channel to the y-direction only
– Let QI(y) be the total mobile electron charge in the surface inversion layer
• QI(y)=-Cox[VGS-Vc(y)-VT0]

19
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(2)
Assumeing that all mobile electrons in the inversion layer has a constant surfacr mobility μn
dy
dR = − (mimus sign is due to the negative polarity of the inversion layer charge Q I)
W ⋅ μ n ⋅Q I(y)
The electron surface mobility μn dependents on the doping concentration of the channel region,
and its magnitude is typically about one - half of that of the bulk electron mobility
ID
dVC = I D ⋅dR = - ⋅dy
W ⋅ μn ⋅Q I (y)
L VDS
∫
0
I D ⋅dy = −W ⋅ n ∫
0
QI ( y) ⋅dVC
VDS
ID ⋅ L = W ⋅ n ⋅Cox ∫ VGS −VC −VT 0 ⋅dVC
0

⋅Cox W
⋅ ⋅ 2 ⋅ VGS −VT 0 VDS −VDS
2
ID = n
2 L
k' W
I D = ⋅ ⋅ 2 ⋅ VGS −VT 0 VDS −VDS 2
where k ' = μ nC ox
2 L
k W
I D = ⋅ 2 ⋅ VGS −VT 0 VDS −VDS
2 where k = k ' ⋅
2 L

20
Example 4

21
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)-saturation region

• For VDS≥VDSAT=VGS-VT0
– ⋅Cox W
⋅ ⋅ 2 ⋅ VGS − VT 0 ⋅ VGS −VT 0 – VGS −VT 0
2
I D (sat ) = n
2 L
⋅C W
= n ox ⋅ ⋅ VGS − VT 0
2

2 L
– The drain current becomes a function only of VGS, beyond the saturation
boundary

22
 Channel length modulation
The inversion layer charge at the source end of the channel is
QI (y = 0 ) = -C ox ⋅ VGS -VT 0
and the inversion layer charge at the drain end of the channel is
QI (y = L) = -C ox ⋅ VGS -VT 0 −VDS
Note that at the edge of saturation, VDS = VDSAT = VGS -VT 0
The inversion layer charge at the drain end become very small
QI(y = L) ≈ 0
The effective channel length L' = L-Δ-
where ΔΔ is the length of the channel segment with Q I = 0
μC W
I D(sat) = n ox ⋅ ' ⋅ VGS −VT 0
2

2 L
⎛ ⎞
⎜ 1 ⎟μ C W
ID(sat) =⎜ ⎟ n ox ⋅ ⋅ VGS −VT 0
2

⎜1 − ΔL ⎟ 2 L'
⎝ L⎠
ΔL ∝ VDS − VDSAT
ΔL
We use 1− ≈ 1 − λ ⋅V DS , λ channel length modulation coefficient
L
Assuming that λλ DS << 1
μn ⋅Cox W
I D(sat) = ⋅ ⋅ VGS − VT 0 ⋅ 1+ λV DS
2

2 L

23
Substrate bias effect
• The discussion in the previous has been done under the assumption
– The substrate potential is equal to the source potential, i.e. VSB=0
• On the other hand
– the source potential of an nMOS transistor can be larger than the substrate
potential, i.e. VSB>0
– VT (VSB ) = VT 0 + ⋅ 2 F +VSB − 2 F
⋅Cox W
I D(lin) =
n
⋅ ⋅ 2 ⋅ VGS −VT (VSB ) VDS −VDS
2
2 L
⋅C W
I D(sat ) = n ox ⋅ ⋅ VGS −VT (VSB ) 2 ⋅ 1+ ⋅VDS
2 L

24
Current-voltage equation of n-, p-channel MOSFET

For n - channel MOSFET

I D = 0, for VGS < VT
⋅Cox W −V V −V 2
for V ≥ V
I D(lin) = n
⋅ ⋅ 2 ⋅ VGS T DS DS GS T
2 L
and VDS < VGS -VT
⋅Cox W
I D( sat ) = n
⋅ ⋅ VGS −VT 2
⋅ 1+ ⋅VDS for VGS ≥ VT
2 L
and VDS ≥ VGS -VT
For p - channel MOSFET
I D = 0, for VGS > VT
⋅Cox W −V 2
for V ≤ V
I D(lin) = n
⋅ ⋅ 2 ⋅ VGS −VT VDS DS GS T
2 L
and VDS > VGS -VT
⋅Cox W
I D( sat ) = n
⋅ ⋅ VGS −VT 2
⋅ 1+ ⋅VDS for VGS ≤ VT
2 L
and VDS ≤ VGS -VT
25
Measurement of parameters- kn, VT0, and
• The VSB is set at a constant value
– The drain current is measured for different values of VGS
– VDG=0
• VDS>VGS-VT is always satisfied saturation mode
• Neglecting the channel length modulation effect
– kn kn
I D ( sat ) =
⋅ V GS − V T 0 , I D = ⋅ V GS − V T 0
2

2 2
– Obtaining the parameters kn, VT0, and γ
– VT (VSB ) −VT 0
=
2 F +VSB − 2 F

26
Measurement of parameters-
• The voltage VGS is set to VT0+1
• The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistor
operates in the saturation mode, VDS1, VDS2
– ID(sat)-(kn/2)(VGS-VT0)2(1+λVDS)
• Since VGS=VT0+1 ID2/ID1=(1+λVDS2)/ (1+λVDS1)
• Which can be used to calculate the channel length modulation coefficient λ
• This is in fact equivalent to calculating the slope of the drain current versus drain
voltage curve in the saturation region
– The slope is λkn/2

27
Example 5

28
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-4)

Department of Electronics and Communication Engineering

16-07-2020 Side 1
MOSFET scaling and small-geometry effects
• High density chip
– The sizes of the transistors are as small as possible
– The operational characteristics of MOS transistor will change with the reduction of iys
dimensions
• There are two basic types of size-reduction strategies
– Full scaling (constant-field scaling)
– Constant-voltage scaling
• A new generation of manufacturing technology replaces the previous one about
– every two or three years
– The down-scaling factor S about 1.2 to1.5
• The scaling of all dimensions by a factor of S>1 leads to the reduction of the area
occupied by the transistor by a factor of S2

29
 Full scaling (constant-field scaling)
To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor
Assuming the surface mobility μn is not significantly affected by the scaled doping density
The gate oxide capacitance per unit area

C'ox = ox
'
=S⋅ ox
= S ⋅C ox
t ox t ox
The aspect ratioW/L unchanged⇒ the k n will also scaled by a factor of S
The linear mode drain current
k 'n
I (lin) = ⋅ 2 ⋅ VGS
'
D
'
−VT' ⋅VDS'
−VDS'2

2
S ⋅k n ⋅ 1 ⋅ 2 ⋅ VGS −VT ⋅VDS −V 2 ID(lin)
= DS
=
2 S2 S
The saturation mode drain current
k n' S ⋅k n ⋅ 1 ⋅ V −V 2 ID(sat)
=
2
I D(sat) = ⋅ VGS
' '
−VT' = 2 GS T
2 2 S S
The power dissipation
1 P
P' = I 'D ⋅VDS
'
= ⋅ I ⋅V =
S 2 D DS S 2
The significant reduction of the power dissipation is one of the most attractivefeatures of full scaling
The power density per unit area remaining virtually unchanged
C g is scaled down by a factor of S ⇒ the charge- up, and charge- down time improved
A reduction of various parasitic capacitances abd resistances

30
 Constant-voltage scaling
All dimensions of the MOSFETare reduced by a factor of S.
The power supply voltage and the terminal voltages remained unchanged.
The doping densities must be increased by a factor of S 2 in order to preserve the charge - field relations
The gate oxide capacitance per unit area Cox is increased by a factor of S
⇒ The transconductance parameter is also increased by S
The linear mode drain current
k'
I (lin) = ⋅ 2 ⋅ VGS
'
D
n '
−VT' ⋅VDS
'
− VDS
'2

2
S ⋅k n
= ⋅ 2 ⋅ VGS −VT ⋅VDS −VDS
2
= S ⋅ I D(lin)
2
The saturation mode drain current
k n' S ⋅k n
2
I (sat) = −VT' =
⋅ VGS −VT = S ⋅ I D(sat)
' ' 2
D VGS
2 2
The drain current density increased by a factor of S 3
The power dissipation
P' = I 'D ⋅VDS
'
= (S ⋅ I D )⋅VDS = S ⋅ P
The power density incresaed by a factor of S 3
To summarized, constant - voltage scaling may be preferred over full scaling in mamy practicalcases
because of the external voltage- level constraints.
Disadv.⇒ increasing current density, power density
⇒ electromigration, hot carrier degradation, oxide breakdown, and electricalover - stress
31
Short-channel effects
• A MOS transistor is called a short-channel device
– If its channel length is on the same order of magnitude as the
depletion region thickness of the S and D junction
– The effective channel length Leff S, D junction depth xj
– Two physical phenomena arise from short-channel effects
• The limitations imposed on electron drift characteristics in the
channel
– The lateral electric field Ey increased, vd reached saturation velocity
L
– I = W ⋅v ⋅ ∫
q ⋅ n(x) ⋅ dx = W ⋅v ⋅ Q = W ⋅v ⋅C ⋅V
eff
D (sat ) d (sat ) d (sat) I d (sat ) ox DSAT
0

» No longer a quadratic function of VGS, virtually independent of the

channel length
– The carrier velocity in the channel also a function of Ex
» Influence the scattering of carriers in the surface
» (eff ) = no
= no
= no
n
1+ Θ ⋅ Ex Θ ox
⋅ VGS −Vc (y) 1+ ⋅ VGS −VT
1+
tox Si

• The modification of the threshold voltage due to the shortening

channel length

32
Short-channel effects-modification of VT
• The n+ drain and source diffusion regions in p-type substrate induce a
significant amount of depletion charge
– The long channel VT, overetimates the depletion charge support by the gate
voltage
– The bulk depletion region asymmetric trapezoidal shape
• A significant portion of the total depletion region charge is due the S and D junction
depletion
VT 0(short channel) = VT0 -ΔVT0
⎛ ΔL + ΔL D ⎞
QB 0 = −⎜1− S ⎟⋅ 2 ⋅q ⋅ε Si ⋅ N A ⋅ 2φF
⎝ 2L ⎠
2 ⋅ε Si 2 ⋅ε Si kT ⎛N D ⋅ N A ⎞
xdS = ⋅φ0 , xdD = ⋅ φ0 +VDS , φ0 = ⋅ln ⎜ 2 ⎟
q⋅NA q⋅NA q ⎝ ni ⎠
x j + xdD 2
= xdm
2
+ x j + ΔL D 2

ΔL2 + 2 ⋅ x ⋅ ΔL + x 2 − x 2 − 2 ⋅ x ⋅ x =0
D j D dm dD j dD

⎛ 2x ⎞
ΔLD = −x j + x 2j − xdm
2
– xdD
2
+ 2x j xdD ≅x j ⋅ ⎜ 1+ dD −1⎟
⎜ xj ⎟
⎝ ⎠
⎛ 2x ⎞
ΔLS ≅x j ⋅⎜ 1+ dS − 1⎟
⎜ xj ⎟
⎝ ⎠
1 x j ⎡⎛ 2x ⎞ ⎛ 2x ⎞⎤
ΔVT 0 = ⋅ 2 ⋅q ⋅ε Si ⋅ N A ⋅ 2φF ⋅ ⋅⎢⎜ 1+ dD −1⎟+ ⎜ 1+ dS − 1⎟⎥
2L ⎢⎜⎝ ⎟ ⎜ ⎟
Cox
⎣
xj ⎠ ⎝ xj ⎠⎦⎥
33
Example 6 (1)

34
Example 6 (2)

35
Example 6 (3)

36
Narrow-channel effect
• Channel width W on the same
order of magnitude as the
maximum depletion region
thickness xdm
• The actual threshold voltage of
such device is larger than that
predicted by the conventional
threshold voltage
• Fringe depletion region under
field oxide
– VT 0 (narrow channel) = VT0 + ΔVT0
1 ⋅ xdm
ΔVT0 = ⋅ 2q Si N A 2 F ⋅
Cox W

= for depletion region modeled by quarter - circular arcs

2

37
Other limitations imposed by small-device geometries
• The current flow in the channel are controlled by two dimensional electric field vector
• Subthreshold conduction
– Drain-induced barrier lowering (DIBL)
– A nonzero drain current ID for VGS<VT0
– qDnWx cn 0 qkT kTq
r
A⋅VGS +B⋅V DS
I D (subthreshold ) ≅ ⋅e ⋅e
LB
• Punch-through
– The gate voltage loses its control upon the drain current, and the current rises sharply
• Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties
– Pinholes, oxide breakdown
• Hot-carrier effect

38
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-5)

Department of Electronics and Communication Engineering

16-07-2020 Side 1
MOSFET capacitances
• L=LM-2LD
– L: the actual channel length
– LM: the mask length of the
gate
– LD: the gate-drain, the gate-
source overlap
• On the order of 0.1μm

39
Oxide related capacitance(1)
• The gate electrode overlap
capacitance
– CGD(overlap)=CoxWLD
– CGS(overlap)=CoxWLD
• With Cox= ox/tox
– Both capacitance do not depend
on the bias condition, they are
voltage-independent
• The capacitances result from the
interaction between the gate
voltage and the channel charge
– Cut-off mode
• Cgs=Cgd=0
• Cgb=CoxWL
– Linear mode
• Cgb=0
• Cgs≅Cgd ≅(1/2) CoxWL
– Saturation mode
• Cgb= Cgd =0
• Cgs≅(2/3) CoxWL 40
Oxide related capacitance(2)
• The sum of all three voltage-dependent (distributed) gate oxide
capacitances (Cgb+Cgs+Cgd)
– A minimum value of 0.66CoxWL, in saturation mode
– A maximum value of CoxWL, in cut off and linear modes
– For simple hand calculation
• The three capacitances can be considered to be in parallel
• A constant worst-case value of CoxW(L+2LD) can be used for the sum of
MOSFET gate oxide capacitances

41
 Junction capacitance(1)

2 ⋅ε Si N A + N D
The depletion region thickness x d = ⋅ φ0 −V
q NA ⋅ND
kT ⎛N ⋅ N ⎞
The built - in potential φ0 = ⋅ln ⎜ A 2 D ⎟
q ⎝ ni ⎠
⎛N ⋅ N ⎞ N ⋅N
The depletion region charge Q j = A⋅q ⋅⎜ A D ⎟⋅ xd = A 2 ⋅εSi ⋅q ⋅ A D φ0 −V
⎝N A + N D ⎠ A +ND
N

dQ j ε ⋅q ⎛N ⋅ N ⎞ 1
The junction capacitance C j = = A⋅ Si ⋅⎜ A D ⎟⋅
dV 2 ⎝N A + N D ⎠ φ0 −V
AC j 0
C j(V) = , the parameter m is grading coefficient
⎜1− V ⎞
m
⎛ ⎟
⎝ φ0 ⎠

⎛N A ⋅ N D ⎞
ε Si ⋅q ⋅⎜ ⎟⋅ 1
The zero bias junction capacitance per unit area C j 0 =
2 ⎝N A + N D ⎠ φ0
The equivalent large - signal capacitance can be defined as
ΔQ Q j(V2 ) −Q j (V1 ) 1 V2
Ceq = = = ∫ C j(V)dV
ΔV V2 −V1 V2 −V1 V1

A⋅C j 0 ⋅ ⎡⎛ V ⎞1−m ⎛ V ⎞1−m ⎤

=− ⋅ ⎢⎜1− 2 ⎟ − ⎜1− 1 ⎟ ⎥
0

V2 −V ⋅ 1− m ⎣⎢⎝ 0 ⎠ ⎝ 0 ⎠ ⎥⎦
For the special case of abrupt pn - junctions
2 ⋅ A⋅C j 0 ⋅φ0 ⎡ V V ⎤
Ceq = − ⋅ ⎢ 1− 2 − 1− 1 ⎥
V 2 −V ⎣ 0 0 ⎦

Ceq = A⋅C j 0 ⋅ K eq
2 0
K eq = − ⋅ −V2 − −V1
V2 −V 1 42
0 0
Example 7

43
Junction capacitance(2)
The sidewalls of a typical MOSFET source or drain diffusion region
are surrounded by a p + channel - stop implant, with a higher doping density
than the substrate doping density N A
Assume the sidewall doping density is given by NA(sw) ,
the zero - bias capacitance per unit area can be found as

ε Si ⋅q ⎛ N A(sw) ⋅ N D ⎞ 1
C j 0 sw = ⋅ ⎜ ⎟⋅
2 ⎝N A(sw) + N D ⎟
⎜
⎠ φ0 sw
C jsw = C j 0sw ⋅ x j
The sidewall voltage equivalence factor
2 0 sw
K eq ( sw) = − ⋅ 0sw −V2 − 0sw −V1
V2 −V1
The equivalent large - signal junction capacitance Ceq(sw) for
a sidewall of length (perimeter)P can be
Ceq(sw) = P ⋅C jsw ⋅ K eq(sw)
44
Example 8 (1)

45
Example 8 (2)

46
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-6)

Presented By:
Prof. R. K. Chauhan
Mr. Prince Kumar Singh
Department of Electronics and Communication Engineering
16-07-2020 Side 1
Introduction
• The SPICE software that was distributed by UC
Berkeley beginning in the late 1970s had three
built-in MOSFET models
– LEVEL1(MOS1) is a described y a square-law
current-voltage characteristics
– LEVEL2 (MOS2) is a detailed analytical MOSFET
model
– LEVEL 3 (MOS3) is a semi-empirical model
• Both MOS2 and MOS3 include second-order effects
– The short channel threshold voltage, subthreshold conduction,
scattering-limited velocity saturation, and charge-controlled
capacitances
– The BSIM3 version
• More accurate characterization sub-micron MOSFET
characteristics
2
Basic concept

• The equivalent circuit structure of the

NMOS LEVEL 1 model

3
 The LEVEL 1 model equation
• K’=27.6μA/V2 KP=27.6U
Linear region
• VT0=1.0V VTO=1
k'W
ID = ⋅ ⋅ 2 ⋅ VGS −VT VDS −VDS
2
⋅ 1+ λ ⋅VDS for VGS ≥ VT • γ=0.53V1/2 GAMMA=0.53
2 Leff • 2φF=-0.58 PHI=0.58
and VDS < VGS -VT • λ=0 LAMBDA=0
Saturation region • μn=800cm2/Vs UO=800
k'
• tox=100nm TOX=100E-9
W
ID = ⋅ ⋅ VGS −VT ⋅ 1+ λ ⋅VDS for VGS ≥ VT •
2
NA=1015cm-3 NSUB=1E15
2 Leff
• LD=0.8μm LD=0.8E-6
and VDS ≥ VGS -VT
The threshold voltage
VT = VT0 + ⋅ 2 F +VSB − 2 F

Leff = L − 2 ⋅ LD
εox
k' = ⋅Cox where Cox =
tox
2⋅ ⋅q ⋅ N A
=
Si

Cox
kT ⎛ni ⎞
2 F =2 ⋅ln ⎜ ⎟
q ⎝N A ⎠

4
Variation of the drain current with model parameter

5
The LEVEL 2 model equation
k' W ⎧⎛ V DS ⎞ 2 3/2 3/ 2 ⎫
ID = ⋅⋅⎨⎜VGS −V FB − 2 − ⎟⋅VDS − ⋅ ⋅ VDS −V BS + 2 – −V BS + 2 ⎬
1 − ⋅VDS Leff ⎩⎝
F F F
2 ⎠ 3 ⎭
The saturation voltage
⎛ 2 ⎞
VDSAT = VGS − VFB − 2 F + 2
⋅⎜1− 1+ 2 ⋅ VGS −V FB ⎟
⎝ ⎠
The saturation mode current
1
I D = IDsat ⋅
1-λ⋅VDS
The zero bias threshold voltage
q ⋅ N ss
VT 0 = Φ GC – +2 F + 2 F
Cox
• In the current equation above, the surface carrier mobility has been assumed
constant, and its variation with applied terminal voltages has been neglected
• In reality, the surface mobility decreases with the increasing gate voltage
– Due to the scattering of carriers in the channel
– Ue
⎛ t oc ⋅U c ⎞
'
k(new) = k ' ⋅⎜ Si ⋅ ⎟
⎝ ox VGS −VT −U t ⋅VDS ⎠
U c is the gate - to - channel critical field
U t is the contribution of the drain voltage to the gate - to - channel field
U e is the exponential fitting parameter 6
variation of channel length in saturation mode
'
Leff = Leff − ΔL
⎡V − V 2⎤
2 ⋅ Si ⎛V − V ⎞
ΔL = ⋅ ⎢ DS DSAT
+ 1+ ⎜ DS DSAT
⎟⎥
q ⋅ NA
⎢⎣ 4 ⎝ 4 ⎠ ⎥⎦
The empirical channel length shortening coefficient
ΔL
=
Leff ⋅VDS
The slope of the ID-VDS vurve is saturation can be adjusted and
fitted to experimental data by changing the substrate doping parameter N A
In this case, however, other N A - dependent electrical parameters such
as 2 F and must be specified separately in the .MODEL statement

7
Saturation of carrier velocity
• The calculation of the saturation voltage VDSAT is based
on the assumption
– The channel charge near the drain becomes equal to zero when
the device enters saturation
– This hypothesis is actually incorrect
• Since a minimum charge concentration greater than zero must exist
in the channel, due to the carriers that sustain the saturation current
• The minimum concentration depends on the speed of the carriers
• The inversion layer charge at the channel-end is found as
– IDsat
Qinv =
W ⋅vmax
2
⎛X D ⋅vmax ⎞ X D2 ⋅vmax
⎜
ΔL = X D ⋅ ⎜ ⎟
⎟ +V DS − VDSAT – 2 ⋅
⎝ 2⋅ ⎠
2 ⋅ Si
XD =
q ⋅ N A ⋅ N eff

– The parameter Neff is used as a fitting parameter

8
Subthreshold conduction
• For VGS<VT, there is a channel current even
when the surface is not in strong inversion
• This subthreshold current
– Due mainly to diffusion between and the
channel
– Becoming an increasing concern for deep-
sub-micron designs
• The model implemented in SPICE
introduces an exponential, semi-empirical
dependence of the drain current on VGS in
the weak inversion region
– ⎛ q ⎞
(VGS −Von )⋅⎜ ⎟
I D (weak inversion) = I on ⋅e ⎝nkT ⎠

I on is the current in strong inversion for VGS = Von

the voltageVon is found as
nkT q ⋅ N FS Cd
Von = VT + where n = 1+ +
q Cox Cox
The parameter N FS is defined as the number of fast superficial states
and is used as a fitting parameter that determines the slope of the subthreshold
current - voltage characteristics
Cd : is the depletion capacitance
This model introduces a discontinuity for VGS = Von , therefore, the simulation
of the transition region between weak and strong inversion is not very precise
9
The LEVEL 3 model equations
• The LEVEL 3 model has been developed for simulation of short channel
MOS transistor
– Quite precisely for channel lengths down to 2μm
– The current-voltage equation in the linear region has been simplified with a
Taylor series expansion
– The majority of the LEVEL 3 model equations are empirical
• To improve the accuracy of the model
• To limit the complexity of the calculation
W ⎛ 1 + FB
ID = s ⋅C ox ⋅ ⋅ ⎜VGS −VT − ⋅VDS ⎞
⎟⋅V DS
Leff ⎝ 2 ⎠
⋅ Fs
where FB = + Fn
4⋅ 2 F +VSB
The empirical parameter FB express the dependence of the bulk depletion charge
The VT . Fs , and μs are influenced by the short - channel effects
The Fn is influenced by the narrow - channel effects
μ
μs =
1 + θ ⋅ VGS -VT
The decreasein the effective mobility with the average lateral electricalfield
μs
μeff =
VDS
1+ μs ⋅
vmax ⋅ Leff
10
State-of-art MOSFET models
• BSIM-Berkeley short-channel IGFET model
– The model is analytically simple and is based on a small number
of parameters, which are normally extracted from experimental
data
– Accuracy and d\efficiency
– Widely used by many companies and silicon foundries
• EKV (Enz-Krummenacher-Vittoz) transistor model
– Previous models considering
• The strong-inversion region of operation separately from the weak-
inversion region
• Causing serous problems in the modeling of transistors at very low
voltages as in many cases involving deep sub-micron CMOS
technology
– Attempting to solve this problem by
• Using a unified view of the transistor operating regions
• Avoiding the use of disjoint equations in strong and weak inversion

11
Gate oxide capacitance
• SPICE uses a simple gate oxide capacitance model that represents the charge
storage effect by three nonlinear two-terminal capacitor: CGB, CGS and CGD
• The geometry information required for the calculation of gate oxide capacitance are:
– Gate oxide thickness TOX
– Channel width W
– Channel length L
– Lateral diffusion LD
• The capacitances CGBO, CGSO, and CGDO, which are specified in the .MODEL
statement, are the overlap capacitances between the gate and the other terminals
outside the channel region
• If the parameter XQC is specified in the .MODEL statement
– SPICE uses a simplified version of the charge-controlled capacitance model proposed by
Ward

12
Junction capacitance

C j ⋅ AS C jsw ⋅ PS
C SB = +
⎛ VBS ⎞
Mj
⎛ VBS ⎞
Mjsw

⎜1− ⎟ ⎜1− ⎟
⎝ 0 ⎠ ⎝ 0⎠

C j ⋅ AD C jsw ⋅ PD
C DB = +
⎛ VBD ⎞
Mj
⎛ VBD ⎞
jsw M

⎜1− ⎟ ⎜1− ⎟
⎝ 0 ⎠ ⎝ 0 ⎠

C j : the zero - bias depletion capacitance per unit area at the bottom of the junction
C jsw : the zero - bias depletion capzcitance per unit length at the sidewall junctions
Cjsw ≅ 10 ⋅C j ⋅ x j
AS and AD are the source and the drain areas
PS and PD are the source and the drain perimeters
M j and M jsw denote the junction grading coefficients for the bottom and the sidewalls junctions
Default values are M j = 0.5 and M jsw = 0.33

13
Comparison of the SPICE MOSFET models
• The LEVEL 1 model
– Not very precise
– Quick and rough estimate of the circuit performance
without much accuracy
• THE LEVEL 2 model
– Require a larger time
– May occasionally cause convergence problems in the
Newton-Raphson algorithm used in SPICE
• THE LEVEL 3 model
– The CPU time needed for model evaluation is less
and the number of iterations are significantly fewer for
the LEVEL three model
– Disadvantage
• The complexity of calculating some of its parameters

14
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-1, Lecture-7)

Department of Electronics and Communication Engineering

23-09-2021 Side 1
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur
Variation of
Surface Charge
Density

Fig. Variation of surface charge

density in p-type
semiconductor as a function of
surface potential
23-09-2021 Side 2
 Madan Mohan Malaviya Univ. of Technology, Gorakhpur

C-V Characteristics of MOSFETs

23-09-2021 Side 3