UNIT-4

10 marks

a) Explain the internal configuration of a DMA Controller diagrammatically and it works.

In modern computer systems, transferring data between input/output devices and memory
can be a slow process if the CPU is required to manage every step. To address this, a Direct
Memory Access (DMA) Controller is utilized. A Direct Memory Access (DMA) Controller
solves this by allowing I/O devices to transfer data directly to memory, reducing CPU
involvement. This increases system efficiency and speeds up data transfers, freeing the CPU
to focus on other tasks. DMA controller needs the same old circuits of an interface to
communicate with the CPU and Input/Output devices.
Direct Memory Access (DMA) uses hardware for accessing the memory, that hardware is
called a DMA Controller. It has the work of transferring the data between Input Output
devices and main memory with very less interaction with the processor. The direct Memory
Access Controller is a control unit, which has the work of transferring data.
DMA Controller is a type of control unit that works as an interface for the data bus and the
I/O Devices. As mentioned, DMA Controller has the work of transferring the data without the
intervention of the processors, processors can control the data transfer. DMA Controller also
contains an address unit, which generates the address and selects an I/O device for the
transfer of data. Here we are showing the block diagram of the DMA Controller.

Block diagram of DMA Controller

Types of Direct Memory Access (DMA)

There are four popular types of DMA.
 Single-Ended DMA
 Dual-Ended DMA
 Arbitrated-Ended DMA
 Interleaved DMA
Single-Ended DMA: Single-Ended DMA Controllers operate by reading and writing from a
single memory address. They are the simplest DMA.
Dual-Ended DMA: Dual-Ended DMA controllers can read and write from two memory
addresses. Dual-ended DMA is more advanced than single-ended DMA.
 Arbitrated-Ended DMA: Arbitrated-Ended DMA works by reading and writing to several
memory addresses. It is more advanced than Dual-Ended DMA.
Interleaved DMA: Interleaved DMA are those DMA that read from one memory address and
write from another memory address.

Working of DMA Controller

The DMA controller registers have three registers as follows.
 Address register – It contains the address to specify the desired location in memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.

The figure below shows the block diagram of the DMA controller. The unit communicates with
the CPU through the data bus and control lines. Through the use of the address bus and allowing
the DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. RD
and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can communicate with
DMA registers. When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can
communicate directly with the memory.

Working Diagram of DMA Controller

b) Explain the hardware organization of the associative memory in detail.

An associative memory can be treated as a memory unit whose saved

information can be recognized for approach by the content of the
information itself instead of by an address or memory location.
Associative memory is also known as Content Addressable Memory
(CAM).
 The block diagram of associative memory is shown in the figure. It
includes a memory array and logic for m words with n bits per word.
The argument register A and key register K each have n bits, one for
each bit of a word.

The match register M has m bits, one for each memory word. Each word in
memory is related in parallel with the content of the argument register.

The words that connect the bits of the argument register set an equivalent
bit in the match register. After the matching process, those bits in the
match register that have been set denote the fact that their equivalent
words have been connected.

Reading is proficient through sequential access to memory for those

words whose equivalent bits in the match register have been set.

The key register supports a mask for selecting a specific field or key in the
argument word. The whole argument is distinguished with each memory
word if the key register includes all 1's.

Hence, there are only those bits in the argument that have 1's in their
equivalent position of the key register are compared. Therefore, the key
gives a mask or recognizing a piece of data that determines how the
reference to memory is created.
The following figure can define the relation between the memory array
and the external registers in associative memory.

The cells in the array are considered by the letter C with two subscripts.
The first subscript provides the word number and the second determines
the bit position in the word. Therefore cell Cij is the cell for bit j in word i.
A bit in the argument register is compared with all the bits in column j of
the array supported that K j = 1. This is completed for all columns j = 1,
2 . . . , n.
If a match appears between all the unmasked bits of the argument and
the bits in word i, the equivalent bit Mi in the match register is set to 1. If
one or more unmasked bits of the argument and the word do not match,
Mi is cleared to 0.

c) Explain the cache memory mapping techniques.

Cache mapping is the procedure in to decide in which cache line the main memory block will
be mapped. In other words, the pattern used to copy the required main memory content to
the specific location of cache memory is called cache mapping. The process of extracting the
cache memory location and other related information in which the required content is
present from the main memory address is called as cache mapping. The cache mapping is
done on the collection of bytes called blocks. In the mapping, the block of main memory is
moved to the line of the cache memory. Cache mapping is needed to identify where the
 cache memory is present in cache memory. Mapping provides the cache line number where
the content is present in the case of cache hit or where to bring the content from the main
memory in the case of cache miss.

There are three types of cache mappings namely:

 Direct Mapping
 Fully Associative Mapping
 Set Associative Mapping

Direct Mapping
In direct mapping physical address is divided into three parts i.e., Tag bits, Cache Line
Number and Byte offset. The bits in the cache line number represents the cache line in which
the content is present whereas the bits in tag are the identification bits that represents
which block of main memory is present in cache. The bits in the byte offset decides in which
byte of the identified block the required content is present.

Tag Number of Cache Lines Byte Offset

Cache Line Number = Main Memory block Number % Number of Blocks in Cache

Fully Associative Mapping: In fully associative mapping address is divided into two parts i.e., Tag bits
and Byte offset. The tag bits identify that which memory block is present and bits in the byte offset
field decides in which byte of the block the required content is present.

Tag Byte Offset

Set Associative Mapping
In set associative mapping the cache blocks are divided in sets. It divides address into three
parts i.e., Tag bits, set number and byte offset. The bits in set number decides that in which
set of the cache the required block is present and tag bits identify which block of the main
memory is present. The bits in the byte offset field gives us the byte of the block in which the
content is present.

Tag Set Number Byte Offset

Cache Set Number = Main Memory block number % Number of sets in cache