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Coa 2

The document is a question bank focused on Computer Organization and Architecture, covering various topics such as microinstruction formats, cache memory techniques, I/O operations, and pipeline processing. It includes questions on the design and comparison of different architectures, memory organization, and specific algorithms like Booth's for multiplication. The questions aim to assess understanding of both theoretical concepts and practical applications in computer architecture.

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6 views2 pages

Coa 2

The document is a question bank focused on Computer Organization and Architecture, covering various topics such as microinstruction formats, cache memory techniques, I/O operations, and pipeline processing. It includes questions on the design and comparison of different architectures, memory organization, and specific algorithms like Booth's for multiplication. The questions aim to assess understanding of both theoretical concepts and practical applications in computer architecture.

Uploaded by

validreason4excuse
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Question Bank-II

Computer Organization and Architecture

1. Discuss the role of next address generator.

2. Difference between normal instruction format and microinstruction format.

3. Explain how the mapping from an instruction code to a microinstruction address can
be done by means of a read-only memory. What is the advantage of this method.

4. Consider 9-bits microoperation field, 4 bits branching a 7-bit address field. Design the
microinstruction format for the following operations: ADD, AND, SHR.

5. Explain the difference between hardwired control and microprogrammed control. Is it


possible to have a hardwired control associated with a control memory.

6. Consider a CPU address of 20 bits and you are requiring interfacing 6 RAMs and 1 ROM
of 2k*16. Identify the number of address line used and demonstrate it with an interfacing
diagram

7. Discuss different mapping techniques in a cache memory.

8. A cache memory is accessed for 11, 9, 8 hits with reference to 12 instructions. The hit
time is 100ns and the miss time is 300ns. Develop a comparison table for the above three
cases with hit time, miss time, execution time and delay.

9. Describe with a neat diagram, how multiple matched words can be read out from the
associative memory.

10. A digital computer has a memory unit of 64k x16 and a cache memory of 1K words.
The cache uses direct mapping with a block size of four words. How many bits are there
in tag, index, block and word fields of the address format.

11. Discuss about the RAM and ROM chips and the role of chip select in memory
organization.

12. Discuss importance of the cache memory. Consider a cache memory of 512 x12,
implement two way set associative mapping for index 001 tag 01, index 001 tag 02, index
770 tag 02, index 770 tag 00.

13. Explain the concept of programmed I/O and interrupt initiated I/O.

14.Compare between polling and daisy chaining priority in interrupts.

15. Explain with a diagram the data transfer from I/O device to CPU. Determine the
procedure for setting and clearing the flag bit.

16. Discuss in details about DMA operation and role of DMA controller.
17. Distinguish between SISD, MISD, SIMD and MIMD computer architectures for parallel
processing.

18. Consider a four-segment pipeline to complete six tasks and if task requires 1 µsec,
find total clock cycles and speed up ratio of pipeline processing over non pipeline
processing. Implement the space time diagram for pipeline operation.

19. Discuss arithmetic pipeline with an operative diagram for floating point addition and
subtraction.

20. Explain with a flowchart the operation of four segment CPU instruction pipeline.

21. Discuss pipeline processing architecture with a diagram for the operation Ai +Bi +Ci
for i= 1,2,3,….7. Considering three segments find the clock cycles to complete the
operation.

22. Implement the flowchart of booth algorithm for multiplication of signed – 2’s comple
ment numbers. Multiply (-5) and (-7) using booth algorithm.

23. Explain pipelining and vector processing

24. Advantage of pipeline architecture over non pipeline architecture.

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