INTERRUPTS

What are Interrupts?

Interrupts are signals that temporarily pause the normal execution of a program to allow the
CPU to deal with urgent tasks or events. Once the interrupt is serviced, the CPU resumes the
original program.

Sources of Interrupts

Interrupts can be caused by:

1. Internal Events (Within the Microprocessor):

o Example: Divide-by-zero error.
o Response: The microprocessor immediately halts the current program and
executes the interrupt service routine (ISR) for the error.
2. Software Instructions:
o These are interrupt instructions (like INT in 8086).
o Response: The CPU finishes the current instruction and then handles the
interrupt.
3. External Hardware Events:
o Example: A keyboard key press or input from a sensor.
o Response: The CPU completes the current instruction and then acknowledges the
hardware interrupt.

Why Interrupts Are Useful

• Efficient use of CPU time.

• React quickly to important or real-time events.
• Avoid constant polling (wasting CPU cycles checking status repeatedly).

What is the Interrupt Vector Table (IVT)?

• The Interrupt Vector Table is a special memory area in the first 1 KB of memory
(from address 0000:0000 to 0000:03FFh).
• It contains pointers to interrupt service routines (ISRs) for all possible interrupts.

Structure of IVT
 • The IVT has 256 entries (0 to 255) for 256 interrupt vectors.
• Each entry = 4 bytes:
o 2 bytes for IP (Instruction Pointer)
o 2 bytes for CS (Code Segment)
• So, total size = 256 vectors × 4 bytes = 1024 bytes = 1 KB

Memory Layout

You can imagine the IVT like this:

Memory Address Contents Description

0000:0000 IP for IV #0 Lower 2 bytes of pointer
0000:0002 CS for IV #0 Upper 2 bytes of pointer
0000:0004 IP for IV #1
0000:0006 CS for IV #1
... ...
0000:03FC IP for IV #255 Last vector
0000:03FE CS for IV #255

Each 4-byte block = one vector. So vector #n is at:

Address = n × 4

Reserved vs User-defined Vectors

• Vectors 0 – 31 (Interrupt numbers 0 to 31) are reserved by Intel for predefined

exceptions and interrupts (e.g., divide-by-zero, overflow, etc.).
• Vectors 32 – 255 (Interrupt numbers 32 to 255) are available for user-defined
interrupts, like for external devices or software interrupts.

Example Breakdown

Say you have this memory section:

00008 : IPL (Instruction Pointer Low)

00009 : IPH (Instruction Pointer High)
0000A : CSL (Code Segment Low)
0000B : CSH (Code Segment High)

This would be for Interrupt Vector #2 because:

• IV #2 = 2 × 4 = address 0008
 • The ISR address is built from:
o IP = contents at 0008 (low) and 0009 (high)
o CS = contents at 000A (low) and 000B (high)

Steps the 8086/8088 Performs to Service an Interrupt (Real

Mode)
When an interrupt occurs (from hardware, software, or internal error), the microprocessor does
the following automatically:

1. Save Current CPU State to Stack

This ensures that when the ISR (Interrupt Service Routine) is done, the CPU can return to the
interrupted program exactly where it left off.

Step What Happens Why It's Needed

1 PUSHF → Push FLAGS register Save the current CPU status flags
2 Clear IF (Interrupt Flag) → IF = 0 Disable further maskable interrupts
3 Clear TF (Trap Flag) → TF = 0 Turn off single-step debugging mode
4 PUSH CS Save current Code Segment (CS)
5 PUSH IP Save current Instruction Pointer (IP)

2. Jump to the Interrupt Handler

Now, the microprocessor fetches the address of the ISR from the Interrupt Vector Table
(IVT):

Step What Happens Description

6 IP = [4 × n] Set IP to address stored at 4×n (low 2 bytes)
7 CS = [4 × n + 2] Set CS to address stored at 4×n + 2 (high 2 bytes)

Where n = interrupt number.

This causes a far jump to the ISR address.

3. Save and Use Internal Registers (if needed)

In the ISR (which you write), it's common to:

Step Instruction Why

8 PUSH AX, etc. Save registers
9 ISR Code Handle the event
10 POP AX, etc. Restore registers

These pushes/pops are not automatic—you must add them in your ISR if you use registers.

4. Return to Main Program Using IRET

What
Step Description
Happens
IRET
Pops IP, CS, and FLAGS from stack, returning execution to where it was
11
interrupted

Summary Flow
MAIN PROGRAM
↓
INTERRUPT OCCURS
↓
[Auto] PUSH FLAGS
[Auto] Clear IF, TF
[Auto] PUSH CS
[Auto] PUSH IP
[Auto] Get new CS:IP from IVT
↓
INTERRUPT SERVICE ROUTINE
[Optional] PUSH Registers
ISR CODE
[Optional] POP Registers
IRET
↓
MAIN PROGRAM CONTINUES

Why Clearing IF and TF?

• IF (Interrupt Flag) = 0 disables maskable interrupts so no other interrupt disturbs the
current ISR.
• TF (Trap Flag) = 0 disables single-step debugging (used for step-by-step execution).
Types of Interrupts in 8086/8088
There are four major categories:

1. Internal Interrupts (Exceptions)

• Generated automatically by the CPU due to errors or exceptional conditions during

program execution.
• These are also called exceptions.
• They use Intel-reserved interrupt vectors (0–31).

Examples:

Interrupt Vector # Description

INT 0 0 Divide Error – division by 0 or result too large
INT 6 6 Invalid Opcode – illegal/unknown instruction
INT 7 7 Coprocessor Not Present – no FPU, but ESC or WAIT used
INT 8 8 Double Fault – two faults at once (rare but serious)

Example:

MOV AX, 0900h

MOV CL, 2
DIV CL ; AL = 0x48, AH = 0 (no error)

But if you write:

MOV CL, 0
DIV CL ; INT 0 (Divide by Zero)

2. NON-MASKABLE INTERRUPT (NMI)

What is NMI?

• NMI is a special interrupt input pin on the 8086/8088 microprocessor.

• It is used to handle critical and emergency conditions (e.g., hardware failure, memory
parity error, power failure warning).
• Unlike other interrupts, NMI cannot be disabled using software (like CLI to clear the IF
flag).

NMI Pin and Edge Triggering

• The NMI pin is edge-triggered:

o It triggers an interrupt on a rising edge (0 → 1 transition).
o Before this edge, the pin must be held LOW (0) for at least 2 clock cycles.
o After the edge, the pin must be held HIGH (1) until it is recognized by the CPU.

Clock Cycle View:

_________ __________
|_____|
NMI Pin ↑ Rising Edge → Interrupt

How It Works (Step-by-Step)

Step Action
1 A 0→1 edge occurs on the NMI pin.
2 The microprocessor completes the current instruction.
3 The CPU then responds by pushing FLAGS, CS, and IP onto the stack.
4 The CPU clears the IF and TF flags.
It fetches the Interrupt Vector #2 from the Interrupt Vector Table (at memory
5
00008h–0000Bh).
6 CPU performs a far jump to the ISR (Interrupt Service Routine) using the new CS:IP.
7 The ISR executes, then finishes with an IRET instruction.
Step Action
8 Execution returns to the interrupted program.

Important Points to Remember

Feature Detail
Interrupt Vector Fixed at #2 (address 00008h–0000Bh)
Maskable ❌ No – cannot be disabled
Trigger Type Edge-triggered (positive edge)
Use Case Critical errors like power failure, parity errors
Priority Second only to internal (exception) interrupts
Recognition Delay Must remain LOW for 2 cycles before edge

Interrupt Vector Table (IVT) Entry for NMI

Vector # Address Contents

2 00008h (IPL) Offset of ISR
0000Ah (CSL) Segment of ISR

So NMI jumps to:

CS:IP = WORD at 0000Ah : WORD at 00008h

Example Scenario

Let’s say a power failure detection circuit is connected to the NMI pin. When power drops
below a safe level:

• The hardware asserts a 0 → 1 edge on the NMI pin.

• 8086 finishes current instruction and services the NMI.
• It jumps to a predefined ISR (e.g., saving register states to memory).
• ISR ends with IRET to resume operation (if possible).

Would you like help writing an example ISR for NMI in Assembly, or how to connect and test
NMI on a real system like with a timer or custom hardware circuit?

3. SOFTWARE INTERRUPT: BOUND Instruction (INT 5)

Purpose of BOUND

The BOUND instruction checks whether the value in a register lies within a lower and upper
bound stored in memory.
If the value is out of bounds, it triggers a software interrupt: INT 5.

Syntax:
BOUND reg16, mem

• reg16 is a 16-bit general-purpose register (like AX, BX, etc.)

• mem is a memory address containing two 16-bit words:
o Lower Bound → [mem]
o Upper Bound → [mem+2]

Operation:
IF (reg16 < [mem]) OR (reg16 > [mem+2])
THEN Interrupt 5 occurs (OUT OF BOUND)
ELSE
No interrupt (IN BOUND)

Example You Gave

Instruction:
BOUND AX, [0250h]

Given:

Register / Memory Value

AX 4050h
WORD [0250h] 2030h ⟹ Lower bound (30 20h) = 2030h
WORD [0252h] 6070h ⟹ Upper bound (70 60h) = 6070h

Now compare:

AX = 4050h

Lower Bound = 2030h

Upper Bound = 6070h
Result: 2030h < 4050h < 6070h

In this case, NO interrupt occurs, because AX is within bounds.

Now Modify the Example

Suppose:

AX = 7080h

Then:

7080h > 6070h → AX is OUT OF BOUNDS

Interrupt 5 (INT 5) will occur.

Notes on INT 5
• INT 5 is a software interrupt typically used for print-screen on original IBM PC (default
behavior), but here it's repurposed by BOUND instruction to signal a bounds check
failure.
• It can be handled by writing an ISR (Interrupt Service Routine) at vector 5 →
memory location 00014h–00017h (4 bytes: IP + CS).

Memory View You Mentioned

If memory at 0250h holds:

Address Value Meaning

0250h 30h Lower byte of lower bound
0251h 20h Higher byte of lower bound → 2030h
0252h 70h Lower byte of upper bound
0253h 60h Higher byte of upper bound → 6070h

This confirms:

BOUND AX, [0250h] ; AX compared with range 2030h–6070h

Summary
Condition Result
AX within [2030h, 6070h] No interrupt
AX < 2030h or AX > 6070h INT 5 occurs

SOFTWARE INTERRUPTS IN 8086

1. INTO – Interrupt on Overflow

Purpose:
Triggers an interrupt only if the Overflow Flag (OF) = 1.

Instruction:

INTO

Behavior:

IF OF == 1 THEN
Trigger INT 4 ; i.e., call interrupt vector #4
ELSE
Continue normal execution

Use Case:
To handle overflow conditions after signed arithmetic operations, e.g., after ADD, SUB.

Note: OF is set automatically if an overflow occurs in arithmetic.

2. INT n – General Software Interrupt

Purpose:
Triggers interrupt vector #n, where n = 0 to 255.

Instruction:

INT n ; e.g., INT 21h for DOS calls, INT 10h for video

What happens during INT n?

Step Action
1 PUSHF – Push FLAGS register
Step Action
2 Clear IF and TF flags (disable interrupts and trap)
3 PUSH CS – Push Code Segment
4 PUSH IP – Push Instruction Pointer
5 Load IP from memory (4 * n)
6 Load CS from memory (4 * n + 2)
7 Jump to ISR (Interrupt Service Routine)

3. INT 3 – One-byte Breakpoint Interrupt

Instruction:

INT 3 ; opcode = CCh (1 byte)

Use Case:
Used by debuggers to insert a software breakpoint into the program.

• Special case of INT n, where n = 3

• It is a single-byte instruction (INT n is normally 2 bytes)

Returning from Interrupts

To resume execution after an interrupt, use:

IRET – Interrupt Return

IRET

What IRET does:

Step Action
1 POP IP
2 POP CS
3 POPF

This restores the state saved when the interrupt occurred and resumes program execution.
Quick Summary
Instruction Description Causes INT #
INTO Triggers interrupt if OF == 1 INT 4
INT n Triggers user-defined or system INT INT n
INT 3 One-byte software breakpoint INT 3
IRET Returns from an interrupt —

4. HARDWARE INTERRUPT (via INTR pin)

What is it?

A hardware interrupt is an interrupt generated by external hardware, such as:

• Keyboards
• Timers
• Peripheral controllers
• I/O devices

It signals the microprocessor through the INTR pin (Interrupt Request).

Key Characteristics:

Feature Details
Pin Used INTR (Interrupt Request)
Type Level-sensitive (must remain at logic 1 until acknowledged)
Maskable? ✅ Yes. Can be disabled by clearing the IF (Interrupt Flag)
Acknowledged by INTA (Interrupt Acknowledge) pulse from the CPU
Vector Source External device places interrupt vector type number on D7–D0
Returns using IRET (Interrupt Return Instruction)

Flow of a Hardware Interrupt (INTR):

1. Device sets INTR = 1

o External device holds INTR line high (logic 1)
o Must be level-sensitive → stays high until accepted
2. 8086 finishes current instruction
3. If IF = 1, CPU:
 oDisables further INTRs (IF ← 0)
oSends two pulses of INTA (Interrupt Acknowledge)
4. During 2nd INTA pulse:
o External device places interrupt type (0–255) on data bus D7–D0
o e.g., Type = 35 ⇒ jump to vector @ 4 × 35 = 008Ch
5. CPU performs steps like software interrupt (INT n):
o PUSHF (flags)
o Clear IF, TF
o PUSH CS
o PUSH IP
o Load IP & CSfrom IVT address (4 × interrupt type)
6. CPU executes ISR (Interrupt Service Routine)
7. At the end of ISR:
o IRET restores previous state (IP, CS, FLAGS)
o Re-enables INTR

Example

Let’s say an external device triggers an interrupt by:

• Setting INTR = 1
• During INTA cycle, provides interrupt type = 35

Then:

• CPU jumps to ISR whose address is stored at:

 o IP = word @ [008C]
o CS = word @ [008E]

(Recall: 4 × 35 = 008C)

Summary Table

Signal Direction Meaning

INTR Input Interrupt request from external device
INTA Output Acknowledge from CPU
D7–D0 Bidirectional Device places vector type during INTA

PRIORITY RESOLUTION OF INTERRUPTS

When multiple interrupts occur, the microprocessor must decide which interrupt to service
first. This is done based on two criteria:

1. Priority Based on Interrupt Type

Interrupt Type Priority Level

Internal Interrupt Highest priority
Non-Maskable Interrupt (NMI) Second highest
Software Interrupt Next
Hardware Interrupt Lowest priority

2️. Priority Based on Interrupt Vector Number

• Interrupt vector numbers range from 0 to 255

• Lower vector number → Higher priority
• Vector 0 is highest priority interrupt, vector 255 is lowest

Example of Priority Resolution in Action

• Suppose an external hardware interrupt of type 50 is currently being serviced.
• Which interrupts can preempt (interrupt) this ongoing interrupt?
Allowed to interrupt:

• Any internal interrupt (highest priority)

• Non-maskable interrupt (NMI)
• Any software interrupt (INT n)
• Any external hardware interrupt with vector number < 50

Blocked (masked out):

• External hardware interrupts with vector number ≥ 50

Summary Table of Interrupt Preemption When Handling

INT #50
Interrupt Type Can Interrupt?
Internal Interrupt Yes
Non-Maskable Interrupt (NMI) Yes
Software Interrupt Yes
External Hardware Interrupt # < 50 Yes
External Hardware Interrupt # ≥ 50 No (masked out)

Why Masking?

• To avoid interrupt storms or infinite nested interrupts of the same or lower priority.
• Ensures that only higher priority interrupts preempt the current service routine.

EXPANDING INTERRUPT STRUCTURE OF 8088/8086

MICROPROCESSOR
Background:

• The 8088/8086 microprocessor has only one INTR input pin for hardware interrupts
from I/O devices.
• Without expansion, only one device can be directly connected to this INTR line.
• To connect multiple interrupt sources, we need techniques to expand or multiplex the
interrupt signals.
Methods to Expand Interrupt Inputs:
1⃣ Using 74ALS244 Buffer

• The 74ALS244 is an octal buffer/line driver IC.

• It can be used to isolate and buffer multiple interrupt lines.
• However, the 74ALS244 alone does not prioritize or arbitrate multiple interrupts.
• It can be used in a simple setup where multiple devices connect through buffers to the
INTR line.
• Typically, this is limited and not suitable for complex systems with many devices.

2️⃣ Daisy-Chain Method

• Multiple interrupt devices are connected in a serial chain (daisy chain).

• Interrupt requests flow through devices in a chain; priority is resolved by the device’s
position in the chain.
• The first device in the chain has the highest priority, the last device the lowest.
• When an interrupt occurs, the microprocessor acknowledges it, and the chain passes the
acknowledge signal along.
• Each device can pass or hold the acknowledge based on whether it initiated the interrupt.

3️⃣ Using 8259 Programmable Interrupt Controller (PIC)

• The 8259 PIC is a dedicated interrupt controller IC designed to handle multiple

interrupts.
• It accepts interrupt requests from up to 8 devices and prioritizes them.
• It sends a single interrupt request to the microprocessor’s INTR pin.
• The 8259 supplies the interrupt vector number during the INTA cycles.
• Multiple 8259s can be cascaded to expand beyond 8 interrupts.
• This is the most common and effective method to expand interrupt handling.

Summary Table:
Method Description Priority Handling Scalability
74ALS244 Simple buffering of interrupt
None (no arbitration) Limited
Buffer lines
Daisy-Chain Serial connection of devices Priority by position Moderate
 Method Description Priority Handling Scalability
Programmable Interrupt Yes (software High
8259 PIC
Controller configurable) (cascadable)

1. Using 74ALS244 Buffer to Expand Interrupt Structure

Problem:

• The 8088/8086 microprocessor has only one INTR input pin.

• To connect multiple interrupting devices directly to the INTR pin is not feasible.
• Without expansion, only one device can interrupt the CPU.

Solution:

• Use 74ALS244 octal buffer/line driver IC to combine multiple interrupt lines from
different devices into the single INTR pin of the microprocessor.
How it Works:

• The 74ALS244 has 8 input lines and 8 corresponding outputs.

• Each input line is connected to an individual device’s interrupt request line.
• The outputs of the buffer are wired together (wired-OR configuration) and connected
to the microprocessor’s INTR pin.
• If any device’s interrupt input is high (logic 1), the combined output line to INTR will
be high, signaling the CPU that an interrupt is pending.
• This effectively combines multiple interrupt requests into a single interrupt input for
the microprocessor.

Important Notes:

• The 74ALS244 does not provide interrupt priority or arbitration.

• If multiple devices raise interrupts simultaneously, the microprocessor will see only one
interrupt signal via INTR.
• The software or hardware external to 74ALS244 must determine which device actually
caused the interrupt.
• Usually, the interrupting device places an interrupt vector number or signals priority
via additional logic or programmable interrupt controllers.

Basic Circuit Example:

Device 1 Interrupt ---> Input 1 of 74ALS244
Device 2 Interrupt ---> Input 2 of 74ALS244
...
Device 8 Interrupt ---> Input 8 of 74ALS244

Outputs of 74ALS244 (all 8 outputs) are wired together ---> INTR pin of 8086

Control pins of 74ALS244 (OE, G) are enabled to pass input to output.

Summary:

Feature Explanation
IC Used 74ALS244 Octal buffer/line driver
Number of Interrupt
Up to 8 (one per input pin)
Inputs
Priority Handling None (all inputs combined with wired-OR)
Interrupt Signal to CPU Single INTR pin, high if any device asserts interrupt
Use Case Simple expansion for multiple interrupt lines
Feature Explanation
Does not resolve which device caused interrupt; no priority
Limitation
mechanism

2. What is the Daisy-Chain Method for Interrupt

Expansion?
➤ Basic Idea:

The daisy-chain method connects the INTR (Interrupt Request) lines of multiple devices in a
chain, all leading to a single interrupt input pin on the microprocessor.

• Instead of assigning a separate interrupt line to each device, one interrupt line (INTR) is
shared.
• Devices signal interrupts in sequence, and software checks (polls) each device to find
who raised the interrupt.

Why Use Daisy-Chaining?

Advantages:

• Saves hardware lines – only one interrupt vector is needed.

• Flexible – can be expanded easily.
• Priority can be assigned by software (not fixed like hardware-based priority).

Trade-off:

• Requires software polling, so interrupt handling takes more time than fixed priority
hardware like 8259A.

Using 8255 in Mode 1 with Interrupts

8255 Mode 1: Input or Output with Handshaking + Interrupt Capability

Each port (A or B) in Mode 1 supports:

• Handshake lines (like STB, ACK)

• Buffer status (IBF, OBF)
• Interrupt generation (INTR)
• Interrupt enable (INTE) — this is a bit in Port C.

A. Mode 1 Input (e.g., PORT A or B)

Signal Meaning
STB Strobe – tells 8255 data is available
IBF Input Buffer Full – shows data received
INTR Becomes 1 when IBF is full AND INTE is enabled
INTE Software-set bit (bit 4 or bit 2 of Port C) – enables interrupt

To activate interrupt for Port A input:

• Set bit 4 of Port C = 1 (INTE A)

• Example: Command Byte B = 09h = 00001001

To activate interrupt for Port B input:

• Set bit 2 of Port C = 1 (INTE B)

• Example: Command Byte B = 05h = 00000101
B. Mode 1 Output (e.g., PORT A or B)
Signal Meaning
OBF Output Buffer Full – shows data is written to buffer
ACK Acknowledge – confirms data was read by external device
INTR Becomes 1 when OBF is full AND INTE is enabled
INTE Software-set bit (bit 6 or bit 2 of Port C) – enables interrupt

To activate interrupt for Port A output:

• Set bit 6 of Port C = 1

• Example: Command Byte B = 0Dh = 00001101

To activate interrupt for Port B output:

• Set bit 2 of Port C = 1

• Example: Command Byte B = 05h

4. Connecting Multiple 8255s Using Daisy-Chain Interrupts

Imagine you have 2 x 8255 chips. Each one has INTR outputs from Port A and B.

How They're Chained:

INTR_A1 ---+
INTR_B1 ---|\
| \
| +--> To CPU's INTR
INTR_A2 ---| /
INTR_B2 ---+/

• If any one of the INTRs becomes 1, the combined signal to CPU's INTR pin goes high.
• CPU then executes ISR (Interrupt Service Routine).
• Inside ISR, the CPU polls each 8255 and each INTR line to find the source of the
interrupt.

5. Software Priority (Polling)

Since many devices share one interrupt line:

• After the CPU receives an interrupt, it checks:

1. Is 8255 #1's Port A interrupt pending?
2. If not, check 8255 #1's Port B.
3. Then 8255 #2's Port A, and so on.

This is software-based priority, and it can be written to suit your application’s needs.

6. Comparison With Hardware Methods (e.g., 8259)

Feature Daisy-Chaining 8259 PIC
Hardware lines One shared interrupt line One interrupt line per device or cascaded 8259s
Priority Software-controlled Hardware-controlled
Response Time Slower (due to polling) Faster
Complexity Simpler hardware More complex but powerful

Summary
• Daisy-chaining is a method to expand interrupt capability using minimal lines.
• 8255 in Mode 1 supports interrupts via Port C bits (INTE).
• You control interrupts via Command Byte B by setting bits in Port C.
• All INTRs go to a single CPU line, and the ISR uses polling to find the interrupt source.

First, What Is Port C in 8255?

Port C has 8 bits (PC7 to PC0) and is used for:

• Handshaking/control signals (like STB, ACK, IBF, OBF)

• Enabling interrupts (using bits called INTE A, INTE B)

We can set or reset individual bits of Port C using a special control word called
Command Byte B (also known as Bit Set/Reset (BSR) Mode).

What Is Command Byte B (Bit Set/Reset Mode)?

Format (8 bits):
D7 D6 D5 D4 D3 D2 D1 D0
0 x x x B B B S

• D7 = 0 → This selects BSR mode (Bit Set/Reset mode)

• BBB = Bit number to modify (000 for PC0, ..., 111 for PC7)
• S = 1 to SET the bit, S = 0 to RESET the bit

How It Works – With Examples

To activate interrupt for Port A (Input Mode)

Interrupt Enable A = PC4

Set bit 4 →

• BBB = 100 (for PC4)

• S = 1 → set bit

Command Byte = 00001001 = 09h

MOV AL, 09h

OUT CONTROL_PORT, AL ; Set PC4 = 1 → INTE A enabled
To activate interrupt for Port B (Input Mode)

Interrupt Enable B = PC2

Set bit 2️ →

• BBB = 010 (for PC2)

• S=1

Command Byte = 00000101 = 05h

MOV AL, 05h

OUT CONTROL_PORT, AL ; Set PC2 = 1 → INTE B enabled
To activate interrupt for Port A (Output Mode)

Interrupt Enable A = PC6

Set bit 6 →

• BBB = 110
• S=1

Command Byte = 00001101 = 0Dh

MOV AL, 0Dh

OUT CONTROL_PORT, AL ; Set PC6 = 1 → INTE A for Output
To activate interrupt for Port B (Output Mode)

Interrupt Enable B = again PC2 (same bit used)

So again:

Command Byte = 00000101 = 05h

Summary Table
Purpose Bit to Set Bit No. (BBB) Command Byte (Bin) Hex
INTE A (Input) – PC4 PC4 100 00001001 09h
INTE B (Input) – PC2 PC2 010 00000101 05h
INTE A (Output) – PC6 PC6 110 00001101 0Dh
INTE B (Output) – PC2 PC2 010 00000101 05h

3. What is the 8259A PIC?

The 8259A is a hardware chip used to handle interrupts in a microprocessor system, especially
in 8085 and 8088-based systems. It helps manage multiple interrupt requests (IR0–IR7) and
prioritizes them so the CPU can process them efficiently.

It can operate in single mode or in cascaded mode (master + slave PICs).

2. Pin Functions (Simplified)
Pin Function
IR0–IR7 8 interrupt request inputs
INT Sends interrupt signal to CPU (INTR)
INTA Acknowledge from CPU when it’s ready to service
D7–D0 Data bus (for communication with CPU)
A0 Selects which command word is being written
CS Chip select (active low)
RD, WR Read/write control
SP/EN Indicates master (SP=1) or slave (SP=0)
CAS0–CAS2 Cascade lines to identify slave

3. Initialization Command Words (ICWs)

KEY CONCEPT:
ICWs (Initialization - Setup Phase)

1. ICW1

o First command sent to initialize the PIC

o Sets: Trigger mode (edge/level), Cascade/Single mode, ICW4 requirement
o Example: OUT 20h, AL (where AL = 00010011b for edge-triggered, single
PIC, ICW4 needed)
2. ICW2

o Defines the base interrupt vector number (e.g., IR0 = 08h, IR1 = 09h,
etc.)
o Example: OUT 21h, AL (AL = 08h → INT 08h for IR0)
3. ICW3 (Only in Cascade Mode)

o Master: Specifies which IR lines have slaves (e.g., 00000100b = slave on

IR2)
o Slave: Specifies its ID (e.g., 00000010b = connected to master’s IR2)
4. ICW4 (Optional)

o Configures advanced modes:

 ▪ 8086/8088 mode (µPM = 1)
▪ Auto-EOI (AEOI = 1)
▪ Buffered Mode (BUF = 1)
o Example: OUT 21h, AL (AL = 00000001b for 8086 mode, normal EOI)

OCWs (Runtime Control)

1. OCW1

o Masks/unmasks specific IRQs (e.g., OUT 21h, AL with AL = 11111110b to

unmask IR0).
2. OCW2

o Controls EOI (End of Interrupt) and priority rotation:

▪ 20h = Non-specific EOI (clears highest-priority ISR bit)

▪ Example: OUT 20h, AL (AL = 20h to signal EOI).

3. OCW3

o Polling mode / Read IRR/ISR registers:

▪ Example: OUT 20h, AL (AL = 0Bh to read ISR).

Key Differences

ICWs OCWs

Sent once during PIC setup Used repeatedly during operation

Configure PIC behavior Control interrupts at runtime

4 ICWs (ICW1–ICW4) 3 OCWs (OCW1–OCW3)

Example: OUT 20h, 11h (ICW1) Example: OUT 20h, 20h (OCW2 EOI)
When to Use

• ICWs: At boot (e.g., BIOS sets up PIC).

• OCWs: During OS/application runtime (e.g., masking IRQs, sending EOI).

This ensures the PIC knows how to handle interrupts (ICWs) and how to manage
them dynamically (OCWs).

ICW1

Defines the basic operating mode:

Bit Meaning
D0 – IC4 1 = ICW4 is required
D1 – SNGL 0 = Cascade mode, 1 = Single
D3 – LTIM 0 = Edge-triggered, 1 = Level-triggered
Others – ADI, A5–A7 Don't care (for 8088)

ICW2

This sets the base address (T7–T3) of the Interrupt Vector Table (used by 8088/8086). Each
interrupt adds 1 to the base.

• For Master: 60h = 0110 0000 = Vectors 60h–67h

• For Slave: 68h = 0110 1000 = Vectors 68h–6Fh
ICW3

This defines the Master-Slave relationship:

• For Master:
o Bits D0–D7: Each bit represents whether a slave is connected to IR0–IR7
o Example: 00100000 = slave connected to IR5
• For Slave:
o Bits D0–D2: Give the ID of which IR line the slave is connected to on the master
o Example: 101 = connected to IR5

ICW4

Defines additional options:

 Bit Meaning
D0 – µPM 1 = 8088 mode
D1 – AEOI 1 = Auto End of Interrupt
D2 – M/S 1 = Master, 0 = Slave
D3 – BUF 1 = Buffered mode
D4 – SFNM 1 = Special Fully Nested Mode

4. Initialization Process Example

Let’s walk through this example:

Master

ICW1: 11h = 00010001

• IC4 = 1 → ICW4 is needed

• SNGL = 0 → Cascade mode
• LTIM = 0 → Edge-triggered

ICW2: 60h = 01100000

• Interrupt vector base = 60h (IR0 = 60h, IR1 = 61h, etc.)

ICW3: 20h = 00100000

• Slave is connected at IR5

ICW4: 1Fh = 00011111

• µPM = 1 (8088)
• AEOI = 1
• BUF = 1 (Buffered)
• M/S = 1 (This is Master)
• SFNM = 1

Slave

ICW1: 19h = 00011001

• Cascade mode
• ICW4 needed
 • LTIM = 1 → Level-triggered

ICW2: 68h = 01101000

• Vector base = 68h (IR0 = 68h, IR1 = 69h…)

ICW3: 05h = 00000101

• Slave ID = 5 (connected to IR5 on master)

ICW4: 19h = 00011001

• µPM = 1 (8088)
• AEOI = 0 (Normal EOI)
• BUF = 1, M/S = 0 (Slave)
• SFNM = 1