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Computer_Architecture_Module_1_2_Notes

The document compares RISC and CISC architectures, highlighting their differences in instruction complexity, execution speed, and architecture design. It also discusses pipelining, memory hierarchy, Direct Memory Access (DMA), control units, inter-processor communication, memory interleaving, and cache mapping and replacement algorithms, emphasizing their roles in improving performance and efficiency in computing systems.

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Akshaya Kumar Gardia
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5 views

Computer_Architecture_Module_1_2_Notes

The document compares RISC and CISC architectures, highlighting their differences in instruction complexity, execution speed, and architecture design. It also discusses pipelining, memory hierarchy, Direct Memory Access (DMA), control units, inter-processor communication, memory interleaving, and cache mapping and replacement algorithms, emphasizing their roles in improving performance and efficiency in computing systems.

Uploaded by

Akshaya Kumar Gardia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1.

RISC vs CISC

RISC (Reduced Instruction Set Computer):


- Simple instructions, one per cycle
- Fixed instruction length
- Load/store architecture
- Example: ARM, MIPS

CISC (Complex Instruction Set Computer):


- Complex instructions, multiple cycles
- Variable instruction length
- Memory-to-memory operations
- Example: Intel x86

Comparison Table:
- Instruction Count: RISC < CISC
- Execution Speed: RISC > CISC
- Complexity: RISC < CISC

2. Pipelining

Pipelining is a technique where multiple instructions are overlapped in execution.

Stages:
- IF: Instruction Fetch
- ID: Instruction Decode
- EX: Execute
- MEM: Memory Access
- WB: Write Back

Hazards:
- Data Hazard (RAW, WAR, WAW)
- Structural Hazard (resource conflict)
- Control Hazard (branch prediction)

Speedup = Time without pipeline / Time with pipeline

3. Memory Hierarchy
Memory levels:
- Registers (Fastest, Smallest)
- Cache (L1, L2, L3)
- Main Memory (RAM)
- Secondary Storage (HDD/SSD)

Principles:
- Temporal Locality: Recent data used again
- Spatial Locality: Nearby data used soon

Trade-off: Speed vs Cost vs Capacity

4. Direct Memory Access (DMA)

DMA allows peripherals to directly access memory without CPU involvement.

Modes:
- Burst Mode
- Cycle Stealing
- Transparent Mode

Benefits:
- CPU is free for other tasks
- Faster I/O operations

5. Hardwired vs Microprogrammed Control Unit

Hardwired:
- Control signals generated using combinational logic
- Fast but inflexible

Microprogrammed:
- Uses control memory to store microinstructions
- Easy to modify and flexible

Control Memory: ROM that stores microinstructions

Used in CISC processors

6. Inter-Processor Communication & Synchronization


Used in multiprocessor systems for cooperation between processors.

Communication:
- Shared memory
- Message passing

Synchronization:
- Locks
- Semaphores
- Barriers

Needed to avoid race conditions and ensure data consistency.

7. Memory Interleaving

Memory is divided into multiple banks accessed in parallel.

Types:
- High-order interleaving
- Low-order interleaving

Improves performance by overlapping memory accesses.

8. Cache Mapping & Replacement Algorithms

Cache Mapping:
- Direct Mapping: One block per line
- Associative Mapping: Any block to any line
- Set-Associative: Set of lines

Replacement Algorithms:
- FIFO: First-In-First-Out
- LRU: Least Recently Used
- Random: Replace any block

Used when cache is full and a new block needs space.

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