Applab 1
Applab 1
Registers window:
Instructions:
Assembly Program Structure
• AREA: This directive defines the name of the program and specifies the
memory area where the code resides. In this example, the code is marked
as READONLY to indicate that it should not be modified during program
execution.
• ENTRY: This directive specifies the entry point of the program. It marks
the first instruction to be executed when the program starts running.
• Define constants and variables: This section is where you can define any
constants or variables that will be used in your program. You can use the
EQU directive to assign values to constants.
Assembly Program Structure
• In ARM assembly programming, "DCD" and "DCB" are directives used to
allocate memory and define the initial values of data within that memory, with
the key difference being that DCD allocates 32-bit words (4 bytes) while DCB
allocates single bytes; essentially, DCD is for larger data types like integers,
while DCB is for characters or small values.
• DCD (Define Constant Doubleword):
• Used to allocate a block of memory where each element is a 32-bit word.
• Syntax: label DCD expression, expression, ...
• Example: my_array DCD 10, 20, 30 ; Allocates 3 32-bit words with values 10, 20, and 30
Assembly Program Structure
• DCB (Define Constant Byte):
• Used to allocate a block of memory where each element is a single byte.
• Syntax: label DCB expression, expression, ...
• Example: my_string DCB "Hello", 0 ; Allocates 6 bytes for the string "Hello" with a null
terminator
Assembly Program Structure
• Stack pointer and memory initialization: This section is optional but can be used to set up
the stack pointer (SP) and perform any necessary memory initialization before the program
starts.
• Reset vector: This is the starting point of your program. It typically includes initialization tasks
that need to be performed before the main program loop.
• Main Loop: This is the main program loop where the bulk of your program's logic resides. It
contains the instructions that will be executed repeatedly until a termination condition is met.
• Handle interrupts or other events: This section is optional but can be used to handle
interrupts or other events that may occur during program execution. You can define interrupt
service routines (ISRs) here.
Assembly Program Structure
• Check for program termination condition and exit: This section is optional but can be
used to check for a termination condition. If the condition is met, you can include an exit
routine or branch to the end of the program.
• Loop back to the main loop: After handling interrupts or checking termination
conditions, the program typically loops back to the main loop to continue its execution.
• Define interrupt service routines (ISRs): This section is optional but can be used to
define interrupt service routines (ISRs) that will be executed in response to specific
interrupts.
• END: This directive marks the end of the program.
Exmaple: PGM 1
AREA prg1,CODE,READONLY mov r3,#0x32
EXPORT __main mov r2,#0x00
mov r5,#0x02
ENTRY add r0,r3,#0x02
__main MOV R4,R0
MVN R4,R2
LDR R5,=0x10000004
mvn r0, #0x00
LDR R6,=0x02 LDR R1,=0x11223344
end
Program 2:
AREA prg1,CODE,READONLY
EXPORT __main
ENTRY
__main
LDR r3,=array ;loads the address of array into R3
LDR R4,[R3]
LDR r6,=array1 ;loads the address of array into R3
LDR R7,[R6]
Program 2:
LDR R5,=num1
STR R4,[R5]
array DCB ‘A’
array1 DCD 0x12345678
AREA DATA1,DATA,READWRITE
num1 DCD 0
end
INTRODUCTION TO ARM Cortex M3
PROCESSOR
• The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including:
• Thumb- 2 instruction set,
• low interrupt latency,
• hardware divide,
• interruptible/continuable multiple load and store instructions,
• automatic state save and restore for interrupts,
• tightly integrated interrupt controller with Wake-up Interrupt Controller and
• multiple core buses capable of simultaneous accesses.
INTRODUCTION TO ARM Cortex M3
PROCESSOR
• The processor has a Harvard architecture, which means that it has a separate
instruction bus and data bus.
• This allows instructions and data accesses to take place at the same time, and
as a result of this, the performance of the processor increases because data
accesses do not affect the instruction pipeline.
• This feature results in multiple bus interfaces on Cortex-M3, each with
optimized usage and the ability to be used simultaneously.
• The instruction and data buses share the same memory space (a unified
memory system).
• https://circuitdigest.com/microcontroller-projects/getting-started-with-
lpc2148-and-program-with-keil-uvision-to-blink-led