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Microprogrammed Control Unit

Chapter 3 discusses micro programmed control in computers, highlighting the use of two separate memories: main memory for user programs and control memory for fixed microinstructions. It explains the role of the control memory address register, control data register, and next address generator in executing microinstructions and managing address sequencing. The chapter also covers the design of the control unit, including multiplexers and microinstruction formats, emphasizing the advantages of micro programmed control in terms of flexibility and efficiency in executing different operations.

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2 views

Microprogrammed Control Unit

Chapter 3 discusses micro programmed control in computers, highlighting the use of two separate memories: main memory for user programs and control memory for fixed microinstructions. It explains the role of the control memory address register, control data register, and next address generator in executing microinstructions and managing address sequencing. The chapter also covers the design of the control unit, including multiplexers and microinstruction formats, emphasizing the advantages of micro programmed control in terms of flexibility and efficiency in executing different operations.

Uploaded by

DEEP ESHH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 3

Micro Programmed Control


A computer that employs a micro programmed control unit will have two separate memories: a
main memory and a control memory. The main memory is available to the user for storing the
program. The control memory holds a fixed microprogram that cannot be altered by the
occasional user. The microprogram consists of microinstructions that specify various internal
control signals for execution of register microoperations. Each machine instruction initials a
series of microinstructions in control memory.

The general configuration of a microprogrammed control unit is demonstrated in the block


diagram of Fig. 4-1.

The control memory is assumed to be a ROM, within which all control information is
permanently stored. The control memory address register specifies the address of the
microinstruction, and the control data register holds the microinstruction read from memory. The
microinstruction contains a control word that specifies one or more microoperations for the data
processor. Once these operations are executed, the control must determine the nest address.

The next address generator is sometimes called a microprogram sequencer, as it determines the
address sequence that is read from control memory. ;the address of the next microinstruction can
be specified in several ways, depending on the sequencer inputs.

The control data register holds the present microinstruction while the next address is computed
and read from memory. It allows the execution of the microoperations specified by the control
word simultaneously with the generation of the next microinstruction.

The main advantage of the micro programmed control is the fact that once the hardware
configuration is established; there should be no need for further hardware or wiring changes. If
we want to establish a different control sequence for the system, all we need to do is specify a
different set of microinstruction for control memory. The hardware configuration should not be
changed for different operations; the only thing that must be changed is the microprogram
residing in control memory.

Prepared by praches Acharya, Kantipur City College


ADDRESS SEQUENCING

The address sequencing capabilities required in control memory are:


1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on statues bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

Figure above shows a block diagram of address sequencer and the associated hardware needed
for selecting the next microinstruction. The diagram shows four different paths from which the
control address register (CAR) receive the address. The incremented increments the content of
the control address register by one, to select the next microinstruction in sequence. Branching is
achieved by specifying the branch address in one of the fields of the microinstruction.

Conditional branching is obtained by using part of the microinstruction to select a specific


statues bit in order to determine its condition. An external address is transferred into control
memory via a mapping logic circuit. The return address for a subroutine is stored in a special
register whose value is then used when the micro program wishes to return form the subroutine.

The branch logic provides decision-making capabilities in the control unit. The branch logic
hardware may be implemented in a variety of ways. The simplest way is to test the specified

Prepared by praches Acharya, Kantipur City College


condition and branch to the indicated address if the condition is met; otherwise, the address
register is incremented.

For each operation code there exists a micro program routine in control memory that executes
the instruction. One simple mapping process that converts the 4-bit operation code to a 7-bit
address for control memory is shown in fig. 4-3. This mapping consists of placing a 0 in the most
significant bit of the address, transferring the four operation code bits, and clearing the two lest
significant bits of the control address register.

Micro instructions can be saved by employing subroutines that use common sections of
microcode. Micro programs that use subroutines must have a provision for storing the return
address during a subroutine call and restoring the address during a subroutine return. This may
be accomplished by placing the incremented output from the control address register into a
subroutine register and branching to the beginning of the subroutine. The subroutine register can
then become the source for transferring the address for the return to the main routine.

DESIGN OF CONTROL UNIT


There are two multiplexers in the circuit shown below. The first multiplexer selects an address
from one of four sources and routes it into a control address register CAR. The second
multiplexer tests the value of a selected status bit and the result of the test is applied to an input
logic circuit. The output from CAR is incremented and applied to one of the multiplexer inputs
and to the subroutine register SBR. The other three inputs to multiplexer number 1 come from
the address field of the present microinstruction, from the output of SBR, and from an external
source that maps the instruction.

The CD (condition) field of the microinstruction selecting one of the status bits in the second
multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise, it is
equal to 0. The T value together with the two bits from the BR (branch) field go to an input logic
circuit. The input logic in a particular sequencer will determine the type of operations that are
available in the unit.

The input logic circuit in Fig. below has three inputs, I0, I1, and T, and three outputs, S0, S1 and
L. variables S0 and S1 select one of the source addresses for CAR. Variable L enables the load
input in SBR. The binary values of the two selection variables determine the path in the

Prepared by praches Acharya, Kantipur City College


multiplexer. For example, with S1 S0 = 10, multiplexer input number 2 is selected and
establishes a transfer path from SBR to CAR.

MICROPROGRAM EXAMPLE

MICROINSTRUCTION FORMAT

The microinstruction format for the control memory is shown in Fig. 4-6. The 20 bits of the
microinstruction are divided into four functional parts. The three fields F1, F2, and F3 specify
microoperations for the computer. The CD field selects status bit conditions. The BR field
specifies the type of branch to be used. The AD field contains a branch address. The address
field is seven bits wide, since the control memory has 128 words. The microoperations are
subdivided into three fields of three bits each. The CD (condition) field consists of two bits
which are encoded to specify four status bit conditions. The BR (branch) field consists of two
bits. It is used, in conjunction with address field AD, to choose the address of the next
microinstruction.

Prepared by praches Acharya, Kantipur City College

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