Microprocessors

& Microcontrollers

ER. BIKASH CHANDRA DAS (M. Tech, ITER)

Assistant professor, Department of ENTC,
Ajay Binay Institute of Technology,
CDA sector-1, Cuttack
 TABLE OF CONTENT

Contents:
MODULE-1: 8085 MICROPROCESSORS

1. INTRODUCTION:
2. IMPORTANT FEATURES OF 8085 MICROPROCESSORS:
3. PIN DIAGRAM OF 8085 MICROPROCESSORS:
4. PIN DESCRIPTION OF 8085 MICROPROCESSORS:
5. INTERNAL ARCHITECTURE OF 8085 MICROPROCESSORS:
6. INSTRUCTION SETS OF 8085 MICROPROCESSORS:
7. ADDRESSING MODE OF 8085 MICROPROCESSORS:
8. PROGRAMMING FOR 8085 MICROPROCESSORS
a) ASSEMBLY LANGUAGE FOR 8 BIT ADDITION:
b) ASSEMBLY LANGUAGE PROGRAMMING FOR 8 BIT ADDITION USING MEMORY LOCATION:
c) ASSEMBLY LANGUAGE PROGRAMMING FOR 8 BIT MULTIPLICATION RESULTING 16 BIT NUMBER:
d) ASSEMBLY LANGUAGE PROGRAMMING FOR DIVISION OF 8 BIT BY A 8 BIT NUMBER:
e) PROGRAM FOR FINDING THE SMALLEST NUMBERR FROM A GIVEN DATA:
f) PROGRAM TO FIND THE LARGEST NUMBER FROM A GIVEN DATA ARRAY:
g) PROGRAM FOR BINARY TO GRAY COAD CONVERSION:
9. TIMING DIAGRAM OF 8085 MICROPROCESSORS:
10. STACK AND SUBROUTIN:
11. MULTIPLE CHOICE QUESTION AND ANSWER:
12. ASSIGNMENT:

MODULE-2: 8086 MICROPROCESSORS

1. IMPORTANT FEATURES OF 8086 MICROPROCESSORS:

2. PIN DIAGRAM OF 8086 MICROPROCESSORS:
3. PIN DESCRIPTION OF 8086 MICROPROCESSORS:
4. INTERNAL ARCHITECTURE OF 8086 MICROPROCESSORS:
5. INSTRUCTION SETS OF 8086 MICROPROCESSORS:
6. ADDRESSING MODE OF 80865 MICROPROCESSORS:
7. PROGRAMMING FOR 8086 MICROPROCESSORS:
8. MINIMUM MODE CONFIGURATION OF 8086 MICROPROCESSORS:
9. MAXIMUM MODE CONFIGURATION OF 8086 MICROPROCESSORS:
10. INTERRUPT STRUCTURE OF 8086 MICROPROCESSOR:
11. MULTIPLE CHOICE QUESTION AND ANSWER:
12. ASSIGNMENT:

MODULE-3: INTERFACING DEVICES

1. INTRODUCTION:
2. 8255 PPI (PROGRAMMABLE PERIPHERAL INTERFACE):
➢ PIN DIAGRAM OF 8255 PPI:
➢ PIN DESCRIPTION OF 8255 PPI:
➢ INTERNAL ARCHITECTURE OF 8255 PPI:
3. 8257 DMA (DIRECT MEMORY ACCESS):
➢ PIN DIAGRAM OF 8257 DMA:
 TABLE OF CONTENT

➢ PIN DESCRIPTION OF 8257 DMA:

➢ INTERNAL ARCHITECTURE OF 8257 DMA:
4. 8259 PIC (PRIORITY INTERRUPT CONTROLLER):
➢ PIN DIAGRAM OF 8259 PIC:
➢ PIN DESCRIPTION OF 8259 PIC:
➢ INTERNAL ARCHITECTURE OF 8259 PIC:
5. 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter):
➢ PIN DIAGRAM OF 8251 USART:
➢ PIN DESCRIPTION OF 8251 USART:
➢ INTERNAL ARCHITECTURE OF 8251 USART:
6. SERIAL DATA TRANSFER FORMAT:
7. INTERFACING PROBLEM:
8. MULTIPLE CHOICE QUESTION AND ANSWER:
9. ASSIGNMENT:

MODULE-4: 8051 MICROCONTROLLERS

1. INTRODUCTION:
2. PIN DIAGRAM OF 8051 MICROPROCESSORS:
3. PIN DESCRIPTION OF 8051 MICROPROCESSORS:
4. INTERNAL ARCHITECTURE OF 8051 MICROPROCESSORS:
5. INSTRUCTION SETS OF 8051 MICROPROCESSORS:
6. ADDRESSING MODE OF 8051 MICROPROCESSORS:
7. MULTIPLE CHOICE QUESTION AND ANSWER:
8. ASSIGNMENT:

PREVIOUS YEAR QUESTION AND ANSWER

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MODULE-1:8085 MICROPROCESSORS

Introduction: It is multipurpose, programmable, clock driven, register based, electronics device

that takes the data in the form of binary, processes and the result is displayed at output device
or LCD display.

Important features of 8085 Microprocessor:

• The 8085 microprocessor is an 8-bit processor that means its data line is 8-bit and
address line is 16-bit.
• Its internal clock frequency is up-to 5MHz so that the processor takes about 0.2µsec to
complete an instruction.
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Pin diagram of 8085 Microprocessor:

Pin description for 8085 Microprocessor:

It consists of 40 pins and operates at +5V DC.

X1 & X2

• Pin no-1 & 2 are used as X1 & X2 respectively.

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• These are two external pins which are connected to an external crystal oscillator which
provides an internal clock frequency up-to 5MMHz to the processor so that the processor
takes about 0.2µsec to compute an instruction.

RESET IN’ & RESET OUT

• Pin no-36 & 3 are used as RESET IN’ & RESET OUT’ respectively.
• These pins are basically used to restart the processor if the program hangs in between.

SOD

• Pin no-4 is used as Serial Output Data pin.

• Through this pin the data from the processor is send to the output device or LCD screen.

SID

• Pin no-5 is used as Serial Input Data pin.

• Through this pin we can transfer the data from IO device to the processor.

TRAP

• Pin no-6 is used as TRAP pin.

• It is a non-maskable interrupt that means its bit line is always high and there are no logic
gates or flipflop to control this interrupt. So once this interrupt is activated the processor
will stop the current program and jump to some other program which is required at that
specific moment of time and till the completion of that specific program the processor
cannot return back to original program.

RST 7.5, RST 6.5 & RST 5.5

• Pin no-7, 8 & 9 are used as RST 7.5, RST 6.5 & RST 5.5 respectively.
• These are the maskable interrupt pins.
• Once this interrupt is activated the processor will stop the current program and jump to
some other program which is required at that specific moment of time and till the
completion of that specific program the processor return back to original program.

INTR

• Pin no-10 is used as Interrupt Request pin.

• This pin is used to receive an interrupt request signal. It is a type of maskable interrupt.

INTA’

• Pin no-11 is used as INTA’ (Interrupt acknowledgement) pin.

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• If the interrupt is activated then the processor will send an acknowledge message through

INTA’ pin i.e. INTA’=0, INTA=1.

AD0-AD7 & A8-A15

• Pin no-12 to pin no-19 are used as both data line and address line pin (AD0-AD7).
• Pin no-21 to pin no-28 are used as address line pin (A8-A15).
• That means in 8085 microprocessors have 8-bit data line and 16-bit address line.

VSS

• Pin no-1 is used as VSS or GND pin.

S0 &S1

• Pin no-29 and pin no-33 is used for S0 & S1 respectively.

• These are 2 status signal pins which are basically used to check read, write and opcode
operation, where S1 is used for memory read operation and S0 is used for memory write
operation.

S1 S0 OPERATION
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH

ALE

• Pin no-30 is used as ALE (Address Latch Enable) pin.

WR’

• Pin no-31 is used as WR’ pin.

• It is used for write operation (WR’=0, WR=1).

• It is basically used to separate the address from the address and data bus.
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RD'

• Pin no-32 is used as RD’ pin.

• It is a read signal used for read operation. It is also an active low signal

IO/M’

• Pin no-34 is used for Input Output/Memory’ pin.

• If the data is transferred to one processor to another processor then it is IO operation.
So, in that case IO/M’=1
• If the data is transferred within the processor itself that means either the data is
transferred to accumulator or to some other memory address or register so in that case
it is either a memory read or memory write operation so IO/M’=0.

READY

• Pin no.-35 is used as READY pin.

• This is an acknowledgment signal from the slower I/O devices or memory.
• When high, it indicates that the device is ready to transfer data, else the microprocessor
is in the wait state.

CLK

• Pin no-37 is used as CLK pin.

• This pin tells about the clock pulse.
• Through this pin we can connect to other digital IC pins and basically use to provide
square wave pulse or clock pulse or clock frequencies.

HOLD & HLDA

• Pin no-38 is used as HLDA and pin no-39 is used as HOLD pin.
• Once the HOLD pin is activated then the processor will not allow any external data to
interfere the current program and if the hold is successfully activated then the processor
will send an acknowledge message through the HLDA pin.

VCC

• Pin no-40 is used as VCC pin.

• Through VCC pin +5V DC supply is provided to the IC.
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INTERNAL ARCHITECTURE OF 8085 MICROPROCESSOR

The total internal architecture of 8085 microprocessor can be divided into 3 major units they
are;

i. Arithmetic and Logic Unit (ALU):

The main function of ALU is to perform arithmetic operation such as addition, subtraction,
multiplication and division etc. and logical operation such as AND, OR, EX-OR etc.
To ALU 3 other sub units are attached which helps in performing different arithmetic and
logical operation they are:
A. Temporary register:
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The main function of temporary register is to store the data temporary before the
data is transforming to ALU to performing different arithmetic and logically units.
B. Status flag:

The main function of status flag is to check the status of the output program or to
check whether the result is right or wrong. It consists of 8-bit out of which 5 are active
flags and three re undefined bits.
➢ Sine flag: After the arithmetic operation if the result is negative then sign
flag is tends to logic 1 otherwise it will tend to logic 0.
➢ Zero flag: After the arithmetic operation if the result is zero then zero flag
will tend to logic 1 otherwise it will tend to logic 0.
➢ Auxiliary flag: After the arithmetic operation if there is a carry from 3rd to
4th bit then auxiliary carry will tends to logic 1 otherwise it will tend to logic
0.
➢ Parity flag: After the arithmetic operation if the result of the sum contains
even no. of 1’s then parity flag will tend to logic 1 otherwise it will tend to
logic 0.
➢ Carry flag: After the arithmetic operation if the result is more than 8 bits
then there will be a carry from 7-8 bit so carry flag will tends to logic 1.

C. Accumulator:
The final result of arithmetic and logical operation is stored in accumulator.

ii. Sets of register:

Registers are temporary storing device and acts as flipflop. We can store the data in register
temporarily and we can delete it. In 8085 microprocessor there are 6 general purpose
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register they are B, C, D, E, H, L and each register can store 8-bits of data individually that
means B can store 8-bit of data, C can store 8-bits of data and so on. But in pair form i.e. BC,
DE, HL ARE STORES 16-bits of data. This are known as general purpose register because in
most of the programming we use these registers commonly for storing 16-bits or 8-bits of
data.
Special purpose register
These are 16-bits registers which are used for some specific purpose. The special
purpose registers are:
A. Stack pointer
o Stack: Stack is a set of memory location whose address is different from
main memory. We can transfer the data from main memory to stack
memory by push instruction and we can retrieve the data from stack
memory to main memory by pop instruction. The data transform from main
memory to stack memory by FIFO (First in First Out) sequence and is retrieve
from stack memory to main memory by LIFO (Last in Last Out) sequence.
o To locate a particular memory address, we take the help of stack pointer
and is given by LXI SP, 9904- load the content of stack pointer into the
memory address 9904.
B. Program counter
o It holds the address of the next instruction or it checks whether the address
for next instruction is available or not.
C. Increment decrement latch
o It is basically used for increment and decrement operation.

iii. Timing and control unit:

The main function of timing and control units is to check how much time the processor will
take to execute the operation. To the timing and control unit an external crystal oscillator is
attached which provide and internal clock frequency up-to 5MHz. So that the processor will
take a specific amount of time i.e. T=1/F, here F=5MHz so T=0.2µsec time is taken by the
processor to execute the operation.
To the timing and control units two other units are attached they are instruction register and
instruction decoder.

Instruction registers: The main function of instruction registers is to store to opcode of an

instruction.
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Instruction: Instructions are set of command given to the processor to perform a specific
operation.

e.g. MVI A, 38

Each instruction has 2 parts i.e. opcode and operand

▪ Opcode: The first part of instruction which specifies some task we done by the processor.
Here MVI is the opcode which means move immediately the data.
▪ Operand:The second part of instruction which is basically used to store the data or to
perform a memory read or memory write operation.
✓ Memory read: When the data is transfer to accumulator then that is the memory
read operation.
✓ Memory write: When the data is transferred to some other memory address apart
from accumulator then that is memory write.

Instruction decoder: Its main function is to convert the mnemonics to its machine code.

Mnemonics: Mnemonics are the literal language understood by user- or user-friendly

language.

INSTRUCTION SETS OF 8085 MICROPROCESSORS

Instructions are sets of commands given to the processor to perform a specific operation.
Each instruction can be defined into two parts one is the opcode and another is operand.
• According to word length: Word length means the no. of bits or bytes a specific
instruction occupies. Accordingly, there are 3-types i.e.1-byte, 2-byte, 3byte.
a) 1-byte: In 1-bytes instruction the opcode is define but the operand data is not
directly specified but is specified by some register.
e.g. ADD B- In this case the opcode is defined i.e. ADD which has got a machine
code of 8-bit, but the operand is specified by register so it is 1-byte instruction.
b) 2-byte: In 2-byte instruction opcode is present followed by 8-bit operand data.
e.g. MVI A, 30- In this case the opcode is defined i.e. MVI which has got a machine
code of 8-bit and the operand data is 30 which has the binary value 00110000 i.e.
8-bit. So, the total size is 16-bits and called 2-byte instruction.
c) 3-byte: In 3-byte instruction the opcode is present and followed by 16-bit operand
data.
e.g. STA 9100- In this case the opcode is defined i.e. STA which has got a machine
code of 8-bit and the operand data is 9100 which has the binary value
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1001000100000000 i.e. 16-bit. So, the total size is 24-bits and called 3-byte
instruction.
• According to operation: according to the type of operation it performs the total
instruction sets can be classified into 5 different types, they are
a) Data transform instruction: It is basically used for transferring the data from one
register to another register or register to memory without changing the content.
E.g. MOV A, B-Move the content of B registers to accumulator.
MOV A,34H-Move the 8-bit data 34H to accumulator.
b) Arithmetic instruction: These are basically used for arithmetic operation such as
addition, subtraction, multiplication, division, increment, decrement etc. In this case
the final result may change.
e.g. ADD B- Add the content of register B with the accumulator.
c) Logical instruction: These instructions are basically used for logical operation
such as ANA (AND), ORA (OR), XRA (XOR), CMP (COMPARE) etc.
d) Branch control instruction: The instruction under this group are basically used
for conditional or unconditional jump operation.
E.g.
JNZ- Jump if the counter data in the register C is not zero to label loop.
JNC- Jump if there is no carry or borrow to label loop.
e) IO and machine control: The instruction under this group are basically used for
controlling the device or for transferring the data from one device to another
device or for set or reset of the status flag or for stack operation comes under this
group.
e.g. HALT (to stop the program)
INO2 (to receive the data from port 02)
OUT01 (to transfer data through port 01)
STC (set the carry flag to logic-1)
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ADDRESSING MODE OF 8085 MICROPROCESSOR

It is the technique through which we are specifying data for operation or how the operand data
is specified accordingly in 8086 microprocessors. There are 8 different addressing mode
according to the type of operation it performs.

1. Register addressing mode

2. Immediate addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Implicit addressing mode
1. Register addressing mode: In this type of addressing mode the operand data is
not directly specified in the instruction itself but it is specified by some register.
E.g. MOV A, B- Move the content of B register to accumulator.
2. Immediate addressing mode: In this type of addressing mode the operand data
is directly specified in the instruction itself.
E.g. MOI A, 08H- Move immediately the data 08H to accumulator.
3. Direct addressing mode: In direct addressing mode the operand address is
directly specified in the instruction itself.
E.g. STA 9100-Stored the content of accumulator to memory address 9100.
4. Register indirect addressing mode: In this type of addressing mode the operand
data is not directly transferred to the accumulator; at first it stored in some
memory address and the transferred to the accumulator.
E.g. LXI H, 9100- Load the content of HL pair into the memory address 9100.
MOV A, M- Move the content of the memory address 9100 to accumulator.
5. Implicit addressing mode: There are certain instruction through which we can
automatically compare with the previous value of accumulator and the instruction
under this group comes under implicit addressing mode.
E.g. CMP M- Compare the content of memory with accumulator.
RAL- Rotate the content of accumulator to left by 1-bit.
RAR- Rotate the content of accumulator to right by 1-bit.
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ASSEMBLY LANGUAGE PROGRAMMING FOR 8 BIT ADDITION

LABEL MNEMONICS OPERANDS COMMENT
MVI A, 49 Move immediately the data49H to
accumulator A.
MVI C, 56 Move immediately the data 56H to register
C.
ADD C Add the content of register C with
accumulator A and the result is stored in
accumulator.
STA 9100 Store the content of accumulator into the
memory address 9100.
END
DATA:
1ST data= 49H
2nd data= 56H
RESULT in memory location 9100= 9F
OR
ASSEMBLY LANGUAGE PROGRAMMING FOR 8 BIT ADDITION USING MEMORY
LOCATION
LABEL MNEMONICS OPERANDS COMMENT
LXI H, 9100 Load the content of HL pair into the
memory address 9101.
MOV A, M Move the content of memory to
accumulator.
INX H Increment the content of HL pair by next
bit.
ADD M Add the content of memory with
accumulator and the result is stored in
accumulator.
STA 9103 Store the content of accumulator in to the
memory address 9103.
END
DATA:
Memory location 9101 = 49H
Memory location 9102 = 56H Result in Memory location 9103 = 9F
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ASSEMBLY LANGUAGE PROGRAMMING FOR 8 BIT MULTIPLICATION

RESULTING 16 BIT NUMBER.

LABEL MNEMONICS OPERANDS COMMENT

MVI E, 05 Move immediately the data 05 to
register E.
MVI C, 05 Move immediately the data 03 to
register C which is used for
counter operation.

MVI D, 00 Move the initial data 00 to

register D.

LXI H, 0000 Load the 16-bit data 0000 to HL

pair.

LOOP DAD D Add the content of HL pair with

DE pair and the result is stored in
HL pair.

DCR C Decrement the content of

register C by 1 bit.

JNZ “LOOP” Jump till the counter data in

register C is not zero to label
LOOP.

SHILD 9105 Store the content of HL pair into

the memory address 9105 &
9106.

END

RESULT:
In memory location 9105 =0F
In memory location 9106 =00
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ASSEMBLY LANGUAGE PROGRAMMING FOR DIVISION OF 8 BIT BY A 8 BIT

NUMBER.

LABEL MNEMONICS OPERAND COMMENT

MVI A, 13 Move the hexadecimal
equivalent of 13 to
accumulator A.
MVI B, 05 Move the hexadecimal
equivalent of 05 to
register B.
MVI C, 00 Move the initial data 00 to
register C, which is
basically used to store the
quotient.
LOOP SUB B Subtract the content of
register B from
accumulator A and the
result is stored in
accumulator.
INR C Increment the content of
register C by 1 bit.
CMP B Compare the content of
register B with
accumulator A.
JNC “LOOP” Jump if there is no carry or
borrow to label loop.

END

RESULT:
Quotient is in register= 03H
Remainder is in accumulator= 04H
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PROGRAM FOR FINDING THE SMALLEST NUMBERR FROM A GIVEN DATA

LABEL MNEMONICS OPERANDS COMMENT
LXI H, 9101 Load the content of HL pair into the memory
address 9101.
MOV C, M Move the content of memory to register C
which is used for counter operation.
INX H Increment the content of memory to
accumulator.
MOV A, M Move the content of memory to the
accumulator.
DCR C Decrement the content of register C by 1 bit.
INX H Increment the content of HL pair address by
next bit.
CMP M Compare the content of memory with
accumulator.
JC “AHED” Jump with carry or borrow to label “AHED”.
MOV A, M Move the content of memory to
accumulator.
DCR C Decrement the content of register C by 1 bit.
JNZ “LOOP” Jump in the counter data in the register C is
not zero to label loop.
STA 9300 Store the content of accumulator into the
memory address 9300.
END
DATA: RESULT:
In memory address 9101= 03H In memory address 9300= 58H
In memory address 9102= 86H
In memory address 9103= 58H
In memory address 9104= 75H
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PROGRAM TO FIND THE LARGEST NUMBER FROM A GIVEN DATA ARRAY

LABEL MNEMONICS OPEANDS COMMENT
LXI H, 9101 Load the content of HL pair into the
memory 9101.
MOV C, M Move the content of memory to the
register C which is used for count
operation.
SUB A Subtract the content of accumulator
from accumulator (A=0) and result is
stored in accumulator.
LOOP INX H Increment the content of HL pair
address by next bit.
CMP M Compare the content of memory with
accumulator.
JNC “AHED” Jump if there is no carry or borrow to
label “AHED”.
MOV A, M Move the content of memory to the
accumulator.
AHED DCR C Decrement the content of register C by
1 bit.
JNZ “LOOP” Jump till the counter data in register C
id not zero to label “LOOP”.
STA 9105 Store the content of accumulator to the
memory address 9105.
END

DATA: RESULT:
In memory address 9101= 03H In memory address 9105= A5H
In memory address 9102= 98H
In memory address 9103= A5H
In memory address 9104= 29H
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PROGRAM FOR BINARY TO GRAY COAD CONVERSION

LABEL MNEMONICS OPERAND COMMENT
MVI A, 48 Move immediately the data 48 to
accumulator A.
MOV C, A Move the content of accumulator to
register C.
STC Set the carry flag to logic -1.
CMC Complement of carry bit.
RAR C Rotate the content of accumulator to
right by 1 bit.
XRA X-OR of register C.
END
RESULT: Gray code is in accumulator= 6CH.

48 - 01001000

C - 01001000

STC - 101001000

CMC - 001001001

RAR - 0001001001

XRA - 001101101 => 6C

TIMING DIAGRAM
It is a graphical representation of instruction cycle or it shows how the control signals are
affected when we are performing an opcode operation r an execution operation.

Instruction cycle:

It is the total time required to read the opcode of an instruction from the memory and to
perform the execution operation.

Instruction cycle = Opcode fetch cycle + Execution cycle

o Opcode fetch cycle:

It is the total time required to read the opcode of an instruction from the memory.
Normally the opcode fetch cycle has got four T-states or Time period (T1, T2, T3, T4) during
which a specific operation is being perform.
▪ T1-state: During this state of machine cycle the address is read from the memory.
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▪ T2 & T3-state: During these states the hexadecimal code or the machine code of
an instruction is read from the memory.
▪ T4 state- This state is known as wait state or during this period the data is transferred
from the opcode fetch cycle to execution cycle.
o Execution cycle:
It is the total time required to perform the memory read or memory write operation.
In execution cycle the final result is stored so we do not require any wait state (time gap
for data overlap).
If the operand data is 8-bit then we required 3T states and if the operand data is 16-bit
then we required 6T states.
✓ During T1 state of execution cycle the address is read from the memory.
✓ During T2 & T3 states of execution cycle the operand data is read from the memory.

Q. If the external clock frequency is 5MHz then how much time the processor will take to
execute the operation

I. MVI A, 30
II. MOV A, B
III. LXI H, 9105

Solution: Given data f= 5MHz

.’. T = 1/f = 1/5MHz = 0.2µsec

I. MVI A, 30 = 4T+3T = 7T =7*0.2 µsec = 1.4 µsec

II. MOV A, B = 4T+0T = 4T = 4*0.2 µsec = 0.8 µsec
III. LXI H, 9105 = 4T+6T = 10T = 10*0.2 µsec = 2 µsec
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Timing diagram of opcode fetch cycle & ADD B

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Timing diagram of MVI A, 30& MVI B, 20

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Timing diagram of STA 9105

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Timing diagram of STA 9105 if the accumulator contains 50 H

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STACK AND SUBROUTIN:

Stack: Stack is the sets whose address is different from main memory address. We can transfer
the data from main memory to stack memory by PUSH instruction and the data is transferred
in FIFO sequence and we can retrieve the data from stack memory to main memory by POP
instruction and the data is retrieve by LIFO sequence.

Subroutine: Subroutine is a subtask or it is a small program in between the main program.

Q. Initialize the stack memory address 9906. Write a program to transfer the data from
main memory to stack & then retrieve it. Suppose the data contain in main memories are:
9101- 2050H, 9103- 3040H, 9105- 6070H.

Solution:

MNEMONICS OPERAND COMMENT

LXI SP, 9906

LXI B, 9901 Load the data in BC

register.
LXI D, 9903 Load the data in DE
register.
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LXI H, 9905 Load the data in HL

register.
PUSH B Store the data in BC
register.
PUSH D Store the data in DE
register.
PUSH H Store the data in register.

POP H Retrieve the data from

register.
POP D Retrieve the data from
register.
POP B Retrieve the data from
register.
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Multiple choice question answer:

1. The 8085 Up is
A) 16 bit
B) 8 bit
C) 20 bit
D) 32 bit
Answer: B
2. The address line of 8085 up is
A) 16 bit
B) 8 bit
C) 24 bit
D) none of these.
Answer: A
3. The function of ALU is
A) Arithmetic operation
B) Arithmetic and logical operation
C) Logical operation
D) None of these.
Answer: B
4. The function of crystal oscillator
A) providing internal clock frequency
B) impedance matching
C) reducing speed
D) Disconnecting ports
Answer: A
5. The no. Of general-purpose register in 8085 up is
A) 6
B) 5
C) 4
D) 3
Answer: A
6. The no. Of addressing mode in 8085 up is
A) 5
B) 4
C) 3
D) 2
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Answer: A
7. The no. Of instruction set in 8085 up is
A) 4
B) 3
C) 5
D) 2
Answer: C
8. The no. Of interrupt in 8085 up is
A) 5
B) 6
C) 7
D) 256
Answer: A
9. Timing diagram is
A) interfacing
B) connecting
C) Analyzing.
D) Graphical representation of instruction cycle
Answer: D
10. MVI A,30 is
A) Immediate addressing mode
B) Implicit
C) Direct
D) Indirect
Answer: A
11. The no. Of pin in 8085 up is
A) 40.
B) 30
C) 28
D) 32
Answer: A
12. The interrupt having highest priority is
A) TRAP
B) INTR
C) RST0
D) RST1
Answer: A
27 | P a g e

13. The clock at which 80i85 up operate is

A) 4 MHz
B) 6
C) 5.
D) None of these
Answer: C
14. MVI A,30 is
A) 2Byte instruction
B) 1
C) 3
D) 4.
Answer: A
15. MOV A, B is
A) 1 Byte instruction
B) 2
C) 4
D) 3
Answer: A
16. The instruction STA A.9000H is
A) 3 Byte instruction.
B) 1.
C) 2.
D) None of these
Answer: A
17.The Instruction LXI H,9100H is
A) 2 Byte instruction.
B) 3.
C) 4
D) None of these
Answer: B
18. The instruction MOV A, B is
A) Direct addressing mode
B) indirect addressing mode
C) Immediate addressing mode
D) Register addressing node
Answer: D
19. The no. Of T states in instruction is MVI A,30H is
28 | P a g e

A) 4
B) 7
C) 10
D) None of these.
Answer: B
20. The instruction cycle consist of
A) opcode fetch cycle.
B) opcode fetch cycle and execution cycle.
C) execution cycle
D) None of these.
Answer: B

ASSIGNMENTFULL MARKS-100
SECTION-A
(ANSWER ALL QUESTIONS)

Q.1 Short answer type question: 2*8=16

a) What are the different types of addressing modes in 8085 microprocessor?

b) Which opcode is used to transfer and which opcode is used to retrieve the data from
main memory to stack memory?
c) How many no. of machine cycles are require to execute the instruction MVI A, 47?
d) Give some example of IO and machine control group instruction.
e) Explain the terms opcode and operand in an instruction with example.
f) Draw the table of status code of 8085 microprocessor and indicate the read, write, halt
and fetch operation.
g) What is the function of program counter in 8085 microprocessor.
h) Explain the different registers in 8085 microprocessor.

SECTION-B

Q.2 Focused answer type question: 6*6=36

29 | P a g e

a) What is interrupt operation? What are the different interrupt pins are in 8085
microprocessor and how they work?
b) Explain the status flag of the 8085 microprocessor.
c) What is timing diagram? Draw the timing diagram of MVI A, B.
d) Write a program to convert a binary code to gray code.
e) Explain the T-states in opcode fetch cycle and execution fetch cycle.
f) Explain some important features of 8085 microprocessor.

SECTION-C

Q.3 Long answer type question: 16*3=48

a) With proper sketch describe the internal architecture of 8085 microprocessor.

b)
(i) Explain the term stack and sub-routine. Suppose the data content of main memory,
BC = 2050H, DE = 1234H, HL = 2640H. Write a program to initialize the stack memory
address at 9080H and transfer the data from main memory to stack memory and
retrieve it.
(ii) If the external clock frequency is 5MHz then how much time the processor will take
to execute an operation,
• MVI A, 30
• MOV A, B
• LXI H, 9105
• ADD B
c)
(i) Write an assembly language program for 8-bit multiplication resulting a 16-bit
number.
(ii) Draw the timing diagram of LXI H, 9100 if the data content in the register is 0756 H.
30 | P a g e

MODULE-2:8086 MICROPROCESSORS
Important features of 8086 Microprocessor:
• It is a 16bit processor that means its data line is 16bit and address line is 20bit.
• It consists of 40 pin IC chip and operates at +5V DC.
• It can operate in 3 different clock frequencies i.e. 5MHz, 8MHz and 10MHz.
• It consists of 9 active status flags out of which 6 are conditional flag and 3 are
control flag.

8085 8086

1. The 8085 microprocessor is an 1. It is a 16-bit processor or that

8-bit processor that means its means its data line is 16 bit and
data line is 8 bit and address address line is 20 bits.
line is 16 bits. 2. It can operate in 3 difference CLK
2. It operates in 3-5MHz clock frequencies i.e. 5MHz, 8MHz,
frequency. 10MHz.
3. It consists of 5 active status 3. It consists of 9 active status flags
flags. out of which 6 are conditional flag
4. It consists of single unit and and 3 are control flag.
there is no division in 4. The total internal architecture can
architecture takes place. be divided into 2 different units
5. It consists of single mode and they are the bus interface unit and
basically used for simple input execution unit.
output operation. 5. It can operate in 2 different modes
i.e. minimum mode and maximum
mode.
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Pin diagram of 8086 Microprocessor:

Pin description for 8086 Microprocessor:

It consists of 40 pins and operates at +5V DC.

GND

• There are two ground pins in the 8086, pin 1 and pin 20.
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AD0 to AD19

• Pin no-2 to pin no-16 and pin no-39 are both used as data line and address line (AD0 to
AD15).
• Pin no-38 to pin no-35 are used only for the address line (AD16 to AD19).

NMI

• Pin no-17 is used for Non-Maskable Interrupt Request.

• The function of NMI pin is same as that of trap pin of 8085 microprocessor.
• This pin is basically used for interrupt operation i.e. to stop the current program and jump
to some other program and till the completion of that specific program, the processor
cannot return by to the original program.

INTR

• Pin no-18 is used as Interrupt Request pin.

• This pin is used to receive an interrupt request signal. It is a type of maskable interrupt.

CLK

• Pin no-19 is used as CLK pin.

• This pin tells about the clock pulse.
• Through this pin we can connect to other digital IC pins and basically use to provide
square wave pulse or clock pulse or clock frequencies.

RESET

• Pin no.-21 is used as RESET pin.

• By using this pin, the program control returns to FFFF0H.
• Basically, it is used to restart the processor if the program hangs in between.

READY

• Pin no.-22 is used as READY pin.

• This is an acknowledgment signal from the slower I/O devices or memory.
• When high, it indicates that the device is ready to transfer data, else the microprocessor
is in the wait state.

TEST'

• Pin no-23 is used as TEST' pin.

• This is also an active low signal. This pin is used for wait instruction when the 8086 is
connected with the 8087 microprocessors.
33 | P a g e

• Normally the processor speed is fast and I/O device speed is slow. So, some time we are
transferring the data to the processor but the data does not reach to the processor. So,
in that case the processor goes to wait state and READY pin becomes LOGIC 0 or
deactivated so in that cases the TEST' pin becomes activated i.e. TEST'=0 and TEST=1.
So, the processor goes to wait state.
• Again, when the data reach the processor then READY pin becomes activated or tends to
LOGIC 1 and TEST' pin becomes deactivated i.e. TEST'=1 and TEST=0.
• READY pin is opposite of TEST' pin.

Minimum and maximum Mode Pins-

Total 8 pins, from Pin 24 to pin 31 work differently for different modes (maximum or minimum).

❖ Minimum mode
o For simple output operation the 8086 microprocessors can operate in minimum
mode and in that case the MN/MX’=1 i.e. MN’=1, MX=0, MX=0, where MN is
minimum mode and MX is maximum mode and, in that case, the minimum mode
pins get activated.
o The minimum mode pins are HOLD, HLDA, WR’, DT/R’, DEN’, ALE, INTR’,
M/IO’.

HOLD & HLDA

 Pin no-30 is used as HLDA and pin no-31 is used as HOLD pin.
 Once the HOLD pin is activated then the processor will not allow any external
data to interfere the current program and if the hold is successfully activated
then the processor will send an acknowledge message through the HLDA pin.

WR’

 Pin no-29 is used as WR’ pin.

 It is used for write operation (WR’=0, WR=1).

M/IO’

 Pin no-28 is used as memory/input output pin.

 If the data is transferred with in the processor then it is a memory operation.
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DT/R’

 Pin no 27 is used as DT/R’ pin (Data transfer and receiver pin).

 If the DT/R’=1, DT=1, R’=1, R=0, then in that case it is a data transfer or write
operation and the data transferred from the processor to the external IO device.
 If the DT/R’=0, DT=0, R’=0, R=1, then in that case it is a data receiver or read
operation and the data received from the external IO device to the processor.

DEN’

 Pin no-26 is used as DEN’ (Data Enable) pin.

 It is basically used to check the validity of the data.

ALE

 Pin no-25 is used as ALE (Address Latch Enable) pin.

 It is basically used to separate the address from the address and data bus.

INTA’

 Pin no-24 is used as INTA’ (Interrupt acknowledgement) pin.

 If the interrupt is activated then the processor will send an acknowledge

message through INTA’ pin i.e. INTA’=0, INTA=1.

❖ Maximum mode
o For multipurpose operation when more than 1 IC chips are used then the 8086

microprocessors can operates in maximum mode and in that case the

MN/MX’=0 i.e. MN=0, MX’=0, MX=1.

o Maximum mode pins are QS1, QS0, S0’, S1’, LOCK’, RQ’/GT1, RQ’/GT0

QS1 and QS0

▪ Pin no 24 and 25 are used as QS1 and QS0 pin respectively.

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▪ These are queue status signals and are available at pin 24 and 25. These
signals provide the status of instruction queue. Their conditions are shown
in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0’, S1’, S2’

• These are the status signals that provide the status of operation, which
is used by the Bus Controller 8288 to generate memory & I/O control
signals. These are available at pin 26, 27, and 28. Following is the table
showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt
36 | P a g e

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK
▪ When this signal is active, it indicates to the other processors not to ask
the CPU to leave the system bus. It is activated using the LOCK prefix on
any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
▪ These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When the signal is received
by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than
RQ/GT1.

RD'

• Pin no-32 is used as RD’ pin.

• It is a read signal used for read operation. It is also an active low signal.

MN / MX'

• Pin no-33 is used as MN / MX'

• This pin is used for minimum or maximum mode of the microprocessor. When this pin is
1, the microprocessor works in minimum mode, and when the pin is at 0, the maximum
mode is followed.

BHE' / S7

• Pin no-34 is used as BHE’ pin.

• BHE stands for Bus High Enable. It is an active low signal, i.e. it is active when it is low. It
is used to indicate the transfer of data over the higher order data bus (D8 to D15).
37 | P a g e

• BHE' decides whether the data bus will carry 16-bit data or 8-bit data. When BHE’ is
enabled (i.e. 0), then the bus will carry 16-bit data, else only 8-bit data through the lower
order data bus lines. It is multiplexed with status pin S7.

VCC

• Pin no-40 is used as VCC pin.

• Through VCC pin +5V DC supply is provided to the IC.

INTERNAL ARCHITECTURE OF 8086 MICROPROCESSOR

The total internal architecture of 8086 microprocessor can be basically divided into two different
units.

1.Bus Interfaces Unit (BIU)

2.Execution Unit (EU)
38 | P a g e

1.Bus Interfaces Unit (BIU):

• It is responsible for transfer of data and address between the processor, memory and
input output device.
• It receives the data from the IO device and stored the data in a 6 bytes instruction
queues in FIFO sequence and this data is transferred to the execution unit for
arithmetic and logical operation.
• The function of different units of bus interface unit are
6 bytes instruction queue

o Its function is to receive 6 no. of 8bit data at a time and stores the data in it and
then this data can be transferred to execution unit for performing arithmetic
and logical operation i.e. execution operation.
o The data is received from IO device to the 6 bytes instruction queue in FIFO
sequence.

Segment register

o There are 4 segment register

▪ Code segment register (CS): It basically used to store the opcode of an
instruction.
▪ Data segment register (DS): It basically used to store the operand of an
instruction.
▪ Extra segment register (ES): It is basically used to store the character or
string instruction such as consonant, vowel, character etc.
▪ Stack segment register (SS):Stack is a set of memory location whose
address is different from main memory address.
✓ We can transfer the data from main memory to stack memory by
push instruction and we can receive the data from stack memory to
main memory by pop instruction. So, segment register is basically
used to store the stack memory value.
✓ To locate a particular memory address, we take the help of stack
pointer and given by the command LXI SP 9605H.

Instruction pointer (IP)

o Its function is same as that of program counter of 8085 microprocessor and is

basically used to check whether the address for next instruction is available or
not. So, it stores the OFF-SET address.

Bus control and address generation

39 | P a g e

o It is basically used to generate 20 bits effective memory address or physical

memory address.
o One address is generated from the segment register which is of 16 bit and
when the address goes to the bus control and address generation it gets
multiplied by the multiplier circuit of value 10 H. So, at the output we get a
segment address of 20 bit.
o Another address is generated from the instruction pointer which is of 16 bit
and is known as OFF-SET address or assembly line address.
o So, when this address goes to the bus control and address generation, it gets
added of with the help of adder circuit which is present inside the bus control
and address generation.
o Hence the 20-bit segment address is added up with the 16-bit IP address with
the help of adder circuit and at the output we get a 20-bit effective memory
address or physical memory address.
o Effective memory address (EMA) or Physical memory address (PMA) = Segment
address*10H +Instruction pointer
o The block diagram of physical address generation is shown as follows.

[Block diagram of physical address generations]

2.Execution Unit (EU):

• The execution unit receives the opcode of an instruction from the 6byte instruction
queue decodes it and perform the arithmetic and logical operation and stores the
result.
• The function of different units of execution units are
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ALU

o It is basically used to perform the arithmetic and logical operation such as addition,
subtraction, multiplication, division, increment, decrement, comparison.
o After the arithmetic and logical operation, the result is check by the status flag.

Status Flag

o The status flags are basically used to check whether the result is writing or wrong.
o Accordingly, in 8086 microprocessor there are 9 active status flags out of which 6 are
conditional flag and 3 are control flag.

Conditional flag: Conditional flags are those where the output depends upon the
input. The conditional flags are Sign flag, zero flag, Auxiliary flag, Parity flag, Carry
flag and overflow flag.
➢ Sine flag: After the arithmetic operation if the result is negative then sign
flag is tends to logic 1 otherwise it will tend to logic 0.
➢ Zero flag: After the arithmetic operation if the result is zero then zero flag
will tend to logic 1 otherwise it will tend to logic 0.
➢ Auxiliary flag: After the arithmetic operation if there is a carry from 3rd to
4th bit then auxiliary carry will tends to logic 1 otherwise it will tend to logic
0.
➢ Parity flag: After the arithmetic operation if the result of the sum contains
even no. of 1’s then parity flag will tend to logic 1 otherwise it will tend to
logic 0.
41 | P a g e

➢ Carry flag : After the arithmetic operation if the result is more than 8 bit
then there will be a carry from 7-8 bit so carry flag will tends to logic 1 and
in case of 16 bit operation if there is a carry from 15 to 16 bit the carry flag
will tends to logic 1 otherwise it will tends to logic 0.
➢ Overflow flag: After the arithmetic operation if the result is more than 16
bits, in that case the data cannot be stored in accumulator or destination
register. So, in that case the overflow flag will tends to logic 1 otherwise it
will tend to logic 0.

So, in conditional flag the output is depends on the input

Control flag: The control flags are basically used for control-oriented activity such
as to stop the program, set or reset the operation, status flag manipulation,
interrupt operation. So, in this case it is used for control-oriented activity and here
the output is does not depends upon input. The control flags are Directional flag,
Interrupt flag, Trap flag.
➢ Directional flag: In case of character or string operation in that case the
directional flag will tends logic 1 otherwise it will tend to logic 0.
➢ Interrupt flag and Trap flag: These two flags are basically used as
interrupt operation.

Resistors

o There are two types of register in 8086 microprocessor such as General-purpose

register and Special purpose register.
42 | P a g e

General-purpose register: The general-purpose register are AH and AL i.e. A

higher order and A lower order. Similarly, B H and BL, CH and CL, DH and DL
respectively. Each register can store individually 8bit of data and combine form it
can store 16bit of data so,
AH + AL = AX (16 bit)
BH + BL = BX (16 bit)
CH + CL = CX (16 bit)
DH + DL = DX (16 bit)
e.g. MOV AH, 08H- Move immediately the data 08 toAH register.
MOV AL, 08H- Move immediately the data 08 toAL register.
MOV AX, 1264H- Move the 16-bit data 1264H to Ax register.

o Since these registers are commonly used for storing the data temporarily for any
arithmetic and logical operation so these are known as general-purpose register.

Special purpose register: The special purpose registers are Stack pointer (SP),
Base pointer (BI), Source index register (SI), Destination index register (DI). These
are known as special purpose register because they are used for some specific
operation and these are 16-bit registers.

➢ Stack pointer (SP): Through stack pointer we can locate to a particular

stack pointer address e.g. LXI SP, 9505H.
➢ Base pointer (BP): It is basically use to store the OFF-SET address (value
of instruction pointer address).
➢ Source index register (SI): It is basically used to store the string address
e.g. MOV SI, [2000H]- Move the OFF-SET address 2000H to SI register.
➢ Destination index register (DI): It is basically used to store the end
address e.g. MOV DI, [2005H]-Move immediately the OFF-SET address 2005H
to DI register.
43 | P a g e

INSTRUCTION SETS OF 8086 MICROPROCESSORS

Instructions are sets of commands given to the processor to perform a specific operation
accordingly in 8086 microprocessor the total instruction set can be divided into 8 different types
according to type of operation it performs. The instructions are;

1. Data transform instruction

2. Arithmetic instruction
3. Logical instruction
4. Branch control instruction
5. Iteration control instruction
6. Interrupt instruction
7. Processor control
8. String instruction

1. Data transform instruction: It is basically used for transferring the data from one
register to another register or register to memory without changing the content.
E.g. MOV AX, BX-Move the content of BX register to AX register.
MOV AX,1234H-Move the 16-bit data 1234H to AX register.
2. Arithmetic instruction: These are basically used for arithmetic operation such as
addition, subtraction, multiplication, division, increment, decrement etc. In this
case the final result may change.
3. Logical instruction: These instructions are basically used for logical operation
such as ANA (AND), ORA (OR), XRA (XOR), CMP (COMPARE) etc.
4. Branch control instruction: The instruction under this group are basically used
for conditional or unconditional jump operation.
E.g.
JNZ- Jump if the counter data in the register C is not zero to label loop.
JNC- Jump if there is no carry or borrow to label loop.
5. Iteration control instruction: These instructions are basically used in label
portion for loop operation.
E.g. LOOP, CALL, AHEAD, STOP.
6. Interrupt instruction : The instruction under this group are basically used for
interrupt operation that means to stop the current program and jump to some
other program which is required at the specific moment of time and after the
completion of that specific program the processor can again return back to the
original program and these are given by through certain software instruction such
as INT, INT0, INT1, INT2, INTR.
44 | P a g e

7. Processor control: The instruction under this group are basically used for status
flag manipulation and for machine control operation.
E.g. CLC- Clear the carry bit.
CLD- Clear the directional flag.
STC- Set the carry bit to logic 1.
STD- Set the directional to logic 1.
CMC- Complement of carry bit.
HALT
PUSH
POP
8. String instruction: String is a series of bytes or series of word stored in a
sequential memory location.
In 8085 microprocessor there are certain instructions which are basically used to
move or store a string of data bytes.
E.g. MOV S- Move the string (single bit).
MOV SP- Move the string of data bytes.
CMP S- Comparison of string.
CMP SP- Comparison of string of data bytes.

ADDRESSING MODE OF 8086 MICROPROCESSOR

It is the technique through which we are specifying data for operation or how the operand data
is specified accordingly in 8086 microprocessors. There are 8 different addressing mode
according to the type of operation it performs.

1. Register addressing mode

2. Immediate addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Base addressing mode
6. Index addressing mode
7. Base index addressing mode
8. Base index and displacement

1. Register addressing mode: In this type of addressing mode the operand data is not
directly specified in the instruction itself but it is specified by some register.
E.g. MOV AX, BX- Move the content of BX register to AX register.
MOV AH, AL- Move the content of AL register to AH register.
45 | P a g e

2. Immediate addressing mode: In this type of addressing mode the operand data is
directly specified in the instruction itself.
E.g. MOV AH, 08H- Move immediately the data 08H to AH register.
MOV AX, 1264H- Move the 16-bit data 1264H to AX register.
3. Direct addressing mode: In direct addressing mode the operand address is directly
specified in the instruction itself.
E.g.
MOV AX, [9000H]- Move the content of memory address 9000 H to AX register.
MOV BX, [9001H]- Move the content of memory address 9001 H to BX register.
4. Register indirect addressing mode: In this type of addressing mode the operand data
is not directly transferred to the accumulator; at first it stored in some memory address
and the transferred to the accumulator.
E.g. MOV BX, [9001]
MOV AX, BX
5. Base addressing mode: In this type of addressing mode the operand address is one of
the contents of base pointer or stack pointer. Basically, it stores the OFF-SET value of the
instruction pointer.

E.g. MOV BX, [9005H]- Move the content of the memory address 9005 H to BX
register base pointer.

6. Index addressing mode: It is basically used to store the string address or the end
address. The source index register is used to store the starting address and destination
index register is used to store the end address.
E.g.
MOV SI, [9000H]- Move the content of memory address 9000 H to the SI register.
MOV DI, [9005H]- Move the content of memory address 9000 H to DI register.
7. Base index addressing mode: In this mode the operand OFF-SET is the sum of the
content of base register or BX and index register SI or DI.
E.g.
MOV AX, [BX+SI]- Move the content of base pointer or stack pointer and the
source index value to AX register or accumulator.
MOV AX, [BX+DI]- Move the sum of the content of base register and destination
index register value to accumulator.
8. Base index and displacement: In this addressing mode the operand OFF-SET is the sum
of the content off base pointer + SI or DI + 8-bit or 16-bit displacement value.
E.g. MOV AX, [AX+SI+08H]
46 | P a g e

PROGRAM IN 8086 MICROPROCESSORS

Program to find largest no. of data array: -

LABEL MNEMONICS OPERAND COMMENT
MOV AX, 0000 Move the 16-bit data 0000H to
accumulator or AX register.
MOV SI, [7400] Move the content of the memory
address 7400H to SI register.
MOV CX, SI Move the content of SI register to CX
register which is basically used to
store the counter data.
BACK INC SI Increment the content of source
index register by next bit to provide
the next counter data.
INC SI Increment the content of the source
index address by next bit to provide
the next value.
CMP AX, (SI) Compare the content of AX register
with SI register where AX acts as
accumulator in 8086
microprocessors.
JA NEXT Jump if the no. in AX register is
greater than SI register to level next.
MOV AX, (SI) Move the content of SI register to AX
register.
NEXT LOOP BACK Go to the label back till the counter
data in SI register as reach the
highest value.
MOV (7565), AX Move the content of AX resistor to
memory address resister to memory
address.
INT 2F
END
DATA:
7400-05 7403-83 7406-39 7409-84 RESULT AX=9630
7401-00 7404-58 7407-46 740A-30
7402-41 7405-72 7408-53 740B-96
47 | P a g e

Program to find smallest no. from a data array: -

LABEL MNEMONICS OPERAND COMMENTS

MOV AX, FFFF Move the highest value FFFFH to AX

register.
MOV SI, [7400] Move the content of memory
address 7400H to SI register.
MOV CX, (SI) Move the content of SI register to
CX register which is basically used
for counter operation.
BACK INC SI Increment the content of SI by next
bit to provide the next counter
data.
INC SI Increment the content of SI address
by next bit to provide the next data.
CMP AX, (SI) Compare the content of AX register
with the SI register.
JB NEXT Jump with borrow and carry.
MOV AX, (SI) Move the content of SI register to
AX register.
NEXT LOOP BACK Go to the label back till the counter
data of SI register or CX register has
reach the highest value.
MOV (7565), AX Move the content of AX register to
the memory address 7565H and
7566H.
END
DATA:
7400-05 7406-39 7565-39 RESULT AX=4639
7401-00 7407-46 7566-46
7402-41 7408-53
7403-83 7409-84
7404-58 740A-30
7405-72 740B-96
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MINIMUM MODE CONFIGURATION OF 8086 MICROPROCESSOR

When the single processor is used, then the 8086 microprocessor operates in minimum mode
MN/MX’ tends to logic 1 i.e. MN=1, MX’=1, MX=0

So, for simple input output operation or when a single processor is used then the 8086
microprocessor operates in minimum mode and in that case the control signal pins which are
attach to minimum mode get activated. The control signal pins are RD’, WR’, ALE, IO/M’, HOLD,
HLDA, DEN’.

The different units which are attached to the minimum mode control pin to perform different
memory read and IO read, IO write operation is known as minimum mode configuration.

The different units are:

i. Latches:
• There are 2 to 3 latches are present and these latches are octal in nature that means
each latch can stores 8 bits of data so the two latches can store 16 bit of data and
3 latches can stores 20 bits of address.
• Latches are temporary storage device or flipflop
• The ALE signal is connected to the latches and its function is to separate the
address from address and data bus.
• The bus high enable pin is also attach to the latches and its main function is to
check the validity of address and the address and data line are also attached to
latches.
ii. Trans receiver:
• Trans receiver means transfer and reception of data.
• Through the trans receiver we can transfer the data from the processor to the IO
device and in that case the DT/R’ tends to logic 1 i.e. DT=1, R’=1, R=0.
• If DT/R’ tends to logic 0 then DT=0, R’=0, R=1 so read operation is perform i.e. data
is received from the IO device to processor.
• Data enable pin is also attached to the trans receiver and its main function is to
check the validity of the data.

iii. RAM:
• It is known as random access memory.
• Its temporary stores the data and it volatile in nature that means if the power supply
OFF the data gets deleted.
• Hera we can perform both read and write operation.
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iv. EPROM:
• EPROM- Erasable Programmable Read Only Memory.
• It is non-volatile in nature and is used to stores the library function.
• It is only used for read operation.
v. IO device or peripheral device:
• It is basically used for providing input data to the processor.
• In minimum mode single processor is used so a single IO device is connected to
processor.
vi. Clock generator:
• It is basically used for providing input clock frequency to the processor so that we
can check how much time the processor will take to execute an operation.
• It can vary from 5MHz to 10MHz.
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Timing diagram of minimum mode operation of 8086 microprocessor:

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MAXIMUM MODE CONFIGURATION OF 8086 MICROPROCESSOR

For multipurpose operation the 8086 microprocessors can operates in maximum mode and in
that case the MN/MX’ pin tends to logic 0 i.e. MN=0, MX’=0, MX=1.

In maximum mode operation multiple RAM, multiple ROM, multiple IO devices are attached to
the processor to perform different memory read and memory write and IO read and IO write
operation.

In maximum mode operation bus controller i.e. 8288 is used because the control signal which
are required to perform different read write operation such as RD’, WR’, IO/M’ are not available
in maximum mode. So, if we are using a bus controller then all the control signal which are
required to perform different read write operation are resent in this bus controller.

Through this bus controller we can connect to multiple or different RAM, ROM, IO devices to
perform different read write operation and this bus controller is indirectly control by the status
signal pin i.e. s0’, s1’, s2’ of maximum mode control pins.

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read
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1 1 0 Memory write

1 1 1 Passive

The different units which are attached to the maximum mode pins to perform different read
write operations are

1. Multiple latches:
• Latches are temporary storage device and acts as a flipflop.
• Multiple latches are used to separately stores the address and the data.
2. Trans receiver:
• Basically, used for transfer and reception of data to multiple RAM, multiple ROM
and multiple IO devices.
3. 8288 bus controllers:
• These bus controllers are basically used for performing different read, write and IO
operation with the help of control signal such as MRDC’, MWTC’, IORC’, IOWC’ etc.
4. Multiple RAM:
• It is known as random access memory.
• Its temporary stores the data and it volatile in nature that means if the power
supply OFF the data gets deleted.
• Hera we can perform multiple read and write operation.

5. Multiple EPROM:
• EPROM- Erasable Programmable Read Only Memory.
• It is non-volatile in nature and is used to stores the library function.
• It is only used for multiple memory read operation.

6. Multiple IO devices:
• It is basically used for providing multiple input data to the processor.
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• In maximum mode multiple processors is used so a multiple IO device is connected

to processor.

7. Clock generator:
• It is basically used for providing input clock frequency to the processor so that we
can check how much time the processor will take to execute an operation.
• It can vary from 5MHz to 10MHz.
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Timing diagram of 8086 microprocessor

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INTERRUPT STRUCTURE OF 8086 MICROPROCESSORS

The 8086 gets the new values of CS and IP register from four memory addresses. When it
responds to an interrupt, the 8086 goes to memory locations to get the CS and IP values for
the start of the interrupt service routine. In an Interrupt Structure of 8086 system the first 1
Kbyte of memory from 00000H to 003FFH is reserved for storing the starting addresses of
interrupt service routines. This block of memory is often called the Interrupt Vector Table in
8086 or the interrupt pointer table. Since 4 bytes are required to store the CS and IP values
for each interrupt service procedure, the table can hold the starting addresses for 256 interrupt
service routines.

Each interrupt type is given a number between 0 to 255 and the address of each interrupt is
found by multiplying the type by 4 e.g. for type 11, interrupt address is 11 x 4 = 4410= 0002CH

Only first five types have explicit definitions such as divide by zero and non- maskable interrupt.
The next 27 interrupt types, from 5 to 31, are reserved by Intel for use in future microprocessors.
The upper 224 interrupt types, from 32 to 255, are available for user for hardware or software
interrupts.
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Five types of defined interrupts are:

1. TYPE-0 or Divided by zero error interrupt

2. TYPE-1 or Single step interrupt
3. TYPE-2 or Non-maskable interrupt
4. TYPE-3 or Break point interrupt
5. TYPE-4 or Overflow interrupt
1. TYPE-0 or Divided by zero error interrupt : In case of division operation if the quotient
value is very large or more than the destination register value or more than 16-bit so in
that case the divided by zero interrupt will get activated to indicate that the result is more
than the destination register value and the result cannot be stored in accumulator.
2. TYPE-1 or Single step interrupt: If this interrupt is activated then it will check the
program step by step so it acts as an interpreter.
3. TYPE-2 or Non-maskable interrupt: If this interrupt is activated then in case of system
power failure or AC power failure then the data will not get deleted.
4. TYPE-3 or Break point interrupt: If the interrupt is activated then the processor will stop
the current program and jump to some other program which is required at that specific
moment of time after the completion of that specific program. The processor can again
return back to the original program.
5. TYPE-4 or Overflow interrupt: In case of any type of arithmetic operation such as
multiplication, addition, subtraction etc. if the result is more than the destination register
value or more than 16-bit or the result is very large, in that case the overflow interrupt
will get activated and tends to logic 1 to indicate that the result is very large and cannot
be stored in accumulator.
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Multiple choice question answer:

1. The 8086 up is ________ bits processor.

A) 8 bits
B) 10 bits
C) 16 bits
D) 32 bits
Answer: C
2. The 8086 up has a____ byte instruction queue.
A) 6 byte
B) 2 byte
C) 4 byte
D) 8 byte
Answer: A
3. The total internal architecture of 8086 up is divided into
A) ALU and Timing control unit
B) Bus interface unit and execution unit
C) Instruction queue and Alu
D) Segment register and IP.
Answer: B
4. The Bus control and address generation generates
A) 20-bit address line.
B) 16-bit
C) 24-bit
D) 12-bit.
Answer: A
5. The no. Of addressing modes in 8086 up is
A) 8.
B) 5.
C) 6.
D) 4.
Answer: A
6. The no. Of instruction set in 8086 up is
A) 8.
B) 6.
C) 5.
D) 4
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Answer: A
7. The no. Of status flags in 8086 up is
A) 6.
B) 8.
C) 9.
D) 5.
Answer: C
8. The status flag of 8086 up is divided into.
A) conditional flag and control flag
B) conditional flag and trap flag.
C)conditional flag and interrupt flag.
D)control flag and interrupt flag.
Answer: A
9. The no. Of conditional flags are.
A)4.
B)5.
C)8.
D)6.
Answer: D
10. The no. Of control flags are.
A)3.
B)5.
C)6.
D)8.
Answer: A
11. The no. of interrupts in 8086 up is
A) 256
B) 255
C) 200
D) 5.
Answer: A
12. The NMI interrupt is
A) TYPE 2
B) TYPE 1.
C) TYPE 3
D) TYPE O.
Answer: A
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13. The single step interrupt is _________.

A) TYPE 0.
B) TYPE 2.
C) TYPE 1.
D) None of these
Answer: C
14. The Divide by zero error interrupt is ___________.
A) TYPE O
B) TYPE 1
C) TYPE 2
D) TYPE 3
Answer: A
15.The Break point interrupt is
A) TYPE 3.
B) TYPE 0.
C) TYPE 1.
D) TYPE 2.
Answer: A
16.The address line of 8086 up is
A) 20 bit.
B) 16 bit.
C) 24 bit.
D) None of these
Answer: A
17. The 8086 up operates at
A) 12V DC.
B) 5V DC.
C) 220V Ac.
D) None of these
Answer: B
18. The minimum mode is used ______.
A) multimode operation
B) complex operation.
C) more than one processor is attached.
D) simple input output operation.
Answer: D
19.The maximum mode is used for________.
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A) simple input output operation.

B) multipurpose operation.
C) logical operation.
D) none of these.
Answer: B
20. The instruction cycle consist of_________.
A) execution cycle.
B) opcode fetch cycle and execution cycle.
C) opcode fetch cycle
D) none of these
Answer: B
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ASSIGNMENTFULL MARKS-60
SECTION-A

Q.1 Short answer type question: 2*4=8

a. What are the maximum mode control signal pins?

b. What are the general-purpose registers of 8086 microprocessor?
c. What is stack and stack pointer?
d. How many status flags are in 8086 microprocessors among them? What are the
conditional flags and control flags?

SECTION-B

Q.2Focused answer type question: 6*6=36

a. Explain the minimum mode configuration of 8086 microprocessor.

b. Explain the opcode fetch cycle of minimum mode configuration.
c. Explain the maximum mode configuration of 8086 microprocessor.
d. Write the program to find the largest no. from the data array using 8086
microprocessors.
e. Explain the interrupts of 8086 microprocessor.
f. Explain the addressing modes of 8086 microprocessor with suitable examples.

SECTION-C

Q.3 Long answer type question: 16*1=16

a) Explain the internal architecture of 8086 microprocessor with suitable diagram. Write
a program to find smallest no. from data array using 8086 microprocessors.
OR
b) Explain the instruction set of 8086 microprocessors. Draw the timing diagram of read
cycle of minimum mode configuration for 1byte instruction.
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MODULE-3: INTERFACING DEVICES

Introduction:

The main function of interfacing device is that,

• It matches the processor’s speed with IO device speed so that our data will not get loosed.
Normally the processor’s speed is fast and IO speed is low so if we are using an interfacing
device then it matches the processor speed with IO device speed.
• It obeys the ASCII (American Standard Code for Information Interchange) or alpha
numeric code.
• It acts as voltage regulator so that our appliance will not get brunt.
• Through the interfacing device instead of transferring the data directly to the processor
we can indirectly store in the interfacing device and we can transfer it to the processor.
So, in this way we can avoid over burden of the processor.
• Through the interfacing device we can connect multiple IO device so in this way we can
receive data from multiple IO devices and then we can transfer into the processor.
• The various interfacing devices are:
1. 8255 PPI (Programmable Peripheral Interface)
2. 8257 DMA (Direct Memory Access)
3. 8259 PIC (Priority Interrupt Controller)
4. 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)
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1. 8255 PPI (Programmable Peripheral Interface):

• It consists of 40 pin IC chip and operates at +5V DC.
• It is known as programmable peripheral interface because through certain
control word bit which is present inside the read write logic section of PPI.
• We can control the ports and mode of operation that means we can make
any port as input or output port and through this port we can transfer the
data from the processor to the external device or we can receive the data
from the IO device to the processor.

Pin diagram of 8255 PPI:

Pin description of 8255 PPI:

Port: Out of 40 pins, 24 pins are used for ports. There are 3 ports through we can transfer and
receives data.
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a) Port A (PA0-PA7): Pin no. -3,2,1,40,39,38,37,36.

b) Port B (PB0-PB7): Pin no-18 to pin no-25
c) Port C:
i. Port C upper (PC4-PC7): Pin no-13 to Pin no-10
ii. Port C lower (PC0-PC3): Pin no-14 to Pin no-17

RD’: Pin no-5 is used for read operation if RD’=0, RD=1.

CS’: Pin no-6 is used as cheap selection pin. If CS’=0, CS=1, then the control signal pins are
get activated.

GND: Pin no-7 is used as ground pin.

A1& A0: Pin no-8 & pin no-9 is used as A1&A0 respectively. These 2 pins are control signal
pins used for controlling the ports and modes operations.

VCC: Pin no-26 is used as supply pin. +5V DC is supply to the IC through V CC pin.

D0 to D7: Pin no-34 to pin no-27 is used as data line pins (D0 to D7) which is of 8-bits and
these pins are bidirectional through which we can transfer and receive the data.

Reset: Pin no-35 is used as reset pin. It is basically used to restart the processor.

WR’: Pin no-36 is used for write operation if WR’=0, WR=1.

INTERNAL ARCHITECTURE OF 8255 PPI:

• It is known as 8255 programmable peripheral interfaces because through certain control

word bits we can control the ports and modes of operation.
• The total internal architecture of 8255 PPI can be divided into 3 different units they are:
a) Ports
b) Data bus buffer
c) Read write control logic section

a) Ports: In 8255 PPI there are 3 parts i.e. Port A, Port B & Port C and the port C is
also divided into 2 types i.e. Port C lower and Port C upper. Each port can transfer
or receive 8-bits of data and can operated in 3 different modes.
i. Mode-0: In this mode of operation there no combination of ports takes
place and all the ports behaves as simple input output ports i.e. Port A can
transfer individually 8-bit of data, Port B can transfer 8-bit of data and Port
C upper & Port C lower can transfer individually 4 bits of data.
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ii. Mode-1: In this mode of operation there is combination of codes takes place
i.e. Port A combines with Port C upper and Port B combine with Port C lower
to transmit 12-bits of data. So, mode-1 is also known as “Handshaking
Mode”, where the combination of ports takes place.
iii. Mode-2: In this mode only Port-A get activated and all other ports get
deactivated so, Port A behaves as bidirectional port through which we can
transfer or receive the data. This port is controlled by group control that
means group controls Port A and Port C upper and the mode of operation.
Similarly, group control the Port B and Port C lower and mode of operation.

b) Data bus buffer: It is known as bidirectional that means it can transfer and receive
data and it consists of 8-bit of data.

c) Read write control logic section: It is basically use for controlling the ports and
mode of operation with the help of control word bit which is present inside the
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read write logic section and these control word bits are connected to different
ports through which it controls the ports that means it can make any port as input
or output through the control word data which is of 8-bit.

Q. Make a control word bit for mode-0 operation where port A and port B behaves as
input port & port C upper and port C lower output port.
Ans.

7 6 5 4 3 2 1 0
1 0 0 1 0 0 1 0

= 92H

Q. Make a control word bit for mode-1 operation, port A input, port B output, port C
upper input, port C lower output.
Ans.
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7 6 5 4 3 2 1 0
1 0 1 1 1 1 0 0

=BCH

Q. Make a control word bit for mode-2 operation port A behaves as input all other ports
are output ports.
Ans.

7 6 5 4 3 2 1 0
1 1 0 1 0 0 0 0

= D0H
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2. 8257 DMA (Direct Memory Access):

Pin diagram of 8257 DMA

Pin description of 8257 DMA

It consists of 40 pin IC chip and operates at +5V DC.

IOR and IOW’

• Pin no-1 and pin no-2 is used as IOR and IOW’ operation respectively.
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• IOR is used for IO read from IO device and IOW’ is used for IO write for
transferring the data from the processor to the IO device.

MEMR’ and MEMW’

• Pin no-3 and pin no-4 is used as memory read and memory write operation
respectively.
• If MEMR’=0 AND MEMW’=1 then memory read operation occurs.
• If MEMR’=1 and MEMW’=0 then memory write operation occurs.

MARK

• Pin no-5 is used for memory acknowledgement pin.

• Through this pin the processor sends an acknowledgement message if a
read write operation is performed.

READY

• Pin no-6 is used as ready pin.

• It keeps the processor in active state.
• Normally the processor speed is fast and IO device speed is slow. So, some
time we are transferring the data to the processor but the data has not
reach to the processor. So, in that case the ready pin tends to logic 0 and
the processor goes to wait state.

HLDA

• Pin no-7 is used as HLDA pin.

• The processor will send an acknowledge message through the HLDA pin.

ADSTB

• Pin no-8 is used as address strobe pin.

• Its function is same as that of ALE pin of 8085 microprocessor.
• It is basically used to separate the address bus and data bus.

AEN

• Pin no-9 is used as Address Enable pin.

• It is basically used to check the validity of the address.

HRQ

• Pin no-10 is used as Hold Request pin.

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• Through this pin the request message for HOLD operation is send to the
processor.

CS’

• Pin no-11 is used as cheap selection pin. If CS’=0, CS=1, then the control
signal pins are get activated.

CLK

• Pin no-12 is used as CLK pin.

• This pin tells about the clock pulse.
• Through this pin we can connect to other digital IC pins and basically use
to provide square wave pulse or clock pulse or clock frequencies.

RESET

• Pin no.-13 is used as RESET pin.

• By using this pin, the program control returns to FFFF0 H.
• Basically, it is used to restart the processor if the program hangs in between.

DACK’

• There are 4 DACK’ pin in 8257 DMA such as DACK’0(pin no-25), DACK’1(pin
no-24), DACK’2(pin no-14) and DACK’3(pin no-15)
• The use of DACK’ pin is to send an acknowledge message when the data is
successfully accepted by the processor.

DRQ

• There are 4 different DMA Request pin such as DRQ3(pin no-16), DRQ2(pin
no-17), DRQ1(pin no-18), DRQ0(pin no-19).
• Through these pin 4 different IO devices are connect to the IC chip.

GND

• Pin no-20 is used as the GND pin.

D0-D7

• Pin no-30,29,28,27,26,23,22,21 is used as D0, D1, D2, D3, D4, D5, D6, D7
respectively.
• These pins are data line pins which is of 8 bit and bidirectional in nature i.e.
it can transmit and receive the data.
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VCC

• Pin no-31 is used as VCC pin.

• Through VCC pin +5V DC supply is provided to the IC.

A0-A7

• Pin no-32, 33, 34, 35, 37, 38, 39, 40 is used as A0, A1, A2, A3, A4, A5, A6, A7.
• These pins are address line pin which is unidirectional in nature.

TC

• Pin no-36 is used as trans connected pin.

• This pin is generally kept blank so that through this pin we can connect
other digital IC.

INTERNAL ARCHITECTURE OF 8257 DMA:

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It is known as DMA (Direct Memory Access) because instead of transmitting the data directly to
the processor, we can indirectly store the data from different IO devices and then we can
transfer the data to processor to avoid over burden of the processor.

The total internal architecture of 8257/8237 DMA is basically divided into 5 different units

a) 4 Channel
• There are 4 channels I DMA through which we can connected to 4 different IO devices.
• Each channel has got 2 pins i.e. DQR pin and DACK’ pin.
b) Priority resolver
• The main function of priority resolver is to check which data has gone 1 st from 4 different
channels through FIFO sequence and then according to priority basis, the data is
transferred to the processor.
c) Data bus buffer
• It is bidirectional, through which we can transfer and receive 8 bits of data.
d) Read/write logic section
• It has the different control signal such as IOW’, IOR’ etc. through which it can perform
different read write operation.
e) Mode set and status word register
• This unit has got different control signal such as ADSTB pin, HLDA, RD’, WR’ etc. through
which it can control the device and can perform different memory read and memory write
operations.
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3. 8259 PIC (Priority Interrupt Controller)

Pin diagram of 8259 PIC

Pin description of 8259 PIC

It consists of 28 pin IC chip.

CS’ PIN

• Pin no-1 is used as CS’ pin.

• This pin is used for chip selection purpose.
• If CS’=0, CS=1, then control signals are activated.

WR’ PIN

• Pin no-2 is used as memory write pin.

• If WR’=0, WR=1, then chip perform the write operation.

RD’ PIN

• Pin no-3 is used as memory read pin.

• If RD’=0, RD=1, then chip perform the memory write operation.

D7-D0 PIN

• Pin no-4 to pin no-11 are used for data line pin i.e. D7-D0.
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• The data line pins are of 8 bit and is bidirectional in nature i.e. we can transfer or receive
the data.

CAS PIN

• Pin no-12,13 & 15 is used as CAS0, CAS1& CAS2 respectively.

• These pins are cascade buffer pin.
• Basically, it is used to increase the interrupt label.
• Normally a single 8259 PIC can connect to 8 different IO devices but through these
cascade buffer pin we can increase the interrupt label to 64.

GND

• Pin no-14 is used as the GND pin.

SP/EN’

• Pin no-16 is used as SP/EN’ pin.

• When a single 8259 PIC is operating the SP/EN’ pin tend to logic 0 i.e. SP=0, EN’=0, EN=1
that means the processor is operating in enable mode
• When 8259 PIC is connected to other PIC then it operates in slave mode that means SP=1,
EN’=1, EN=0.

INT PIN

• Pin no-17 is used as interrupt pin.

• Through this pin the data is send to the processor and if the data is successfully accepted
by the processor then the processor sends an acknowledge message through the INTA’
pin (Pin no-26) or interrupt acknowledgement pin.

IR0-IR7

• Pin no-18 to pin no-25 is used as interrupt request line pin.

• Through this pin the processor can receive 8 no. of interrupt request from 8 different IO
device at the same time.

A0 PIN

• Pin no-27 is used as A0.

• It is a control signal pin for memory read or memory write operation.
• If A0=0 then processor perform memory write operation and if A 0=1 then processor
perform memory read operation.
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VCC

• Pin no-28 is used as VCC pin.

• Through VCC pin +5V DC supply is provided to the IC.

INTERNAL ARCHITECTURE OF 8259 PIC

It is basically used for interrupt driven operation where a single 8259 PIC can receive 8 no. of
interrupt request from 8 different IO devices but in cascade form the interrupt label can be
increase to 64.

The total internal architecture of 8259 PIC can be divided into 4 different units. They are

1. Interrupt and control logic section

2. Data bus buffer section
3. Read write logic section
4. Cascade buffer section

1. Interrupt and control logic section

Under this section we have 5 different units, they are,
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a. Interrupt Request Register (IRR)

Through this register we can receive 8 no. of interrupt request from 8 different IO device
through the interrupt request line i.e. IR0-IR7 and the data is stored in this interrupt
request register.
b. Priority resolver
The main function of priority resolver is to check which data has got the highest priority
by 3 different modes. They are
i. FIFO sequence
In this sequence the data from 8 different IO devices which is stored in IRR is send to
the priority resolver and the priority resolver checks which data has come first
depending upon First In First Out (FIFO) sequence and that data is send to in service
register and other data are being blocked or marked by interrupt mask register.
ii. Rotating Priority mode
In this mode a particular sequence is provided to the interrupt request line so that
the data from the IO device is transmitted in that sequence to the interrupt request
register and then this data are transmitted to the priority resolver.
iii. Fixed Priority mode
In this mode a particular interrupt request line is provided with highest priority so
that the data from these interrupt request lines is transmitted first to the in-service
register and other data are provided with lower priority.
iv. Interrupt mask register
Its main function is to block or mask the data which is having lower priority.
v. In-service register
The data which is having highest priority is send to in-service register and then this
data is send to the processor through the control logic unit.
c. Data bus buffer
It is bidirectional and it is of 8 bits.
d. Read write logic section
It has got different control signal pin such as RD’, WR’, A 0, CS’ pin which is basically used
for read write and cheap selection operation.
e. Cascade buffer and comparator
Through this unit we can increase the interrupt level up to 64. The different pins are CAS0,
CAS1, CAS2 or cascade buffer pin which we can be connected to other 8259 PIC and
SP/EN’ pin is used to check whether the processor is operation in slave mode or enable
mode.
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8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)

Pin diagram of 8251 USART

Pin description of 8251 USART

It consists of 28 pin IC chip and operates at +5V DC.

D0-D7

• Pin no-27,28,1,2,5,6,7,8 is used as D0, D1, D2, D3, D4, D5, D6, D7 respectively.
• These pins are data line pin and bidirectional in nature.

RXD pin
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• Pin no-3 is used as RXD pin.

• It is an input pin or receiver data pin.
• Through this pin the data is received by the processor from the external IO device and
then stored in receiver buffer section.

GND pin

• Pin no-4 is used as the GND pin.

TXC’ pin

• Pin no-9 is used as transmitter clock pin.

• It is used to control the rate at which the characters are transmitted and it is connected
to transmitter control unit and it always keeps it in active mode i.e. TXC’=0, TXC=1.

WR’ Pin

• Pin no-10 is used as memory write pin.

• If WR’=0, WR=1, then chip perform the write operation.

CS’ PIN

• Pin no-11 is used as CS’ pin.

• This pin is used for chip selection purpose.
• If CS’=0, CS=1, then control signals are activated.

C/D’ pin

• Pin no-12 is used as control/data pin.

• This pin is used to differentiate between the control signal and data.
• If C/D’=0 then the data lines are activated and if C/D’=1 then the control signals are
activated.

RD’

• Pin no-13 is used as memory read pin.

• If RD’=0, RD=1, then chip perform the memory write operation.

RXRDY

• Pin no-14 is used as receiver ready pin.

• these pins are used to inform the processor that the data is ready for transfer to the
processor.
• This pin is connected to the receiver control unit.
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• TXRDY
• Pin no-15 is used as transmitter ready pin.
• It is an output pin and its function are to inform the processor that the transmitter buffer
is ready to transmit the data to the external IO device.

SYNDET/BRKDET

• Pin no-16 is used as synchronous detect/baud rate pin.

• This pin is an input output pin through which we can detect the synchronous data transfer
and also, we can measure the baud rate (The no. of data bits transmitted per unit time).

CTS’

• Pin no-17 is used as control and data transfer pin.

• It is used in modem control for checking serial or parallel data transmission.

TXE

• Pin no-18 is used as transmitter empty pin.

• It is an output pin and it is used to inform the processor that the transmitter control
section is empty and it can receive new data.

TXD

• Pin no-19 is used as transmitter data pin.

• It is an output pin which is connected to the transmitter buffer pin and is basically used
to transfer the data to the external IO device.

CLK

• Pin no-20 is used as clock pin.

• This pin tells about the clock pulse.
• Through this pin we can connect to other digital IC pins and basically use to provide
square wave pulse or clock pulse or clock frequencies.

RESET

• Pin no-21 is used as RESET pin.

• By using this pin, the program control returns to FFFF0H.
• Basically, it is used to restart the processor if the program hangs in between.

DSR’

• Pin no-22 is used as data set ready pin.

80 | P a g e

• It is an input pin and it is basically used to check whether the data is ready for receiving
at the modem unit.

DTS’

• Pin no-23 is used as data request to send pin.

• It is an output pin and is connected to the modem and it indicates that the transmitter is
ready to transmit the data through themodem.

DTR’

• Pin no-24 is used as data transfer and receiver pin.

RXD’

• Pin no-25 is used as receiver data pin.

VCC

• Pin no-26 is used as power supply pin.

• Through VCC pin +5V DC supply is provided to the IC

INTERNAL ARCHITECTURE OF 8251 USART

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It supports both synchronous and asynchronous modes of operation.

The 8251 USART receives parallel data from the processor and transfer it serially and also it
receives serial data from the IO device and transmit them parallelly to the processor.

The total internal architecture of 8251 USART can be divided into 4 different units such as

1. Transmitter and receiver buffer control unit

• These are basically used for reception and transmission of data.
• The receiver unit has got receiver control and receiver buffer unit.
• The receiver control has got different control signals such as RXD for receiving data,
RXRDY it indicates that the receiver is ready to received data from the IO device and
to transmit it to the processor through the receiver buffer unit.
• The SYNDT indicates that the receiver is ready to receive a group of characters or data
at a time.
• Similarly, the transmitter section has got 2 units; they are control buffer and
transmitter buffer.
• The transmitter control has got different control signals through which it checks
whether the transmitter is empty and to transmit data to the transmitter buffer.
(Control signals are TXRDY’, TXE).
2. Data bus buffer
• It is bidirectional in nature and through the data bus buffer we can transfer and receive
8-bit of data.
3. Read write logic unit
• It is basically used for read write operation and for control-oriented activities such as
RD’ for read operation, WR’ for write operation.
• If the C/D’=0 then the data line is selected.
• If the C/D’=1 then the control signal is selected
4. Modem control
• It is basically used to convert the digital to analog data and vice versa.
• It is also used for data transmission.
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SERIAL DATA TRANSFER FORMAT

1. Synchronous serial data transfer

• In this method a block of data is transmitted serially at the same time.
• The no. of data bytes is not limited.
• The data bytes transmitted one after the other.
• Here the data speed or bit rate is more than 20KB/sec.
• In this case the data which is transmitted are serially between the transmitter and receiver
and some synchronous characters are added to the data bits and these synchronous
characters can be connected to multiple receivers. So, in synchronous data transfer serial
to parallel data is transmitted and there is no start and stop bit and data transmission is
unlimited normally 256 bits.
2. Asynchronous serial data transfer
• In this method 1 bytes of data is transfer serially at a time.
• After each data transfer there is a start and stop bit.
• The data transfer rate is slow or less than 20 KB/Sec.
• Here the data transfer rate is limited as compare to synchronous data transfer where the
word length is unlimited.
• Here 8 bits of data is transferred at a time after which there is a stop bit but there is no
start or stop bit in synchronous data transfer.

SERIAL DATA TRANSFER PARALLEL DATA TRANSFER

1. 1 bit of data is transferred at a time. 1. 8 bit / 16 bit of data is transferred at
2. Data transfer is slow. a time.
3. This method is used for long 2. Data transfer is fast.
distance communication. 3. This method is used for short
distance communication.

Q. Connect the 32Kbyte RAM with 8086 microprocessors in maximum mode with the
starting address from 60000H.

Solution:

Total capacity of RAM= 32KB

Even memory bank size= 16KB

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Odd memory bank size= 16KB

Now 16 Kbytes= 16*1024= 24*210= 214 i.e. here 14 pins are used for address operation.

A A A A A A A A A A A A A A A A A A A A BHE’ ADDRESS RAM

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /RO
M
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 60000 16K*
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 67FFE 8
0 EVEN
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 60001 16K*
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 67FFF 8
0 ODD

[ In 8086 microprocessor address line= 20bit

According to question we have to connect 32Kbyte RAM with 8086 Microprocessor so
32kbyte= 16kbyte + 16kbyte
EVEN ODD

16kbyte= = 16*1024= 24*210= 214 i.e. here 14 pins are used for address operation and among
from rest 6pin, 5 (A19-A15 pins) are used for control signal and 1 (A0 pin) is used for even or
odd ram selection pin.

Q. Connect the 64Kbyte RAM with 8086 microprocessors in maximum mode with the
starting address from 00000H.

Solution:

Total capacity of RAM= 64KB

Even memory bank size= 32KB

Odd memory bank size= 32KB

Now 16 Kbytes= 32*1024= 25*210= 215 i.e. here 15 pins are used for address operation.

A A A A A A A A A A A A A A A A A A A A BHE’ ADDRESS RAM

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /RO
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00000 32K*
8
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0FFFE
EVEN
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00001
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0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0FFFF 32K*
8
ODD

[ In 8086 microprocessor address line= 20bit

According to question we have to connect 32Kbyte RAM with 8086 Microprocessor so
64kbyte= 32kbyte + 32kbyte
EVEN ODD

32kbyte= = 32*1024= 25*210= 215 i.e. here 15 pins are used for address operation and among
from rest 5 pin, 4 (A19-A16 pins) are used for control signal and 1 (A0 pin) is used for even or
odd ram selection pin.

Q. Using a 3:8 decoder interfaces a 32Kbyte RAM with 8086 microprocessors in minimum
mode with the starting address from 00000H.

Solution:

Total capacity of RAM= 32KB

Even memory bank size= 16KB

Odd memory bank size= 16KB

Now 16 Kbytes= 16*1024= 24*210= 214 i.e. here 14 pins are used for address operation.

A A A A A A A A A A A A A A A A A A A A BHE’ ADDRESS RAM

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /RO
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00000 16K*
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 07FFE 8
0 EVEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00001 16K*
8
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 07FFF
ODD

[ In 8086 microprocessor address line= 20bit

According to question we have to connect 32Kbyte RAM with 8086 Microprocessor so
32kbyte= 16kbyte + 16kbyte
EVEN ODD
85 | P a g e

16kbyte= = 16*1024= 24*210= 214 i.e. here 14 pins are used for address operation and among
from rest 6 pin, 5 (A19-A15 pins) are used for control signal and 1 (A0 pin) is used for even or
odd ram selection pin.

Multiple choice question answer:

1. The no. Of ports in 8255 PPI is

A) 2
B) 3
C) 4
D) 5
Answer: B
2. which port in 8255 PPI is divided into upper and lower port.
A) port c
B) port A
C) port B
D) none of these.
Answer: A
3. In Mode 0 operation.
A) All the ports behave as bidirectional port
B) All the ports behave as simple input output port.
C) Port A behaves as bidirectional port
D) None of these.
Answer: B
4. The function of interfacing device i.e.
A) speed matching
B) impedance matching
C) reducing speed
D) Disconnecting ports
Answer: A
5. Mode 1 operation
A) Hand shaking Mode
B) Bidirectional Mode
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C) Unidirectional Mode
D) Wait Mode
Answer: A
6. In Mode 2 operation
A) Only port A behaves as bidirectional Mode
B) unidirectional Mode
C) wait Mode
D) Inactive Mode
Answer: A
7. 8255 PPI is known as programmable peripheral device because
A) It is an interfacing device
B) connecting ports
C) Through control word bit we can control the ports and Mode of
Operation.
D) connecting ports
Answer: C
8. If control word bit is 80 H then it operates in
A) Mode 0
B) Mode 1
C) Mode 2
D) Mode 3
Answer: A
9. In 8257 DMA there are
A) 2 channel
B) 1 channel
C) 3 channel
D) 4 channel.
Answer: D
10. The FIFO sequence
A) The data which has come first will transfer first.
B) The data which has come first will transfer last.
C) Fixed data transfer.
D) Rotating data transfer
Answer: A
11. The function of priority resolver is
A) The data having highest priority.
B) lowest priority.
C) interfacing
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D) connecting external device.

Answer: A
12. A single 8259 PIC has
A) 8 interrupt request line
B) 7 interrupt request line
C) 3 interrupt request line
D) 4 interrupt request line
Answer: A
13. In cascade form the interrupt level can be increased to
A) 52
B) 60
C) 64
D) None of these
Answer: C
14.The function of interrupt mask register
A) Block data having lower priority.
B) highest priority
C) unblock data
D) Transfer data
Answer: A
15. The function of in-service register
A) store data having highest priority
B) lowest priority
C) No priority
D) unblock data
Answer: A
16. The main function of control logic unit of 8259 PIC is
A) Transfer data to the processor
B) block data to the processor
C) Unblock data
D) None of these
Answer: A
17.The function of 8251 USART
A) synchronous data transfer.
B) synchronous and Asynchronous data transfer
C) Asynchronous data transfer.
D) None of these
Answer: B
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18. A function of MODEM

A) Modulation
B) Demodulation
C) Encoding
D) Modulation and Demodulation.
Answer: D
19. The function of Bus High Enable pin
A) check the validity of data
B) Check the validity of address.
C) connecting to ports
D) None of these.
Answer: B
20. The number of cascade buffer pin in 8259 PIC is
A) 2
B) 3
C) 4
D) 5
Answer: B
21. In 8255 PPI has
A) 28 pin
B) 30
C) 32
D) 40
Answer: D
22. How many Modes are there in 8255 PPI?
A) 1
B) 2
C) 4
D )3
Answer: D
23. The unit which is present in maximum Mode but not in minimum Mode
A) 8288 Bus controller
B) latches
C) Trans receiver
D) None of these
Answer: A
24. How many pins are there in 8257 DMA
A) 124
89 | P a g e

B) 28
C) 30
D) 40
Answer: D
25. If the control word bit is 98H then 8255 PPI will operate in
A) Mode 2
B) Mode 3
C) Mode 1
D) Mode 0
Answer: D
26. If the control word bit is (BC)H the 8255 PPI will operate in
A) Mode 0
B) Mode 1
C) Mode 2
D) none of these
Answer: B
27. If the control word bit is (DO)H then 8255 PPI will operate in
A) Mode 2
B) Mode 1
C) Mode 3
D) none of these
Answer: A
28. Microprocessor is used for
A) program oriented
B) interfacing
C) control oriented
D) none of these
Answer: A
29. The function of latches
A) storing result
B) connecting ports
C) Data
D) Data and address
Answer: D
30. In synchronous data transfer the data transfer rate is more than
A) 10 kbps
B) 15 kbps
C) 20 Kbps
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D) 5 kbps
Answer: C

ASSIGNMENTFULL MARKS-100
SECTION-A

(ANSWER ALL QUESTIONS)

Q.1 Short answer type question: 2*8=16

a) What is meant by interfacing device?

b) How many ports are there in 8255 PPI?
c) why 8255 is known as programmable peripheral interface.
d) Make a control word bit for mode operation where port A and B behaves as input
port.
e) what is meant by 8257 DMA?
f) How many channels are there in 8257 DMA?
g) what is the function of priority resolver?
h) what is the function of 8259 PIC?

SECTION-B

Q.2Focused answer type question: 6*6=36

a) Explain the function of 8255 PPI.

b) Explain the function of 8257 DMA.
c) Explain the pin diagram of 8555 PPI.
d) Explain the pin diagram of 8257 DMA
e) Explain the function of 8259 PIC.
f) Explain the pin diagram of 8259 PIC.
g) Explain the various modes of operation of 8255 PPI.
91 | P a g e

h) Make a control word bit for mode o and mode 1 operation where port A behaves as input
port, port B as output port, port Cupper as input and port Clower output.

SECTION-C

Q.3 Long answer type question: 16*3=48

a) Explain the internal architecture and pin diagram of 8255 PPI.

b) Explain the internal architecture and pin diagram of 8257 DMA.
c) Explain the internal architecture and pin diagram of 8259 PIC.

d)

MODULE-4:8051 MICROCONTROLLER
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Microcontroller is like a mini computer with a CPU along with RAM, ROM, serial ports, timers,
and IO peripherals all embedded on a single chip. It’s designed to perform application specific
tasks that require a certain degree of control such as a TV remote, LED display panel, smart
watches, vehicles, traffic light control, temperature control, etc. It’s a high-end device with a
microprocessor, memory, and input/output ports all on a single chip. It’s the brains of a
computer system which contains enough circuitry to perform specific functions without external
memory. Since it lacks external components, the power consumption is less which makes it ideal
for devices running on batteries. Simple speaking, a microcontroller is complete computer
system with less external hardware.

It basically consists of 40 pin IC chip and operates at 12MHz clock frequency and supply voltage
is +5V DC.

MICROPROCESSOR MICROCONTROLLER
1. A microprocessor is a general- 1. A microcontroller is a dedicated
purpose device which is called a chip which is also called single
CPU. chip computer.
2. It is basically used for program- 2. It is basically used for control-
oriented activity. oriented activity or controlling
3. We have to attach external RAM, the device.
ROM, oscillator with 3. Microcontroller consists of
microprocessor. microprocessor and all other
4. Microprocessors are most units such as RAM, ROM, input
commonly used as the CPU in crystal oscillator etc. for
microcomputer systems. complete input output
5. Microprocessor instructions are operation.
mainly nibble or byte 4. Microcontrollers are used in
addressable. small, minimum component
designs performing control-
oriented applications.
5. Microcontroller instructions are
both bit and byte addressable.

PIN DIAGRAM OF 8051 MICROCONTROLLER

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PIN DESCRIPTION OF 8051 MICROCONTROLLER

Pins 1 to 8: These pins are known as Port 1. This port doesn’t serve any other functions. It is
internally pulled up, bi-directional I/O port.

Pin 9: It is a RESET pin, which is used to reset the microcontroller to its initial values.

Pins 10 to 17: These pins are known as Port 3. This port serves some functions like interrupts,
timer input, control signals, serial communication signals RXD and TXD, etc.

Pins 18 & 19: These pins are used for interfacing an external crystal to get the system clock.

Pin 20: This pin provides the power supply to the circuit.

Pins 21 to 28: These pins are known as Port 2. It serves as I/O port. Higher order address bus
signals are also multiplexed using this port.

Pin 29: This is PSEN pin which stands for Program Store Enable. It is used to read a signal from
the external program memory.

Pin 30: This is EA pin which stands for External Access input. It is used to enable/disable the
external memory interfacing.
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Pin 31: This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the
address-data signal of port.

Pins 32 to 39: These pins are known as Port 0. It serves as I/O port. Lower order address and data bus
signals are multiplexed using this port.

Pin 40: This pin is used to provide power supply to the circuit.

INTERNAL ARCHITECTURE OF 8051 MICROCONTROLLER

The total internal architecture of 8051 microcontroller basically consists of following units such
as
95 | P a g e

1. RAM
• It consists of 128 bytes of RAM out of which 32 bytes are used for register bank
selection.
• There are 4 register banks i.e. Bank-0, Bank-1, Bank-2, Bank-3 and these register banks
can be selected with the help of status control word i.e. RS0 and RS1 which is present
inside the status flags 8051 microcontroller.
• So, with the help of logic bits we can select a particular register bank and the mode
of operation.
2. ROM
• it is basically used to store the predefine data or library function and its memory
capacity is 4kB.
3. CLK frequency / Oscillator
• Inbuilt crystal oscillator is present inside the microcontroller which provide internal
CLK frequency up-to 12MHz.
4. Ports
• There are 4 ports such as Port-0, Port-1, Port-2, Port-3 and each port can transfer and
receives 8-bit of data.
• It is a connecting point or interface between the processor and the external device.
5. Timer and counter
• There are 2 timers i.e. timer-0 and timer-1 which consists of 16 bits registers and is
basically used for time delay operation and providing a matching clock frequency.
6. Processor
• It is basically used for arithmetic ad logical operation and for storing the result, to the
processor status flag is attached which is basically used to check the status of the
output program or for checking the result.
• In 8051 microcontroller the status flag consists of 8-bits out of which 6 are define and
2 are undefined pins.
• The defined pins are Carry flag, Auxiliary carry, RS0, RS1, Overflow flag, Parity flag.
• RS0& RS1 are basically used for register bank selection or for selecting a particular
bank for storing the data. If no bank is selected the by default Bank-0 is selected.

RS1 RS0 REGISTER BANK

0 0 BANK-0
0 1 BANK-1
1 0 BANK-2
1 1 BANK-3
• In case of any arithmetic operation if the result is more than the destination register
value then the data cannot be stored in accumulator so in this case the overflow flag
will tends to logic-1.
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7. Interrupt control
• Basically, it is used for interrupt operation. It has got different interrupt pins such as
INT0, INT1 etc. through which we perform interrupt operation.

INSTRUCTION SETS OF 8051 MICROCONTROLLERS

Instructions are sets of commands given to the processor to perform a specific operation
accordingly in 8051 microcontrollers the total instruction set can be divided into 5 different
types according to type of operation it performs. The instructions are;

1. Data transform instruction

2. Arithmetic instruction
3. Logical instruction
4. Boolean variable and manipulation instruction
5. Programming branching instruction
1. Data transform instruction: It is basically used for transferring the data from one
register to another register or register to memory without changing the content.
E.g. MOV A, R0-Move the content of register R0 to accumulator.
MOV A, #20-Move immediately the data 20H to the accumulator. (Here #
indicates a data)
2. Arithmetic instruction: These are basically used for arithmetic operation such as
addition, subtraction, multiplication, division, increment, decrement etc. In this case the
final result may change.
E.g. SUB A, R0- Subtract the content of R0 from the accumulator and the result is
stored in accumulator.
ADD A, #20- Add immediately the data 20 with accumulator and the result will
stored in accumulator.
3. Logical instruction: These instructions are basically used for logical operation such as
ANA (AND), ORA (OR), XRA (XOR), CMP (COMPARE) etc.
4. Boolean variable manipulation instruction: The instruction on this group are basically
for et or of the status bit and for status flag manipulation.
E.g. CLC- Clear the Carry bit.
STC- Set the carry bit to logic 1.
CMC- Complement of carry bit.
JC- Jump with carry.
JNC- Jump with no carry.
B- Borrow
JNB- Jump with no borrow
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5. Program branching instruction: The instruction under this group are basically used for
conditional or unconditional jump operation or to call to a particular memory address or
to return to the particular memory address.
E.g. CALL, JMP etc.

ADDRESSING MODE OF 8051 MICROCONTROLLER

It is the technique through which we are specifying data for operation or how the operand data
is specified accordingly in 8086 microprocessors. There are 8 different addressing mode
according to the type of operation it performs.

1. Register addressing mode

Immediate addressing mode
2.
3. Direct addressing mode
4. Register indirect addressing mode
5. Base register + Index register addressing mode
1. Register addressing mode: In this type of addressing mode the operand data is not
directly specified in the instruction itself but it is specified by some register.
E.g. MOV A, R0- Move the content of register R0 to accumulator.
2. Immediate addressing mode: In this type of addressing mode the operand data is directly
specified in the instruction itself.
E.g. MOV A, #20-Move immediately the data 20H to the accumulator.
3. Direct addressing mode: In direct addressing mode the operand address is directly
specified in the instruction itself.
E.g.
MOV A, 54H- Move the content of memory address 54H to accumulator.
4. Register indirect addressing mode: In this type of addressing mode the operand data is
not directly transferred to the accumulator; at first it stored in some memory address and
the transferred to the accumulator.
E.g. MOV C, 54H- Move the content of memory address 54H to register C.
MOV A, C- Move the content of register C to the accumulator.
5. Base register + Index register addressing mode: It is the combination of base addressing
mode and index addressing mode.
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Multiple choice question answer:

1. RAM is
A) non-volatile
B) Interfacing
C) Volatile
D) None of these
Answer: C
2. ROM is
A) Volatile
B) interfacing
C) non-volatile
D) None of these
Answer: C
3. The Microcontroller is used for
A) Control oriented activity
B) program-oriented activity.
C) Transfer oriented activity.
D) None of these
Answer: A
4. How many pins are there in 8051 microcontrollers.
A) 124
B) 28
C) 30
D) 40
99 | P a g e

Answer: D
5. The internal clock frequency of 8051 microcontroller is
A) 10 MHz
B) 30
C) 10
D) 12
Answer: D
6. Out of 40 pins in 8051 microcontroller the no. Of pins used for port is
A) 16
B) 32
C) 24
D) none of these
Answer: B
7. In 8051 microcontroller the external clock frequency can be increased to
A)20 MHZ
B)12
C)10
D)none of these
Answer: A
8. Microprocessor is used for
A) program oriented
B) interfacing
C) control oriented
D) None of these
Answer: A
9. The function of latches
A) storing result
B) connecting ports
C) Data
D) Data and address
Answer: D
10. In 8051 microcontroller the timers are
A) Timer 0
B) Timer 1
C) Timer 0 and Timer 1
D) None of these
Answer: C
100 | P a g e

ASSIGNMENTFULL MARKS-100
SECTION-A
(ANSWER ALL QUESTIONS)

Q.1 Short answer type question: 2*8=16

a) What are the different ports are in 8051 microcontroller and what is the function of the
ports in 8051 microcontroller?
b) Write the difference between the microprocessor and microcontroller.
c) What is the function of XTAL1 and XTAL2 in 8051 microcontroller.
d) How much RAM are used for the register bank selection option?
e) How many types of addressing modes are there in 8051 microcontroller?
f) Which control word bit is used for register bank selection?
g) What is the function of timer and it is of how many bits?
h) What is the function of TMO register?
SECTION-B

Q.2 Focused answer type question: 6*6=36

a) Explain the different instruction sets of 8051 microcontroller.

b) What are the register banks and explain the selection of register bank in 8051
microcontroller?
c) Draw the pin diagram of 8051 microcontroller.
d) Explain the different addressing modes of 8051 microcontroller.
e) Describe the importance of 8051 microcontroller.
f) Explain the pin description of 8051 microcontroller.
SECTION-C

Q.3 Long answer type question: 16*3=48

a) Describe the internal architecture of 8051 microcontroller.

b) Explain the function of timer and TMOD register give suitable example. Write a program
to generate a square wave of 2KHz frequency.
c) (i) Explain the different instruction cycles in 8051 microcontroller.

(ii) Explain the status flag in 8051 microcontroller.

101 | P a g e

5th Semester Regular / Back Examination 2019-20

MICROPROCESSOR & MICROCONTROLLER

BRANCH : ELECTRICAL

Max Marks : 100

Time : 3 Hours

Q.CODE : HRB163
Answer Question No.1 (Part-1) which is compulsory, any EIGHT from Part-II and any TWO from Part-III.

The figure in the right hand margin indicate marks.

Part-I

Q1 Only Short Answer Type Questions (Answer All-10) (2×10)

a) List out the control and status signal lines available in 8085.
b) What is the difference between RET and RETI instruction?
c) One user transfers an ASCII character “E” (45H) with no parity bit, one start bit, one stop bit. Find the time take to
transfer 1000 characters using 9600bps.
d) If carry=1 & A=75H and B=3FH prior to execution of SUB A, B, then what will be the content of A after execution.
e) Assume the content of accumulator are 71H and CY=0. Illustrate the accumulator content after RRC and RAR
instructions.
f) Distinguish between interrupt and polling.
g) What is the significance of ALE pin in 8051?
h) Distinguish between RISC processor and CSIC processor.
i) To get a 20 µs delay, which value should be loaded into TH register using mode 1, where XTAL=11.0592MHz.
j) Determine the control words for 8255 PPI, when port A= output, port B= output, port C lower= input, port Cupper=
input.

Part-II
Q2 Only Focused-Short Answer Type Questions- (Answer Any Eight out of Twelve) (6×8)
a) Explain the various steps of instruction decoding and execution in 8085.
b) Write the program to transfer the bytes of ROM space into RAM location starting at 50H.
c) Draw the timing diagram for execution of the instruction MVI A, 54H.
d) Write a subroutine to generate delay of 220ms. Assume crystal frequency = 12MHz.
e) How does data transfer from memory to microprocessor occurs? Explain in detail.
f) Describe all steps of interrupt process of 8085.
g) Do the schematic diagram to show the minimum interface between a computer and a peripheral.
h) What do you mean by stack and bank1 conflict with reference to their address in 8051? What steps are being
followed to overcome this problem?
i) Assume that we have 4 bytes of hexadecimal data: 35H, 42H, 3FH and 52H.
a. Find the checksum byte.
b. Perform the checksum operation to ensure data integrity.
c. If the second byte 42H has been changed to 22H, show how checksum detects the error.
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j) Assume that the lower three bits of P1 are connected to three switches. Write a program to send the ASCII
characters 0,1,2,3,45,6,7 based on the status of the switches.
k) How direct memory data transfer occurs in 8085? Discuss using suitable figure.
l) Write a program to read 200 bytes of data from P1 and save the data in external RAM starting at RAM
location 3000H.

Part-III

Only Long Answer Type Questions (Answer Any Two out of Four)

Q3 Draw the block diagram of the 8259 and explain how it can be used for increasing the interrupt capabilities of 8085.
Explain how 8259 read the status and change the interrupt mode during a program execution.

(16)

Q4 Describe the internal hardware architecture of intel 8086 in details using suitable schematics.
(16)

Q5 Write an assembly language program to divide one 16bit number with an 8-bit number in 8085.
(16)

Q6 Draw and explain the architecture details of 8051 and discuss the different addressing modes of 8051.
(16)

SOLUTION
Q1

a) These signals are used to identify the nature of operation. There are 3 control signal and 3 status signals. Three
control signals are RD, WR & ALE and three status signals are IO/M, S0 & S1.

j)

7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 1

= 89H

Q2
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a) The instructions which are to be executed by microprocessor are first stored in the memory
of the processor and then executed. But the processor does not execute the instructions
directly. It reads the instruction byte by byte and then executes it.

Consider MVI A, 18H. when the instruction is to be executed, the microprocessor gets the
Opcode for MVI A and performs the necessary operation on the data which is 18H in this case.
The Opcode for MVI A is 3EH. So the microprocessor first reads this Opcode from the
instruction and then performs the operation specified by Opcode over the data given.

Now let us assume we want to store the above instruction in a specific address say 5500H. We
know that in 8085 processor only one byte can be stored in each address location. Therefore
the Opcode 3EH is stored at the location 5500H and the data 18H is stored at the next
location 5501H.

Now for execution of this instruction the processor has to send the address to the memory for
reading. Then the MEMR’ signal is activated. As soon as this signal is activated the memory
places the Opcode byte (3EH) on the data bus.

The above process is considered as a single cycle and is called the OPCODE FETCH CYCLE. The
period during which the Opcode is fetched from address to the data bus is called as Opcode
fetch cycle.

A microprocessor by default knows that the first byte which is under execution is always
Opcode. The internal data bus sends the Opcode to the instruction decoder. The instruction
decoder decodes the Opcode and identifies it as MVI A instruction. As soon as this
information is obtained, the microprocessor searches for the data on which this operation
should be performed.

To find the data for performing the operation the microprocessor instructs the timing and
control unit to generate a proper timing signal to obtain the data. As a result of the timing
signal the program counter is increased by 1. So, the address bus moves from 5500H to
5501H. Now we know that the data 18H is placed at 5501H. So, when the address bus is
placed at 5501H, it identifies the data and the MEMR’ signal is activated. After the activation
of this signal the data is placed on the internal address bus and then it is moved to the
accumulator. Then the MVI A operation is performed on the data 18H and the result is sent to
the respective registers.

This process of placing the address and reading the data is considered as a single cycle and
this cycle is called Memory Read cycle. In general, these cycles are called as machine cycles.

b)
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c)

f)
Q4

The total internal architecture of 8086 microprocessor can be basically divided into two different
units.

1.Bus Interfaces Unit (BIU)

2.Execution Unit (EU)
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1.Bus Interfaces Unit (BIU):

• It is responsible for transfer of data and address between the processor, memory and
input output device.
• It receives the data from the IO device and stored the data in a 6 bytes instruction
queues in FIFO sequence and this data is transferred to the execution unit for
arithmetic and logical operation.
• The function of different units of bus interface unit are
6 bytes instruction queue
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o Its function is to receive 6 no. of 8bit data at a time and stores the data in it and
then this data can be transferred to execution unit for performing arithmetic
and logical operation i.e. execution operation.
o The data is received from IO device to the 6 bytes instruction queue in FIFO
sequence.

Segment register

o There are 4 segment register

▪ Code segment register (CS): It basically used to store the opcode of an
instruction.
▪ Data segment register (DS): It basically used to store the operand of an
instruction.
▪ Extra segment register (ES): It is basically used to store the character or
string instruction such as consonant, vowel, character etc.
▪ Stack segment register (SS):Stack is a set of memory location whose
address is different from main memory address.
✓ We can transfer the data from main memory to stack memory by
push instruction and we can receive the data from stack memory to
main memory by pop instruction. So, segment register is basically
used to store the stack memory value.
✓ To locate a particular memory address, we take the help of stack
pointer and given by the command LXI SP 9605H.

Instruction pointer (IP)

o Its function is same as that of program counter of 8085 microprocessor and is

basically used to check whether the address for next instruction is available or
not. So, it stores the OFF-SET address.

Bus control and address generation

o It is basically used to generate 20 bits effective memory address or physical

memory address.
o One address is generated from the segment register which is of 16 bit and
when the address goes to the bus control and address generation it gets
multiplied by the multiplier circuit of value 10 H. So, at the output we get a
segment address of 20 bit.
o Another address is generated from the instruction pointer which is of 16 bit
and is known as OFF-SET address or assembly line address.
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o So, when this address goes to the bus control and address generation, it gets
added of with the help of adder circuit which is present inside the bus control
and address generation.
o Hence the 20-bit segment address is added up with the 16-bit IP address with
the help of adder circuit and at the output we get a 20-bit effective memory
address or physical memory address.
o Effective memory address (EMA) or Physical memory address (PMA) = Segment
address*10H +Instruction pointer
o The block diagram of physical address generation is shown as follows.

[Block diagram of physical address generations]

2.Execution Unit (EU):

• The execution unit receives the opcode of an instruction from the 6byte instruction
queue decodes it and perform the arithmetic and logical operation and stores the
result.
• The function of different units of execution units are
ALU

o It is basically used to perform the arithmetic and logical operation such as addition,
subtraction, multiplication, division, increment, decrement, comparison.
o After the arithmetic and logical operation, the result is check by the status flag.
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Status Flag

o The status flags are basically used to check whether the result is writing or wrong.
o Accordingly, in 8086 microprocessor there are 9 active status flags out of which 6 are
conditional flag and 3 are control flag.

Conditional flag: Conditional flags are those where the output depends upon the
input. The conditional flags are Sign flag, zero flag, Auxiliary flag, Parity flag, Carry
flag and overflow flag.
➢ Sine flag: After the arithmetic operation if the result is negative then sign
flag is tends to logic 1 otherwise it will tend to logic 0.
➢ Zero flag: After the arithmetic operation if the result is zero then zero flag
will tend to logic 1 otherwise it will tend to logic 0.
➢ Auxiliary flag: After the arithmetic operation if there is a carry from 3rd to
4th bit then auxiliary carry will tends to logic 1 otherwise it will tend to logic
0.
➢ Parity flag: After the arithmetic operation if the result of the sum contains
even no. of 1’s then parity flag will tend to logic 1 otherwise it will tend to
logic 0.
➢ Carry flag : After the arithmetic operation if the result is more than 8 bit
then there will be a carry from 7-8 bit so carry flag will tends to logic 1 and
in case of 16 bit operation if there is a carry from 15 to 16 bit the carry flag
will tends to logic 1 otherwise it will tends to logic 0.
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➢ Overflow flag: After the arithmetic operation if the result is more than 16
bits, in that case the data cannot be stored in accumulator or destination
register. So, in that case the overflow flag will tends to logic 1 otherwise it
will tend to logic 0.

So, in conditional flag the output is depends on the input

Control flag: The control flags are basically used for control-oriented activity such
as to stop the program, set or reset the operation, status flag manipulation,
interrupt operation. So, in this case it is used for control-oriented activity and here
the output is does not depends upon input. The control flags are Directional flag,
Interrupt flag, Trap flag.
➢ Directional flag: In case of character or string operation in that case the
directional flag will tends logic 1 otherwise it will tend to logic 0.
➢ Interrupt flag and Trap flag: These two flags are basically used as
interrupt operation.

Resistors

o There are two types of register in 8086 microprocessor such as General-purpose

register and Special purpose register.
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General-purpose register: The general-purpose register are AH and AL i.e. A

higher order and A lower order. Similarly, B H and BL, CH and CL, DH and DL
respectively. Each register can store individually 8bit of data and combine form it
can store 16bit of data so,
AH + AL = AX (16 bit)
BH + BL = BX (16 bit)
CH + CL = CX (16 bit)
DH + DL = DX (16 bit)
e.g. MOV AH, 08H- Move immediately the data 08 toAH register.
MOV AL, 08H- Move immediately the data 08 toAL register.
MOV AX, 1264H- Move the 16-bit data 1264H to Ax register.

o Since these registers are commonly used for storing the data temporarily for any
arithmetic and logical operation so these are known as general-purpose register.
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Special purpose register: The special purpose registers are Stack pointer (SP),
Base pointer (BI), Source index register (SI), Destination index register (DI). These
are known as special purpose register because they are used for some specific
operation and these are 16-bit registers.

➢ Stack pointer (SP): Through stack pointer we can locate to a particular

stack pointer address e.g. LXI SP, 9505H.
➢ Base pointer (BP): It is basically use to store the OFF-SET address (value
of instruction pointer address).
➢ Source index register (SI): It is basically used to store the string address
e.g. MOV SI, [2000H]- Move the OFF-SET address 2000H to SI register.
➢ Destination index register (DI): It is basically used to store the end
address e.g. MOV DI, [2005H]-Move immediately the OFF-SET address 2005H
to DI register.

Q6
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The total internal architecture of 8051 microcontroller basically consists of following units such
as

8. RAM
• It consists of 128 bytes of RAM out of which 32 bytes are used for register bank
selection.
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• There are 4 register banks i.e. Bank-0, Bank-1, Bank-2, Bank-3 and these register banks
can be selected with the help of status control word i.e. RS 0 and RS1 which is present
inside the status flags 8051 microcontroller.
• So, with the help of logic bits we can select a particular register bank and the mode
of operation.
9. ROM
• it is basically used to store the predefine data or library function and its memory
capacity is 4kB.
10. CLK frequency / Oscillator
• Inbuilt crystal oscillator is present inside the microcontroller which provide internal
CLK frequency up-to 12MHz.
11. Ports
• There are 4 ports such as Port-0, Port-1, Port-2, Port-3 and each port can transfer and
receives 8-bit of data.
• It is a connecting point or interface between the processor and the external device.
12. Timer and counter
• There are 2 timers i.e. timer-0 and timer-1 which consists of 16 bits registers and is
basically used for time delay operation and providing a matching clock frequency.
13. Processor
• It is basically used for arithmetic ad logical operation and for storing the result, to the
processor status flag is attached which is basically used to check the status of the
output program or for checking the result.
• In 8051 microcontroller the status flag consists of 8-bits out of which 6 are define and
2 are undefined pins.
• The defined pins are Carry flag, Auxiliary carry, RS0, RS1, Overflow flag, Parity flag.
• RS0& RS1 are basically used for register bank selection or for selecting a particular
bank for storing the data. If no bank is selected the by default Bank-0 is selected.

RS1 RS0 REGISTER BANK

0 0 BANK-0
0 1 BANK-1
1 0 BANK-2
1 1 BANK-3
• In case of any arithmetic operation if the result is more than the destination register
value then the data cannot be stored in accumulator so in this case the overflow flag
will tends to logic-1.
14. Interrupt control
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• Basically, it is used for interrupt operation. It has got different interrupt pins such as
INT0, INT1 etc. through which we perform interrupt operation.
ADDRESSING MODE OF 8081 MICRCONTROLLER

It is the technique through which we are specifying data for operation or how the operand data
is specified accordingly in 8086 microprocessors. There are 8 different addressing mode
according to the type of operation it performs.

6. Register addressing mode

7. Immediate addressing mode
8. Direct addressing mode
9. Register indirect addressing mode
10. Base register + Index register addressing mode
6. Register addressing mode: In this type of addressing mode the operand data is
not directly specified in the instruction itself but it is specified by some register.
E.g. MOV A, R0- Move the content of register R0 to accumulator.
7. Immediate addressing mode: In this type of addressing mode the operand data
is directly specified in the instruction itself.
E.g. MOV A, #20-Move immediately the data 20H to the accumulator.
8. Direct addressing mode: In direct addressing mode the operand address is
directly specified in the instruction itself.
E.g.
MOV A, 54H- Move the content of memory address 54H to accumulator.
9. Register indirect addressing mode: In this type of addressing mode the operand
data is not directly transferred to the accumulator; at first it stored in some
memory address and the transferred to the accumulator.
E.g. MOV C, 54H- Move the content of memory address 54H to register C.
MOV A, C- Move the content of register C to the accumulator.
10. Base register + Index register addressing mode: It is the combination of
base addressing mode and index addressing mode.
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