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From Bits and Gates to C and Beyond

Digital Logic Structures

Chapter 3

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 Transistor: Building Block of Computers

Microprocessors contain billions of transistors

• Intel Broadwell-E5 (2016): 7 billion.
• IBM Power 9 (2017): 8 billion.

Logically, each transistor acts as a switch

Combined to implement logic functions
• AND, OR, NOT.

Combined to build higher-level structures

• Adder, multiplexer, decoder, register, …

Combined to build processor

• LC-3.

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 A Simple Switch Circuit

A wall switch determines whether current flows through the light bulb.

If switch is closed, current flows, lamp is ON, voltage across lamp is non-zero.
If switch is open, no current flows, lamp is OFF, voltage across lamp is zero.

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 Transistor = Voltage-Controlled Switch 1

Figure shows an N-type transistor.

When Gate voltage is positive, relative to Source, transistor acts as a
short circuit: a closed switch.
When Gate voltage is zero (or negative), relative to Source, transistor
acts as an open circuit: an open switch.

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 Transistor = Voltage-Controlled Switch 2

Consider the circuit below. The bar at the top represents the high voltage rail
(+1.2V) and the triangle at the bottom represents ground (0V).

When Gate = +1.2V, what happens?

• Gate-to-source voltage > 0.

• Transistor = closed switch.

• Current flows, lamp is ON.

When Gate = 0V, what happens?

• Gate-to-source voltage = 0.
• Transistor = open switch.
• No current flows, lamp is OFF.

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 Transistor = Voltage-Controlled Switch 3

A different type of transistor is shown below, the P-type transistor.

Notice the little "bubble" on the gate.

When Gate voltage is negative, relative to

Source, transistor acts as a short circuit: a
closed switch.
When Gate voltage is zero (or positive),
relative to Source, transistor acts as an open
circuit: an open switch.

NOTE: This behavior is the opposite of the

N-type. Behavior is complementary.

We use both N-type and P-type transistors together to implement logic

gates. This is known as CMOS or Complementary MOS logic.

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 Logic Gate

A logic gate is a circuit that transforms binary input signals into a single
binary output signal. Signals are voltages.

Binary: +1.2V = 1 (true), 0V = 0 (false)

P-type transistors: source connected to +1.2V

• When gate = 1, transistor is OFF.
• When gate = 0, transistor is ON.

N-type transistors: source connected to 0V

• When gate = 1, transistor is ON.
• When gate = 0, transistor is OFF.

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 NOT Gate (Inverter)

Example:
When input = 0, P-type transistor
turns on and N-type transistor
turns off. Output is connected to
+1.2V, so output = 1.

Logic gate is described

using a truth table.

Input Output
0 1
1 0

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 NOR Gate

When either input is 1, output is 0.

Example:
When B = 1, N-type transistor
turns on and output (C) is
connected to GND. Both inputs
must be 0 to connect C to +1.2V.

A B C
0 0 1
0 1 0
1 0 0
1 1 0

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 OR Gate

When either input is 1, output is 1.

Add NOT after NOR.

A B C D
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1

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 Why do we need NOT after NOR?

Why can't we simply put the P-type on the bottom and the N-type on top?

(b) A B C
0 volts 0 volts 1.0 volts
0 volts 1.2 volts 0.7 volts
1.2 volts 0 volts 0.7 volts
1.2 volts 1.2 volts 0.7 volts

Does not work because of the electrical properties

of the transistors.
Must always connect P to + and N to GND
for CMOS circuit to work properly.

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 NAND and AND Gates

NAND: When any input is 0, output is 1.

AND: When all inputs are 1, output is 1.
A B C
0 0 1
0 1 1
NAND
1 0 1
1 1 0

A B D
0 0 0
0 1 0 AND
1 0 0
1 1 1

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 Standard Symbols for Logic Gates

Instead of drawing the circuit diagram, we can abstract these logic gates
and give each a symbol. The bubble indicates inversion (NOT).

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 Gates with more than one input

Notion of AND and OR generalizes to more than two inputs.

AND: output = 1 if ALL inputs are 1
OR: output = 1 if ANY input is 1

(a) A B C OUT
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
Challenge: Draw the CMOS circuit
1 0 1 0 for a 3-input AND gate.
1 1 0 0
1 1 1 1
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 Building Logic Circuits from Gates

To build more complex logic functions, we create circuits using the basic
logic gates.

Combinational Logic Circuits

• Output depends only the current input values.
• Stateless -- no "memory" of the past.

Sequential Logic Circuits

• Output depends on both past and current input values.
• "remembers" inputs from the past.
• Example: output = 1 if we see four zero inputs in a row.

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 Combinational Logic Circuits

We need both combinational and sequential circuits to build a computer.

First, we will introduce three useful combinational circuits:

Decoder: recognizes specific bit patterns

Multiplexer: chooses among various inputs

Adder: performs addition on unsigned or 2's complement integers

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 Decoder

A decoder has n inputs and 2n outputs.

Each output corresponds to one possible input combination.
Exactly one output will be 1, and all others will be 0.

2-bit decoder

Useful for converting

encoded values (integers)
into a set of control signals.
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 Multiplexer (Mux)

A mux has 2n data inputs, n select inputs, and one output.

The select bits are used to "choose" one of the data inputs to flow
through to the output.

4-to-1 mux
4 input bits,
2 select bits

This is the standard symbol for a mux. S is a two-bit signal.

S1 is the most significant bit, and S0 is the least significant bit.
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 Full Adder (1-bit binary addition)

A full adder represents one column in a binary addition operation.

A and B are the bits to be added. Cin is the carry-in from the previous
column (from the right). There are two outputs: S = sum, Cout = carry-out
(to the next column).
Cin A B S Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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 N-bit Adder

Feed Cout from one bit into Cin of the next bit...

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 Logical Completeness

Can implement any truth table using only AND, OR, and NOT.
See process below. This may not create the best circuit, but it will result in
a correct circuit. (Optimizing circuits is for another class...)

A B C D
0 0 0 0
1. AND combinations
0 0 1 0
that yield a "1" in the
0 1 0 1 truth table. (Invert
0 1 1 0 inputs as needed.)
1 0 0 0
2. OR the results of
1 0 1 1
the AND gates.
1 1 0 0
1 1 1 0

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 Sequential Logic Circuits

Output depends on previous state.

Must store previous information in order to act on it.
Example: ticket counter.
• When input is 1, output the "next" count: 0, 1, 2, 3, 4, 5, ...
• Output depends on stored data (the current count) plus the input.

Requires storage element (memory).

Will be used to implement "state machines" that perform a prescribed
sequence of actions, depending on inputs.

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 Storing One Bit: R-S Latch

A latch uses feedback to store a bit of information. In the circuit below,

inputs R and S are both 1. The output may be either 0 or 1.
NOTE: This is different than combinational logic -- different possible
outputs for a particular input.

As long as R = S = 1, the output is stable. It either stays 0 or stays 1.

This is known as the quiescent state. The circuit "remembers" this data.

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 Clearing the latch: R = 0

To force the output (the stored data) to zero, set R = 0 and S = 1.

Once the latch is cleared, make R = S = 1 to remember the data.

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 Setting the latch: S = 0

To force the output (the stored data) to one, set R = 1 and S = 0.

Once the latch is set, make R = S = 1 to remember the data.

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 R-S Latch Summary

R=S=1
R S Q'
Hold current value in latch 0 0 illegal
R = 0, S = 1 0 1 0
Clear/reset latch (value = 0) 1 0 1
1 1 Q
R = 0, S = 1
Set latch (value = 1) Q' is output. Q is previous output.

What about R = 0, S = 0?
Both outputs = 1, final state determined by electrical properties of the gates.
Don't do it!!! This set of inputs is prohibited and should never occur during the
operation of the latch.

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 D-Latch: Simpler Control for One-Bit Latch

D = data input, WE = write enable

When WE = 0, latch output does not change. (D is irrelevant.)
When WE = 1, latch output = D.

NOTE: This uses an R-S latch. R and S will never both be zero.
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 The Concept of Memory 1

Now that we can store a bit, we can build a memory: a k × m array of

stored bits.

Address Space:
number of locations
(usually a power of 2)

Addressability:
number of bits per location (for
example, byte-addressable)

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 The Concept of Memory 2

We have an array of k = 2 memory locatios.

n

Each location stores an m-bit value. The value 𝑚 is known as the

addressability or the width of the memory.
Each location has a unique identifier, known as an address.
Addresses range from 0 to k − 1. The number of addresses (k) is known
as the address space of the memory.
WE (write enable) indicates whether we want to retrieve the stored value
(WE = 0) or store a new value (WE = 1).

Memory Operation Inputs Output

Address (n bit) Data (m bits) stored at
READ
WE = 0 specified address
Address (n bits)
WRITE New Data (m bits) New Data (m bits)
WE = 1

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 A Memory Circuit

Bits are stored in an

array of D-latches.
An m-bit value in each row.
Address is decoded to
select a row.
Mux is used to output
selected bit in each column.
To write, data input at the
top and WE changes the
latches in selected row.

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 Example: Reading Address 3 of a 4×3 memory

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 Notation: Mult-bit values

Convention: Bits are numbered from right to left

• Bit 0 is the least significant (all the way to the right).
• Bit n-1 is the most significant (all the way to the left).

Use brackets to denote a range of bits: A[left:right]

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 More Info about Memory

This is a not the way actual memory is implemented.

• Fewer transistors, much more dense, relies on electrical properties.

But the logical structure is very similar.

• Address decoder / word select line / word write enable.

Two basic kinds of RAM (Random Access Memory)

Static RAM (SRAM)
• Fast, maintains data as long as power applied.

Dynamic RAM (DRAM)

• Slower but denser, bit storage decays – must be periodically refreshed.

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 Sequential Logic Circuit: Finite State Machine

Uses both combinational logic and storage

"Remembers" state, computes output (and new state) depending on
previous state and new input data

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 What is State?

The state of a system is a snapshot of all the relevant data that describes
the system.

• The state of a basketball game can be represented by the scoreboard:

Number of points, time remaining, possession, etc.
• The state of a tic-tac-toe game can be represented by the placement of
X’s and O’s on the board.

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 Example: A Combination Lock

Output (lock open / closed) depends

on a sequence of actions.
For example, R-13, L-22. R-3.

Four States:
A: The lock is not open, and no relevant operations have been performed.
B: The lock is not open, and the user has completed the R-13 operation.
C: The lock is not open, and the user has completed R-13, followed by L-
22.
D: The lock is open. (User completed R-13, L-22, and R-3.)

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 State Diagram

Description of a state machine

Shows all states (nodes), output value for each state (value in node),
transitions (edges) between states for different input values (edge labels).

Output value is not shown

in this example.
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 Finite State Machine: Definition

A finite state machine (FSM) is a description of a system with the

following elements:

1. A finite set of states.

2. A finite number of external inputs.
3. A finite number of external outputs.
4. An explicit specification of all state transitions.
5. An explicit specification of what determines each output value.

A state diagram is one representation of an FSM.

• Inputs trigger state transitions.
• An output value is associated with each state (or with each transition in
some specifications).

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 Another Example: Drink Machine

Suppose you have an old drink machine that accepts nickels and dimes.
Inserting 15 cents will unlock the drink dispenser.

A: Open -- one drink can be removed.

B: User has inserted five cents.
C: User has inserted ten cents.
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 Synchronous versus Asynchronous

In examples so far, no fixed notion of time. User can wait any amount of
time between inputs. This is an asynchronous system. The inputs
happen whenever they happen...
In a synchronous system, state transitions happen at fixed time
intervals. At each interval, the input and state determine the transition.
A clock signal is used to trigger the state transitions. For example, a
transition happens whenever the clock changes from 0 to 1.

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 Implementing a Finite State Machine

Combinational Logic -- given current state and input, what is the next
state and output?
Storage Elements -- stores state bits until next cycle

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 FSM Example: Danger Sign

One input: on/off switch.

Five outputs: lights.
When sign is off, no lights.
When sign is on:

1. No lights
2. 1 and 2 on.
3. 1, 2, 3, and 4 on.
4. 1, 2, 3, 4, and 5 on.

Repeats 1 to 4 as long as switch is on.

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 Danger Sign: State Diagram

Four states. Assign a

two-bit label to each state.
Input: 1 = on, 0 = off.
State transitions are labeled
with the input that causes
that transition.
Outputs: 1 bit per light.

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 Danger Sign: Implementation
Given current state,
what should outputs be?

Given current state and

input, what should
the next state be?

One storage element for each state bit.

Current state (left) is input to logic.
Next state (right) is output from logic,
written to storage on next clock cycle.

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 Danger Sign: Truth Tables

Two truth tables: one for each combinational logic circuit.

On left, translate state S[1:0] to output signals:
W = lights 1 & 2, X = lights 3 & 4, V = light 5
On right, translate input (Switch) and state S[1:0] to next state: S'[1:0]

S[1:0] W X V Switch S[1:0] S'[1:0]

00 0 0 0 0 00 00
01 1 0 0 0 01 00
10 1 1 0 0 10 00
11 1 1 1 0 11 00
1 00 01
All information can be 1 01 10
read from the state diagram. 1 10 11
1 11 00

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 Danger Sign: Combinational Logic

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 Storage Elements: D-Latch?

Suppose we use a D-Latch to store each data bit.

We want the new state to be written into the latch each clock cycle. So
we can use the Clock signal as write-enable (WE).
Problem:
As long as WE = 1, the new data will change the stored data.
This means that we need WE (Clock) to go back to zero before the next
state is prepared by the logic circuit. Otherwise, we would transition
through two or more states in a single clock cycle.
This would require the clock to be carefully tuned to our circuit, and it's
unreliable -- some gates are faster than others, speed depends on
temperature, etc., etc. BAD DESIGN!
Solution: flip-flop!

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 Storage Elements: Flip-flop

A flip-flop uses two latches to separate the reading phase and the writing
phase of the clock cycle.

When Clock = 0 (write phase), new data (D) When Clock = 1 (read phase),
is stored in the Master latch, but output (Q) data from Master is stored into the
does not change. Slave and the output (Q) changes
to the new value.

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 Timing Diagram

As long as worst-case propagation delay through the logic is less than half of the
clock cycle, state will properly change each clock cycle.
Because of this behavior, flip-flop is considered an edge-triggered storage
element: its state changes on the clock edge. A latch is level-triggered, because it
changes as long as the WE signal is enabled.

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 FSM Summary

State diagram, truth tables, and circuit are three different representations
of the state machine. Given one, can easily derive the other two.

Switch S[1:0] S'[1:0]

0 00 00
S[1:0] W X V 0 01 00
00 0 0 0 0 10 00
01 1 0 0 0 11 00
10 1 1 0 1 00 01
11 1 1 1 1 01 10
1 10 11
1 11 00

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 Preview: LC-3 Data Path

A computer is built from the

components described in this
chapter:
Multiplexer
Decoder
Adder
Registers (storage)
Finite State Machine
In the next chapters, we’ll show
how they fit together to make a
programmable computing device.

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© 2020 McGraw Hill. All rights reserved. Authorized only for instructor use in the classroom.
No reproduction or further distribution permitted without the prior written consent of McGraw Hill.