University of Zakho

Faculty of Science
Department of CS.

Microprocessors

Lecture #5
Memory, & Memory Organization
Interfacing SRAM and EPROM
Interfacing I/O and peripheral devices
Previous Lecture

❑ Microprocessor
❑ Addressing Modes
❑ Instruction Set

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Contents

5.0 Objectives
5.1 Memory
5.2 Memory organization in 8086
5.3 Interfacing SRAM and EPROM
5.4 ROM Memory
5.5 RAM Memory
5.6 Memory Hierarchy
5.7 Interfacing I/O and peripheral devices
5.8 8086 and 8088 comparison

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5.0 Objective of This Lecture

At the end of this lecture you will become familiar with:

❑ Memory & Memory Organization in 8086
Microprocessor
❑ Interfacing SRAM and EPROM
❑ Interfacing I/O and peripheral devices

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 5.1 Memory
Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost 

Primary or Main Memory

▪ Storage area which can be directly accessed by
Memory microprocessor
▪ Store programs and data prior to execution
Store Programs
▪ Should not have speed disparity with processor
and Data
 Semi Conductor memories using CMOS
technology
▪ ROM, EPROM, Static RAM, DRAM

Secondary Memory
▪ Storage media comprising of slow devices such as
magnetic tapes and disks
▪ Hold large data files and programs: Operating
system, compilers, databases, permanent
programs etc. 5
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5.2 Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two consecutive memory

locations; for LSB and MSB

Address of word : Address of LSB

Bank 0 : A0 = 0  Even addressed

memory bank

Bank 1 : 𝑩𝑯𝑬 = 0  Odd

addressed memory bank

Figure 5.1 Memory Organization in 8086

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5.2 Memory organization in 8086 (Cont’d.)

# Operation ��𝑯𝑬 A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation byte from
odd bank is transferred
1 0 D7 – D0 in first operation byte from
odd bank is transferred 7
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5.2 Memory organization in 8086 (Cont’d.)

Available memory space = EPROM + RAM

Allot equal address space in odd and even bank for both
EPROM and RAM

Can be implemented in two IC’s (one for even and other for
odd) or in multiple IC’s

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Blank Slide

Take Rest
Refresh Your Mind

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5.3 Interfacing SRAM and EPROM

Memory interface  Read from and write in to a set of

semiconductor memory IC chip

EPROM  Read operations

RAM  Read and Write

In order to perform read/ write operations,

Memory access time  read / write time of the processor

Chip Select (CS) signal has to be generated

Control signals for read / write operations

Allot address for each memory location

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5.3 Interfacing SRAM and EPROM (Cont’d.)
Typical Semiconductor IC Chip

Figure 5.2 Interfacing Memory Organization (SRAM & EPROM)

No of Memory capacity Range of address
Address pins in hexa
In Decimal In kilo In hexa

20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF

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5.3 Interfacing SRAM and EPROM (Cont’d.)
Memory map of 8086

EPROM’s are mapped at FFFFFH

 Facilitate automatic execution of monitor programs and creation of
interrupt vector table

RAM are mapped at the beginning; 00000H is allotted to RAM

Figure 5.3 Memory Map 8086 12

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5.3 Interfacing SRAM and EPROM (Cont’d.)
Monitor Programs
 Programing 8279 for keyboard scanning and display
refreshing

 Programming peripheral IC’s 8259, 8257, 8255, 8251, 8254 etc

 Initialization of stack

 Display a message on display (output)

 Initializing interrupt vector table

Note : 8279 Programmable keyboard/ display controller

8257 DMA controller

8259 Programmable interrupt controller

8255 Programmable peripheral interface

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5.4 ROM Memory
The read-only memory (ROM) permanently stores programs and data
that are resident to the system and must not change when power supply is
disconnected.
Types of ROM
1. ROM - Read Only Memory
2. PROM - Programmable Read Only Memory
3. EPROM - Erasable Programmable Read Only Memory
4. EEPROM - Electrically Erasable Programmable Read Only Memory
5. Flash EEPROM memory

Each type has unique characteristics, but all types of ROM memory have
two things in common:
➢ Data stored in these chips is non-volatile -- it is not lost when power is
removed.
➢ Data stored in these chips is either unchangeable or requires a special
operation to change. 14
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5.4 ROM Memory (Cont’d.)
1. Read Only Memory (ROM)
The ROM is permanently programmed so that data are always
present, even when power is disconnected. This type of memory is
often called nonvolatile memory, because its contents do not
change even if power is disconnected.

Figure 5.4 Read Only Memory (ROM)

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5.4 ROM Memory (Cont’d.)
2. Programmable Read Only Memory (PROM)
PROM memory devices are also available, although they are not
as common today. The PROM (programmable read-only memory)
is also programmed in the field by burning open tiny NI-chrome or
silicon oxide fuses; but once it is programmed, it cannot be erased.

Figure 5.5 Programmable Read Only Memory (PROM)

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5.4 ROM Memory (Cont’d.)
2. Programmable Read Only Memory (PROM)
Creating ROM chips totally from scratch is time-consuming and
very expensive in small quantities.
PROM chips have a grid of columns and rows just as ordinary
ROMs do. The difference is that every intersection of a column and
row in a PROM chip has a fuse connecting them. A charge sent
through a column will pass through the fuse in a cell to a grounded
row indicating a value of 1.

Since all the cells have a fuse, the initial (blank) state of a PROM
chip is all 1s. To change the value of a cell to 0, you use a
programmer to send a specific amount of current to the cell. The
higher voltage breaks the connection between the column and row
by burning out the fuse. 17
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5.4 ROM Memory (Cont’d.)
3. Erasable Programmable Read Only Memory (EPROM)
This type is similar to PROM, except that the content of it can be
erased by exposing it to ultra violet light to restore it to its
unprogrammed state. EPROMs are configured using an EPROM
programmer that provides voltage at specified levels depending
on the type of EPROM used.

Figure 5.6 EPROM

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5.4 ROM Memory (Cont’d.)
3. Erasable Programmable Read Only Memory (EPROM)
The EPROM has a grid of columns and rows and the cell at each
intersection has two transistors. The two transistors are separated
from each other by a thin oxide layer. One of the transistors is
known as the floating gate and the other as the control gate.
The floating gate's only link to the row (wordline) is through the
control gate. As long as this link is in place, the cell has a value of
1. To change the value to 0 requires a process called Fowler-
Nordheim tunneling.

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5.4 ROM Memory (Cont’d.)

Figure 5.7 The pin-out of the 2716, 2K × 8 EPROM. (Courtesy of Intel Corporation.) 20
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5.4 ROM Memory (Cont’d.)
4. Electrically Erasable Programmable Read Only Memory
(EEPROM)
EEPROM chips remove the biggest drawbacks of EPROMs.
In EEPROMs:
1. The chip does not have to removed to be rewritten.
2. The entire chip does not have to be completely erased to
change a specific portion of it.
3. Changing the contents does not require additional dedicated
equipment.
Instead of using UV light, you can return the electrons in the cells of
an EEPROM to normal with the localized application of an electric
field to each cell. This erases the targeted cells of the EEPROM,
which can then be rewritten. EEPROMs are changed 1 byte at a
time, which makes them versatile but slow. 21
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 5.4 ROM Memory (Cont’d.)
5. Flash EEPROM Memory
EEPROM chips remove the biggest drawbacks of EPROMs.
It is a type of EEPROM that uses in-circuit wiring to erase by
applying an electrical field to the entire chip or to predetermined
sections of the chip called blocks. This erases the targeted area of the
chip, which can then be rewritten. Flash memory works much faster than
traditional EEPROMs because instead of erasing one byte at a time, it
erases a block or the entire chip, and then rewrites it. The electrons in the
cells of a Flash-memory chip can be returned to normal ("1") by the
application of an electric field, a higher-voltage charge.

Figure 5.8 A serial EEPROM interface

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5.4 ROM Memory (Cont’d.)
Some images of ROM Memory

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5.5 RAM Memory
Random Access Memory (RAM)

❑ The term “random” means any memory location can be accessed

in the same amount of time regardless of its position in the
memory.
❑ Volatile memory.
❑ Read and Write to any location given a valid address.
❑ Sends/Receives data quickly between CPU .
❑ This is way quicker than using just the HDD
❑ RAM holds temporary data used by any open application or
active / running process
❑ Multiple types of RAM, which have different Speeds, power
consumption and technology.
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5.5 RAM Memory
1. Static Random Access Memory (SRAM)
❑ SRAM This type consist essentially of internal Flip-Flop that store
binary information. The stores information remain valid as long
as power is applied to the unit.
❑ Based on flip flops. Vcc
❑ Fast but relatively large.
❑ Consume a lot of power.
❑ Used for memory applications that J Q
are small but fast.
CLK

Figure 5.9 SRAM Flip Flop

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5.5 RAM Memory (Cont’d.)
2. Dynamic Random Access Memory (DRAM)
DRAM In this type, only one transistor needed to store data bit.
The information represented by small charge in the capacitor.
Duet the leakage, the charge of the capacitor would be lost.
The solution of this problem is to read the data before it lest and
write them again. This procedure called Refresh of Dynamic RAM

Control

Figure 5.10 DRAM

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5.5 RAM Memory (Cont’d.)
2. Dynamic Random Access Memory (DRAM)

❑ Dynamic RAM (DRAM) employ capacitors

❑ Capacitor stores electric charge whose level represents a 1 or 0
❑ Capacitors dissipate with time and hence the charge must be
restored frequently
❑ DRAMs
smaller, slower than SRAMs
support low cost, low power and high density and hence used in
main memory
❑ These days most DRAM is also synchronous SDRAM

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5.5 RAM Memory (Cont’d.)
2.1 Double Data Rate synchronous Dynamic Random Access
Memory (DDR SDRAM)

❑ It is also known as DDR1 SDRAM is a class of memory

integrated circuits used in computers. The interface uses double
pumping (transferring data on both the rising and falling edges
of the clock signal) to lower the clock frequency. One advantage
of keeping the clock frequency down is that it reduces the signal
integrity requirements on the circuit board connecting the
memory to the controller.

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5.5 RAM Memory (Cont’d.)
2.2 Double Data Rate synchronous Dynamic Random Access
Memory (DDR2SDRAM)
DDR2 memory is fundamentally similar to DDR SDRAM. Still, while DDR
SDRAM can transfer data across the bus two times per clock, DDR2
SDRAM can perform four transfers per clock. DDR2 uses the same
memory cells, but doubles the bandwidth by using the multiplexing
technique.
The DDR2 memory cell is still clocked at the same frequency as DDR
SDRAM and SDRAM cells, but the frequency of the input/output buffers is
higher with DDR2 SDRAM (as shown in Fig 10). The bus that connects the
memory cells with the buffers is twice wider compared to DDR. Thus, the
I/O buffers perform multiplexing: the data is coming in from the memory
cells along a wide bus and is going out of the buffers on a bus of the
same width as in DDR SDRAM, but of a twice bigger frequency. This
allows to increase the memory bandwidth without increasing the 29
operational frequency.
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5.5 RAM Memory (Cont’d.)

Figure 5.11 A four-word memory with four bits

per word in 2D organization
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 5.5 RAM Memory (Cont’d.)

RAM Grid

Figure 5.12 2-1/2D organization of a 64-word by one-bit RAM 31

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5.5 RAM Memory (Cont’d.)

RAM Grid
 During read operation:
 Entire row is selected
 It is fed into the column MUX
 MUX selects a single bit for output
 During write operation:
 Single bit to be written is distributed by the DEMUX to the
target column
 Row decoder selects the proper column to be written

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5.5 RAM Memory (Cont’d.)

Some examples of RAM Images

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 5.6 Memory Hierarchy

Increasing performance
and
increasing cost

Slow and
inexpensive

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 5.7 Interfacing I/O and peripheral devices
I/O devices
 For communication between microprocessor and outside world

 Keyboards, CRT displays, Printers, Compact Discs etc.

 Ports / Buffer IC’s

Microprocessor I/ O devices
(interface circuitry)

 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port controlled by
software

Interrupt driven I/ O
I/O device interrupts the processor and
initiate data transfer
Direct memory access
Data transfer is achieved by bypassing
the microprocessor
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5.8 8086 and 8088 comparison
Memory mapping I/O mapping
20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for I/O
devices

The I/O ports or peripherals can be treated like Only IN and OUT instructions can be used for
memory locations and so all instructions related data transfer between I/O device and processor
to memory can be used for data transmission
between I/O device and processor

Data can be moved from any register to ports Data transfer takes place only between
and vice versa accumulator and ports
When memory mapping is used for I/O devices, Full memory space can be used for addressing
full memory address space cannot be used for memory.
addressing memory.
 Suitable for systems which require large
 Useful only for small systems where memory memory capacity
requirement is less

For accessing the memory mapped devices, the For accessing the I/O mapped devices, the
processor executes memory read or write cycle. processor executes I/O read or write cycle.
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 M / M is asser ted high  M / M is asser ted low
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5.8 8086 and 8088 comparison
8086 8088

Similar EU and Instruction set ; dissimilar BIU

16-bit Data bus lines obtained by demultiplexing 8-bit Data bus lines obtained by demultiplexing
AD0 – AD15 AD0 – AD7

20-bit address bus 8-bit address bus

Two banks of memory each of 512 kb Single memory bank

6-bit instruction queue 4-bit instruction queue

Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz

In MIN mode, pin 28 is assigned the signal M / In MIN mode, pin 28 is assigned the signal IO /
I𝐎 𝐌

To access higher byte, 𝐁H𝐄 signal is used No such signal required, since the data width is
only 1-byte
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Appendix

Date Model F[MHz] Data Address Integration on Chip

1974 8080 3 8 16 5000

1978 8086 5 16 20 29000
1982 80186 6 16 20 More than 20000
1982 80286 10 16 24 134000
1985 80386 16 32 32 275000
1988 80486 50 32 32 1200000
1993 Pentium 66.7 64 32 3100000
1995 Pentium Pro 200 64 36 5500000
1997 Pentium II 450 64 46 7500000
1999 Pentium III 600 64 46 9500000
2000 Merced 1000 64 64 50000000
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End of Lecture 5
Tank You for Attention
Any Question?