University of Zakho

Faculty of Science
Department of CSc.

Microprocessors
Lecture # 1
8086 Microprocessor

Instructor – Omar M. Malallah

Contents

1.0 Objectives
1.1 Microprocessor
1.2 8086 Microprocessor
1.2.1 Pins and Signals
1.2.2 Architecture

End

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4.0 Objective of This Lecture

At the end of this lecture you will become familiar with:

 Microprocessor.
 8086 Microprocessor
 Architecture of 8086 Microprocessor
 Pins and Signals of 8086 Microprocessor
 Registers details

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1.1 Microprocessor

A microprocessor is a component that performs the instructions

and tasks involved in computer processing. In a computer system,
the microprocessor is the central unit that executes and manages
the logical instructions passed to it.

A microprocessor may also be called a processor or central

processing unit, but it is actually more advanced in terms of
architectural design and is built over a silicon microchip.

Figure 4.1 Microprocessor

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1.1 Microprocessor (Cont’d.)
Fifth Generation Pentium

Fourth Generation
During 1980s
Third Generation Low power version of HMOS technology
During 1978 (HCMOS)
HMOS technology  Faster speed, Higher 32 bit processors
packing density Physical memory space 224 bytes = 16 Mb
16 bit processors  40/ 48/ 64 pins Virtual memory space 240 bytes = 1 Tb
Easier to program Floating point hardware
Dynamically relatable programs Supports increased number of addressing
Processor has multiply/ divide arithmetic modes
hardware
More powerful interrupt handling Intel 80386
capabilities
Flexible I/O port addressing Second Generation
During 1973
Intel 8086 (16 bit processor) NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973
and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed 5
Intel 8085 (8 bit processor)
 1.1 Microprocessor (Cont’d.)
Various conditions of the
Computational Unit;
results are stored as Internal storage of data
performs arithmetic and
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU Generates the
address of the
Functional blocks instructions to be
Instruction fetched from the
Flag decoding unit
Register memory and send
through address
bus to the
memory
Timing and
control unit PC/ IP

Control Bus Address Bus Figure 4.2

Generates control signals for
Functional Blocks of
internal and external Decodes instructions; sends Microprocessor
operations of the information to the timing and
microprocessor control unit 6
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1.2 8086 Microprocessor

The Intel 8086

8086 Addressing Modes
Instruction Set
Instruction Format

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1.2 8086 Microprocessor (Cont’d.)
Common signals
1.2.1 Pins and Signals
AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
Figure 4.3 8086 Microprocessor Pins & Signal 8
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1.2 8086 Microprocessor (Cont’d.)
Common signals
1.2.1 Pins and Signals
BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most significant
half of data bus, D8-D15. 8-bit device connected to
upper half of the data bus use BHE (Active Low)
signal. It is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low. 9
Figure 4.3 8086 Microprocessor Pins & Signal
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1.2 8086 Microprocessor (Cont’d.)
Common signals
1.2.1 Pins and Signals
RESET (Input)

Causes the processor to immediately terminate its

present activity.
The signal must be active HIGH for at least four
clock cycles.

CLK
The clock input provides the basic timing for
processor operation and bus control activity. Its an
asymmetric square wave with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled during the

last clock cycles of each instruction to determine the
availability of the request. If any interrupt request is
pending, the processor enters the interrupt
acknowledge cycle.
This signal is active high and internally
Figure 4.3 8086 Microprocessor Pins & Signal synchronized. 10
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1.2 8086 Microprocessor (Cont’d.)
1.2.1 Pins and Signals Min/ Max Pins
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any co-
processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work in

multi-processor or co-processor configuration.

Minimum or maximum mode operations are

decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Figure 4.4 8086 Microprocessor
Min/Max Pins Maximum mode. 11
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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture

Figure 4.7 8086

Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have already BIU fetches instructions, reads data from
been fetched by the BIU. memory and I/O por ts, writes data to
BIU and EU functions separately. memory and I/ O por ts. 12
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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)

Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Figure 4.7 8086

Microprocessor
Architecture

Segment Registers >> 13

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly address Programs obtain access to code
memory is divided into four segments (256 K bytes and data in the segments by
segments of up to 64K within the 1 M byte of memory) changing the segment register
bytes each. at a particular time. content to point to the desired
segments.
Figure 4.8 8086 Microprocessor Segment Registers 14
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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)
Segment Code Segment Register
Registers
16-bit
CS contains the base or star t of the current code segment; IP
contains the distance or offset from this address to the next
instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting
the contents of CS 4-bits to the left and then adding the 16-bit
contents of IP.
That is, all instructions of a program are relative to the
contents of the CS register multiplied by 16 and then offset is
added provided by the IP.

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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)
Segment Data Segment Register
Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)
Segment Stack Segment Register
Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the
Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address
is calculated from the Stack segment (SS) and the Base
Pointer (BP).

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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)
Segment Extra Segment Register
Registers

16-bit

Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-bit

physical address for the destination.

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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)
Segment Instruction Pointer
Registers
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing to
the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution of
the next instruction takes place.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-Out
(FIFO) in which up to 6 bytes
of instruction code are pre
fetched from the memory
ahead of time.

This is done in order to speed

up the execution by
overlapping instruction fetch
with execution.

This mechanism is known as

pipelining.

Figure 4.8 8086 Microprocessor Instruction Queue 20

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 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.
Four general purpose
registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and

Index registers (Source

Index, Destination Index)
each of 16-bits Some of the 16 bit registers can be
used as two 8 bit registers as :
16-bit ALU for
performing arithmetic AX can be used as AH and AL
and logic operation BX can be used as BH and BL
CX can be used as CH and CL
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DX can be used as DH and DL
1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word, and
AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O por t.
Multiplication and Division instructions also use the AX or
AL.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and
BH contains the high-order byte.
This is the only general purpose register whose contents can
be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements CX

by 1 without affecting flags and will check if [CX] = 0.

If it is zero, 8086 executes the next instruction; otherwise

the 8086 branches to the label START.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a 32
÷ 16 division and the 16-bit reminder after division.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during execution

of instructions that involve the stack segment in the external
memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.

BP contains an offset address in the current SS, which is used

by instructions utilizing the based addressing mode.

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1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Execution Unit (EU)
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 1.2 8086 Microprocessor (Cont’d.)
Auxiliary Carry Flag
1.2.2 Architecture Carry Flag
This is set, if there is a carry from the lowest
Flag Register nibble, i.e, bit three during addition, or borrow This flag is set, when there is a carry
for the lowest nibble, i.e, bit three, during out of MSB in case of addition or a
Execution Unit (EU) subtraction. borrow in case of subtraction.

Sign Flag
Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of the This flag is set to 1, if the lower byte of
result of any computation computation or comparison performed the result contains even number of 1’s
is negative by an instruction is zero ; for odd number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor enters the
This flag is set, if an overflow occurs, i.e, if the single step execution mode by
result of a signed operation is large enough to generating internal interrupts after the
accommodate in a destination register. The result Direction Flag execution of each instruction
is of more than 7-bits in size in case of 8-bit
This is used by string manipulation instructions.
signed operation and more than 15-bits in size in If this flag bit is ‘0’, the string is processed
case of 16-bit sign operations, then the overflow Interrupt Flag
beginning from the lowest address to the
will be set. highest address, i.e., auto incrementing mode.
Causes the 8086 to recognize external
Otherwise, the string is processed from the 37
mask interrupts; clearing IF disables
highest address towards the lowest address, these interrupts.
Falah Hasan Mohammed i.e., auto incrementing mode. 37 Computer Science Dept.
 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

16 bit AX, BX, CX, DX

1 General purpose register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

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6 HasanFlag
Falah (PSW)
Mohammed 16 bit Flag register Computer Science Dept.
 1.2 8086 Microprocessor (Cont’d.)
1.2.2 Architecture Registers and Special Functions
Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

8-bit Accumulator
AL Stores the 8-bit results of arithmetic and logic operations

Used to hold base value in base addressing mode to access

BX Base register
memory data
Used to hold the count value in SHIFT, ROTATE and LOOP
CX Count Register
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

Used to hold the base value in base addressing using SS register to

BP Base Pointer
access data from stack memory
Used to hold index value of source operand (data) for string
SI Source Index
instructions
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Used to hold the index value of destination operand (data) for
DIHasan Mohammed
Falah Data Index Computer Science Dept.
string operations
Next Lecture

 Continuous with 8086 Microprocessor

Architecture and Addressing Modes

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