iot fpga
iot fpga
Abstract—The concept of open-source has permeated various which often require an investment in materials, while open
domains, revolutionizing the way we collaborate, create and share software projects implicate workforce costs and investment. It
knowledge. While open-source software has long been celebrated
for its transformation impact, a new frontier has emerged open should be noted that the software could cost less expenses and
source hardware platforms. These remarkable innovations are charges. Contrary to open software, this is not feasible for most
empowering individuals, communities, and organizations to push open hardware manufacturers. Indeed, a supplier is unable to
the boundaries of hardware development, unlocking a world provide physical components at a competitive price while the
of possibilities. The use of open-source hardware platforms has manufacturing costs are very high. Moreover, the documenta-
increased in the IoT domain due to their flexibility, affordability,
and openness. These platforms offer an array of advantages tion and source files of its product are another source to offset
over proprietary solutions, including the ability to customize and or cover the budget of the production chain. The distinction
modify hardware and software, and the possibility of economies between software and hardware is fairly obvious. Computers
and innovation. In this article, we explore what different open- are ubiquitous, with the same basic general-purpose machine
source hardware platforms are available for IoT. We examine used all around the world. Open-source software downloading
the profits, and limitations of each platform and we discuss their
potential use cases in IoT applications. We also inspect the role is very available and its using is very simple on a local machine
of open-source communities in developing and maintaining these within minutes. The computer on which the software works
platforms, highlighting the collaborative and inclusive nature of has been built, and the components of the software are already
open-source development. We’ll also go through some of the in place and properly organized. However, the situation is
difficulties and things to keep in mind while adopting open-source different as far as equipment is concerned. While you can
hardware platforms for Internet of Things applications. Overall,
this article shows how open-source hardware platforms have the download the design files for a component, you still have
power to transform the IoT space by fostering better creativity, the challenge of covering the cost of supplying raw materials,
teamwork, and accessibility for both consumers and developers. assembling, and various related expenses. The scientific com-
Index Terms—IoT, Architecture, Open Hardware, FPGA munity is moving toward creating publicly accessible tools as
a result of these factors. Much work is being done to develop
I. I NTRODUCTION electronic circuit design tools. In this context, it is important to
Open-source hardware refers to physical devices whose mention the studies evaluating different platforms automating
designs and specifications are publicly accessible, allowing the modeling, prototyping, and verification process of chips
anyone to study, modify, and distribute them freely. This inclu- [1]. Now object-oriented computer languages such as Python
sive approach democratizes technology, enabling individuals facilitate the work of hardware engineers and provide libraries
with diverse skill sets and resources to participate in the hard- open to the public [2]. LiteX presents different functionalities,
ware revolution. From microcontrollers to 3D printers, open- which make it a powerful tool, and in the future, it could en-
source hardware platforms have gained significant traction, sure design validation before physical implementation. Open-
sparking a paradigm shift in how we conceive, build, and source hardware mainly consists of a design for a physical
iterate upon physical systems. Open hardware projects typi- object which can be modified or even reorganized in order
cally involve the production or prototyping of physical objects, to be adapted to several domains and especially IoT. The
B. GAP8:
Flamand and Al [7] present an open-source platform GAP8,
which is used to reduce the quantity of data transmitted
to another device such as the cloud. The author of this
article proposes a solution which is a RISC V multiprocessor
delivered by PULP. The SoC GAP8 contains a cluster, it has
eight cores, each core can access the L1 memory. This also
allows us to activate parallel data processing (open MP model).
The SoC contains a DMA block (Direct Memory Access)
Fig. 1. The IoT Architecture [5]. which reduces the access time. In his research, the author has
developed a tool making it possible to automate the location
The Internet of Things (IoT) is a structure that connects of data that should be as close as possible to the cores [7].
billions of physical objects and sensors, creating vast amounts As shown in the diagram (figure 2), GAB 8 has several I/O
of data that require storage. However, IoT faces challenges interfaces which allows a better adaptation for open-source
related to privacy and security [5]. To address these issues, a hardware projects within the framework of IoT. This solution
proposed architecture for IoT should consider scalability, inter- will make it possible to process the data and send a summary
operability, reliability, quality of service, and other factors. The of the data process. Our research on the platform GAB 8 has
basic architecture of IoT consists of five layers, as illustrated led us to a conclusion, depending on the performance of The
in Figure 1: Perception, Network, Middleware, Application, SoC GAP8, the solution will be very useful for applications
and Business. that use a lot of data processing.
• The Perception layer deals with the identification and
collection of object-specific information, which is trans- C. AI IOT application:
mitted securely to the Middleware layer via the Network Torres [8] proposes a solution for the development of appli-
layer. cations related to artificial intelligence and IoT. In this context,
• The Middleware layer is responsible for processing in- two applications are developed, the first one recognition of
formation, and making decisions based on the results. movements and the second one detection of masks. These
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Cycle-accurate simulators like Modelsim proceed with an
accurate cycle-by-cycle approach using hardware description
language HDL such as system Verilog. Instruction-level sim-
ulators like TimingSimple and O3CPU of gem5 [14] are
imitating the target system instruction by instruction. Event-
driven simulators like SystemC, RISCV TLM, GVSoC, and
systemC+TLM do not directly consider cycles but the more
abstract concept of events, which are changes of state in
the system occurring at a specific instant in time [15]. To
accommodate a wide range of use cases, Internet of Things
(IoT) devices must be programmable and increasingly resem-
ble complete systems-on-node, equipped with sensors, mi-
croprocessors, specialized hardware, memories, and wireless
transceivers that can operate independently for multiple years
[16].
Two processor cores, Zero-riscy and Micro-riscy, have been
Fig. 2. GAP-8 architecture block diagram [7]. designed with specific optimizations for IoT applications [16].
Zero-riscy is more than two times smaller than Riscy, uses 2
times less energy, and has only 1.3 times longer execution time
solutions are based on an SoC (Kendryte K210) built according in Coremark benchmarks [17]. Micro-riscy is even smaller and
to the RISC V instruction set architecture. The card used to consumes 3.5 times less energy than Riscy when executing
make these applications is a Sipeed MAIX GO. The author control-oriented code. Micro-riscy is dedicated to functioning
points out the effect that he did not manage to connect in an always-on voltage domain, interacting with peripherals
the JTAG debugger with the IO platform universal debugger and controlling larger accelerators to offload tasks and im-
because the debugging on board was not fully active, as the plement power-management policies. In contrast, Zero-riscy
firmware was not finished yet [8]. The article describes certain is optimized to have higher computation performance than
limits of the IO platform (J-link could not connect to the Micro-riscy while maintaining a small area and low power
SoC). Besides, our research concludes that the development consumption. Experimental tests of the processor cores show
with the Sipeed MAIX Go card cannot apply in the field of that Riscy, with its advanced ISA and more complex pipeline,
education [9] because they have bugs and the firmware is not is the fastest core in all kernels, whereas Micro-riscy is the
yet developed correctly. Given the limits that apply when using slowest. When running DSP applications, Riscy is 6.1 times
platformeIO and VisualGDB, the author has developed his two faster than Zero-riscy and 53.4 times faster than Micro-riscy.
applications using the MicroPython port and the maixpy IDE
E. OpenPiton
provided by Sipeed.
In the same context, Rui Jia [10] conducted a study on proces- Jonathan Balkind collaborates with many other authors to
sors open-source hardware. The author gives us the results of describe the OpenPiton platform [18]. It is an open-source
a very thorough analysis of 178 open-source processors. The multicore processor designed for scalability and portability,
study is based on the stability properties and the completeness suitable for IoT applications. This platforme aims to facilitate
of all the processors, the detail of this study is not mentioned its use by other researchers, offering a high degree of inte-
in the final analysis. The author downsized the number of gration and configurability. It is configurable and extensible,
processors to seven, with due consideration to factors such making it easy to add research features and support research
as the license, ISA (Instruction Set Architecture), and design on operating systems, security, compilers, execution tools,
characteristics such as ”synchronous or asynchronous” and systems, and CAD tool design. It is a versatile platform for
”single or multi-core. research in many fields, especially the IoT domain. The main
contributions of OpenPiton include the creation and release
D. GVSoC simulator of the world’s first open-source, versatile, and multithreaded
Bruschi [11] discusses the GVSoC simulator, which is an multicore processor [19].
open-source hardware and high-speed simulator used to sim-
F. Cuidats
ulate RISC V systems that are intended for IoT applications.
The GVSoC simulator is classified as a functional or timing Toni Adame [20] introduces a novel IoT monitoring system
simulator. The simulators can only simulate the instruction set that combines RFID and WSN technologies to monitor the
architecture (ISA) but not the pipeline. For example, SPIKER, position of medical equipment (with passive and active RFID
SimpleCPU of gem 5, and RISC-QEMU [12] are function tags) and the well-being of patients (with an active wristband
simulators [13]. Timing simulators, on the other hand, model that tracks skin temperature, heart rate, and motion). The
the micro-architecture of the target and require a distinction article evaluates the current state of real-time locating systems
between cycle-accurate, instruction level, and event-driven. and integrates suitable technologies into the proposed system.
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The system, which includes end nodes and backend servers, Graph a
is both theoretically presented and practically implemented.
The article concludes with feedback and evaluation from tests
conducted in a genuine hospital setting, both qualitatively
and quantitatively. In Figure 3, various embedded cores are
compared based on their performance, power consumption,
and energy efficiency [21]. The data shows that the Cortex-
M3 outperforms the Cortex-M0+ by 1.36 times (graph a).
However, it also consumes 2.89 times more power (graph b),
which results in 113% more energy dissipation to execute the
CoreMark benchmark once (graph c). The energy efficiency
of Cortex-M4 and Cortex-M7 is even worse, as they use 138%
and 656% more energy for the same task compared to Cortex-
Graph b
M0+. The Pulp cores, including Riscy and Zero-riscy, are also
evaluated in Figure 3. Although Riscy performs better, Zero-
riscy consumes less energy for a task due to its simpler micro-
architecture [22].
To reduce power consumption, scaling down the supply
voltage is a commonly used method. Some processors de-
signed aim to work at low voltage or even near-threshold or
sub-threshold voltage. However, voltage scaling has slowed
down in recent years due to rising leakage currents, making ar-
chitecture optimization necessary to improve energy efficiency
further.
G. Fulmine Graph c
A System-on-Chip called Fulmine was introduced as a
solution for smart secure near-sensor data analytic in IoT [23].
Unlike aggressive technology or voltage scaling approaches,
we employed an architectural solution that involves combining
cores and accelerators into a single tightly coupled cluster.
The proposed use cases demonstrate that this method yields
a tenfold improvement in time and energy when compared
to a purely software-based approach, without compromising
on flexibility. The Fulmine SoC facilitates secure, integrated,
and low-power data analytic within the IoT node, while still
maintaining high levels of security.
H. RISC-V for near-threshold NT operation Fig. 3. The performance, power consumption, and energy efficiency of
different embedded cores [21]
Michael Gautschi introduce an extended processor core
architecture based on RISC-V, which is fully compatible with
modern cores and can be utilized in IoT applications [24]. The
core has been specifically designed for a multi-core PULP
system [25]. Furthermore, it includes ISA extensions that
enhance computational density [26]. Its instructions are robust
and can result in considerable energy savings. According
to benchmarks, the core is 37% faster on general-purpose
applications, and vector extensions can yield an additional
gain of up to 2.3x. With the vector and fixed-point extensions,
processing convolutions on the proposed core can lead to an
average speedup of 3.9x. The newly added ISA extensions
significantly reduce shared memory contentions, allowing a
four-core implementation to outperform a single-core imple-
mentation by 3.9x, while consuming only 2.4x more power.
Additionally, the processor core is scalable and achieves high
energy efficiency gains when processing near-threshold at
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farming, business, and emergent solution for healthcare. Open-
source electronic components represent a very important role
in the transfer and universalization of technology, especially
as they are used in the academic process [29]. The IOT
came to promote interaction in the world, by leveraging new
technologies and advances in communications networks (5G
and 6th generation). In parallel, the hardware and electronic
device are supposed to satisfy and follow this evolution while
guaranteeing the balance between cost and innovation.
TABLE I. Different open source cores comparison [28]. Following our study on the different open source hardware
platforms that we have detailed in the previous part. We can
deduce that each platform has its own specialty, from a global
0.46V, making it suitable for a wide range of IoT applications point of view all the platforms discussed lean on IOT but
[24]. following our research on the technical aspects that we have
discussed we can categorize its platform according to the
IV. D ISCUSSION
field of application. For example, for applications that require
There are many works, discussing open-source hardware significant real-time data processing, the GAP8 platform
on different sides. We have some research evaluating and seems the most suitable for this type of application given the
comparing different types of open-source hardware, according performance of the GAP8 SoC. However, for applications
to their specific focus and unique contributions. For example, that require a connection between devices and sending with
M.Makni [27] compares FPGA soft-core processors for em- reception of data, the BKThings and Cuidats platforms seem
bedded multi-core systems. He studies open-source processors more suitable for this type of application. For a research
and commercial processors intending to create a multi-core and development and simulation aspect, the OpenPiton and
system used in IoT applications. The author concluded that the GVSoC platforms will be the most suitable.
clock frequency that processor cores can achieve on FPGAs
is usually directly proportional to the number of pipeline In summary, open-source hardware FPGA platforms present
stages. Additionally, commercial software cores were found exciting paradigms and opportunities for IoT development.
to outperform open-source cores due to their optimization of Here are some guidelines and recommendations for the use
the targeted technology. It should be noted that the author did of open-source hardware FPGA platforms in IoT applica-
not consider RISC-V cores. On the other hand, Roland Höller tions: 1. Understand the Application Requirements: Before
focuses specifically on open-source RISC-V processor IP cores selecting or designing an open-source hardware FPGA plat-
for FPGAs and evaluates them based on their performance, form, thoroughly analyzing the IoT application requirements.
area utilization, and power consumption. Table 1 presents Identifying the specific hardware functionalities, interfaces,
a comparison between different open-source cores has been and performance metrics that are critical to the application’s
illustrated [28]. success. 2. Evaluate Available Open-Source Platforms: Ex-
Roland Höller finds that commercial open-source processor ploring the existing open-source FPGA platforms suitable
are more performant than open-source cores. In his study, he for IoT applications. Considering factors such as community
compares three different designs based on resource usage and support, documentation, hardware compatibility, and available
clock frequency, as well as other parameters mentioned in the tools. Evaluate the platforms based on their features, flex-
previous table [28]. These three processors are widely used in ibility, and ease of use. 3. Leverage Existing Open-Source
IoT applications, and their comparison is necessary to justify Designs: Taking advantage of the wealth of existing open-
their performance. Similarly, Bruschi presents a full-platform source FPGA designs, libraries, and toolchains available in the
simulator for RISC-V-based IoT processors that simulates community. These resources can significantly accelerate the
the entire system [11]. However, another study focuses on development process and provide valuable insights into best
comparing ultra-low-power RISC-V cores for IoT applications practices for IoT hardware design. 4. Prioritize Verification
based on their performance, power consumption, and area and Testing: Thoroughly validate and verify the FPGA designs
utilization [16], while J.Balkind introduces an open-source to ensure correctness and robustness. Use simulation tools,
framework designed to provide a flexible and scalable platform testbenches, and hardware debugging techniques to detect and
for manycore research [18]. Indeed, each one provides his resolve issues early in the development process. Verification
owner overview to evaluate open-source hardware, but we is critical to ensure reliable and secure operation of the
might find a meeting point between all studies cited. They IoT devices. 5. Consider Security Best Practices: Security is
demonstrate the capability of open-source hardware to respond paramount in IoT applications. Implement security measures
to different requirements. The development of these applica- such as secure boot, authentication, encryption, and access
tions arise the confidence that ensures open-source hardware control in the FPGA designs. Regularly update the open-source
for expected improvement in the future. Especially, when we hardware platforms with the latest security patches and stay
talk about Industry 5.0, smart cities, connected vehicles, smart informed about potential vulnerabilities in the ecosystem. 6.
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