MODULE – II

Addressing modes –Instruction Set –Timing Diagrams. Evolution of Microprocessors –

16-bit and 32-bit microprocessors. Intel 8085 Interrupts and DMA: 8085 Interrupts –
Software and Hardware Interrupts –8259 Programmable Interrupt Controller
ADDRESSING MODES IN 8085:
The 8085 microprocessor has several addressing modes that are used to access
memory locations. Some of the most commonly used addressing modes in the 8085
microprocessor are: The way of specifying data to be operated by an instruction is called
addressing mode.
These are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory without any
alteration in the content.
Here are some reasons why addressing modes are used in the 8085 microprocessor:
 Flexibility: Addressing modes provide a flexible way to access data and instructions
in memory. Different addressing modes allow programmers to choose the most
appropriate addressing technique for a particular task, depending on the type of data
being accessed, the size of the data, and other factors.
 Memory optimization: Addressing modes can help to optimize the use of memory
resources by allowing data and instructions to be accessed in the most efficient way
possible. For example, using indirect addressing modes can reduce the amount of
memory needed to store addresses, while using indexed addressing modes can reduce
the number of memory accesses needed to access a large array of data.
 Performance optimization: Addressing modes can also help to optimize the
performance of the microprocessor by reducing the number of memory accesses
needed to fetch data or instructions. This can help to speed up the execution of
programs and improve the overall efficiency of the microprocessor.
 Reduced code size: Addressing modes can help to reduce the size of code needed to
perform a particular task. By using addressing modes that allow data and instructions
to be accessed using fewer instructions, programmers can write more compact and
efficient code.

Addressing modes in 8085 is classified into 5 groups –

Immediate addressing mode:
In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand.
In immediate addressing mode the source operand is always data. If the data is 8-bit,
then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes.
For example: MVI K, 20F: means 20F is copied into register K.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Register addressing mode:
In register addressing mode, the data to be operated is available inside the register(s)
and register(s) is(are) operands. Therefore the operation is performed within various registers
of the microprocessor.
In this mode, the data is copied from one register to another.
For example: MOV K, B: means data in register B is copied to register K.
Direct addressing mode:
In direct addressing mode, the data to be operated is available inside a memory
location and that memory location is directly specified as an operand. The operand is directly
available in the instruction itself.
In this mode, the data is directly copied from the given address to the register.
For example: LDB 5000K: means the data at address 5000K is copied to register B.
Indirect addressing mode
In register indirect addressing mode, the data to be operated is available inside a
memory location and that memory location is indirectly specified by a register pair.
In this mode, the data is transferred from one register to another by using the address
pointed by the register.
For example: MOV K, B: means data is transferred from the memory address pointed by the
register to the register K.
Implied addressing mode
In implied/implicit addressing mode the operand is hidden and the data to be operated
is available in the instruction itself.
This mode doesn’t require any operand; the data is specified by the opcode itself.
For example: CMP.

INSTRUCTION SET
The various techniques to specify data for instructions are:
1. 8-bit or 16-bit data may be directly given in the instruction itself.
2. The address of the memory location, I/O port or I/O device, where data resides, may
be given in the instruction itself.
3. In some instructions, only one register is specified. The content of the specified
register is one of the operands.
4. Some instructions specify two registers. The contents of the registers are the required
data.
5. In some instructions, data is implied. The most instructions of this type operate on the
content of the accumulator.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Due to different ways of specifying data for instructions, the machine codes of all instructions
are not of the same length. It may 1-byte, 2-byte or 3-byte instruction.

Instruction sets are instruction codes to perform some task. It is classified into five categories.

S.No. Instruction & Description

Control Instructions:
1 Includes the instructions related to interrupts and the instruction used to halt
program execution

Logical Instructions
The instructions which performs the logical operations like AND, OR,
EXCLUSIVE-OR, complement, compare and rotate instructions are grouped under this
heading. The flag conditions are altered after execution of an instruction in this group.
2
AND, ORA, XOR: Perform bitwise logical operations on the accumulator with
data from registers, memory, or immediate values.
CMP: Compare the accumulator with data from registers, memory, or
immediate values.

Branching Instructions
The instructions that are used to transfer the program control from one memory
location to another memory location are grouped under this heading.
JMP: Unconditional jump to a specific memory address.
3
JC, JNC, JP, JM, JZ, JNZ: Conditional jumps based on the status of the carry
flag (C), parity flag (P), sign flag (M), zero flag (Z), etc.
CALL: Call a subroutine at a specific memory address.
RET: Return from a subroutine.

Arithmetic Instructions
Includes the instructions, which performs the addition, subtraction, increment or
decrement operations. The flag conditions are altered after execution of an instruction
in this group.
4 ADD, ADC: Add data to the accumulator with or without carry.
SUB, SBB: Subtract data from the accumulator with or without borrow.
INR, DCR: Increment or decrement the value of a register or memory location.
DAD: Double the value of a register pair.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 Data Transfer Instructions
Includes the instructions that moves (copies) data between registers or between
memory locations and registers. In all data transfer operations, the content of source
register is not altered. Hence the data transfer is copying operation.
These instructions move data between registers, or between memory and
registers.
These instructions copy data from source to destination. While copying, the
contents of source are not modified.
Opcode Operand Description
5
MOV Rd, Rs M, Rs Rd, M Copy from source to destination
MVI Rd, Data M Data Move immediate 8-bit
LDA 16-bit address Load Accumulator
LDAX B/D Register Pair Load accumulator indirect
LXI Reg. pair, 16-bit data Load register pair immediate
STA 16-bit address Store accumulator direct
STAX Reg. pair Store accumulator indirect
XCHG None Exchange H-L with D-E

Let us take a look at the programming of 8085 Microprocessor.

Instruction sets are instruction codes to perform some task. It is classified into five
categories.
8085 – Demo Programs
Now, let us take a look at some program demonstrations using the above instructions
Adding Two 8-bit Numbers
Write a program to add data at 3005H & 3006H memory location and store the result
at 3007H memory location.
Problem demo –
(3005H) = 14H
(3006H) = 89H
Result − 14H + 89H = 9DH
The program code can be written like this –
LXI H 3005H : "HL points 3005H"
MOV A, M : "Getting first operand"
INX H : "HL points 3006H"
ADD M : "Add second operand"
INX H : "HL points 3007H"

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 MOV M, A : "Store result at 3007H"
HLT : "Exit program"

Exchanging the Memory Locations

Write a program to exchange the data at 5000M & 6000M memory location.
LDA 5000M : "Getting the contents at5000M location into accumulator"
MOV B, A : "Save the contents into B register"
LDA 6000M : "Getting the contents at 6000M location into accumulator"
STA 5000M : "Store the contents of accumulator at address 5000M"
MOV A, B : "Get the saved contents back into A register"
STA 6000M : "Store the contents of accumulator at address 6000M"

TIMING DIAGRAMS:
A time diagram is a graphical representation. The 8085 instruction timing diagram
represents the execution time of each instruction in graphical format.
Execution time is given in T-states. The 8085 microprocessor has a set of control signals
and data signals that play an important role in the execution of instructions.
A timing diagram is and how to draw a timing diagram of different instructions
 Clock Signal: The time required to execute an instruction is called a clock cycle.
 Machine Cycle: The time required to access memory or input/output devices is called
a machine cycle. The 8085 has 5 basic machine cycles i.e., load opcode, read from
memory, write to memory, read I/O, and write I/O.
 T-State: A machine cycle and an instruction cycle take several clock periods. The
portion of an operation performed in one system clock period is called a T-state.
 Control Signals: The control signal controls the operations. Common signals are
ALE (address block enable), RD (read), WR (write), and IO/M (input/output)
memory.
Machine Cycle of 8085
The 8085 microprocessor has 5 basic machine cycles. They are :
 Opcode Fetch {4T- state}
 Memory Read {3T- state}
 Memory Write {3T- state}
 I/O Read {3T- state}
 I/O Write {3T- state}

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Opcode Fetch Machine Cycle of 8085
 Each processor instruction has a one byte opcode.
 Operation codes are stored in memory. Thus, the processor performs an opcode load
machine cycle to load the opcode from memory.
 Thus, each instruction begins with a machine cycle of opcodes.
 The time the processor takes to perform an opcode load cycle is 4T.
 At this time, the first, 3T-states are used to load the opcode from memory, and the
remaining T-states are used for internal opcodes.

Memory Read Machine Cycle of 8085

 A memory read machine cycle is executed by the processor to read a data byte from
memory.
 The processor takes 3T states to perform this cycle.
 Instructions that have more than one byte word will use machine cycle after machine
cycle to load the opcode.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Memory Write Machine Cycle of 8085
 A write-to-memory machine cycle is executed by the processor to write a data byte to
memory.
 The processor takes 3T states to perform this cycle.
 Instructions that have more than one byte word will use machine cycle after machine
cycle to load the opcode.

I/O Read Machine Cycle

 A reader I/O cycle is performed by the processor to read a data byte from an I/O port
or peripheral that is I/O mapped in the system.
 The processor needs 3T states to execute this machine cycle.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
I/O Write Machine Cycle
 A writer’s I/O cycle is executed by the processor to write a data byte to an I/O port or
peripheral that is I/O mapped in the system.
 The processor needs 3T states to execute this machine cycle.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Evolution of Microprocessors – 16-bit and 32-bit microprocessors
Size of the microprocessor – 16 bit

Number of Inst. per

Name Year of Invention Clock speed transistors sec

1978 (multiply and divide 4.77 MHz,

2.5
8086 instruction, 16-bit data bus and 20- 8 MHz, 10 29000
Million
bit address bus) MHz

1979 (cheaper version of 8086 and 2.5

8088
8-bit external bus) Million

1982 (80188 cheaper version of

80186, and additional components
80186/80188 like interrupt controller, clock 6 MHz
generator, local bus controller,
counters)

1982 (data bus 16bit and address 4

80286 8 MHz 134000
bus 24 bit) Million

Size of the microprocessor – 32 bit

Number of
Name Year of Invention Clock speed transistors Inst. per sec

1986 (other versions

INTEL 80386DX, 80386SX, 16 MHz –
275000
80386 80386SL , and data bus 32- 33 MHz
bit address bus 32 bit)

1986 (other versions 8 KB of

INTEL 16 MHz – 1.2 Million
80486DX, 80486SX, cache
80486 100 MHz transistors
80486DX2, 80486DX4) memory

Cache
memory 8 bit
PENTIUM 1993 66 MHz for
instructions 8
bit for data

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Size of the microprocessor – 64 bit

Number of
Name Year of Invention Clock speed transistors Inst. per sec

64 KB of L1
2006 (other versions
INTEL 291 Million cache per core
core2 duo, core2 1.2 GHz to 3 GHz
core 2 transistors 4 MB of L2
quad, core2 extreme)
cache

2.2GHz – 3.3GHz,
2.4GHz – 3.6GHz,
i3, i5, i7 2007, 2009, 2010
2.93GHz –
3.33GHz

16 –bit Microprocessor:
16-bit stack processors in general have lower costs than 32-bit processors. Their
internal data paths are narrower, so they use fewer transistors and cost less to manufacture.
They only need 16-bit paths to external memory, so they have half as many memory bus data
pins as 32-bit processors.
System costs are also lower, since a minimum configuration 16-bit processor only
needs to have half the number of memory chips as a 32-bit processor for a single bank of
memory.
16-bit chips also have a reasonable amount of silicon area available for special
features, such as hardware multipliers, on-chip program memory, and peripheral interfaces.
The trend is for semicustom 16-bit stack processors such as the RTX 2000 to be complete
systems-on-a-chip, including I/O peripherals and program memory for embedded
applications.

32-bit Microprocessor:
32-Bit stack processors should be used instead of 16-bit processors only in cases
where the application requires high efficiency at one or more of the following: 32-bit integer
calculations, access to large amounts of memory, or floating point arithmetic.
32-Bit integer calculations are obviously well suited to a 32-bit processor. Occasions
where 32-bit integers are required include graphics and manipulation of large data structures.
While a 16-bit processor can simulate 32-bit arithmetic using double-precision operands, 32-
bit processors are much more efficient.
Floating point calculations also require a 32-bit processor for good efficiency. 16-Bit
processors spend a significant amount of time manipulating stack elements when dealing with
floating point numbers, whereas 32-bit processors are naturally suited to the size of the data
elements. There are many instances in which scaled integer arithmetic is more appropriate
than floating point numbers to increase speed on some processors

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Intel 8085 Interrupts and DMA:
Interrupts in 8085:
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e.
A small program or a routine that when executed, services the corresponding interrupting
source is called an ISR.
 TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an
external device, such as a power failure or a hardware malfunction
 RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the second highest priority.
 RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the third highest priority.
 RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the fourth highest priority.
 INTR: The INTR interrupt is a maskable interrupt that is generated by an external
device, such as a keyboard or a mouse. It has the lowest priority and can be disabled.
Priority of Interrupts – When microprocessor receives multiple interrupt requests
simultaneously, it will execute the interrupt service request (ISR) according to the priority of
the interrupts.

When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is transferred to a
sub-routine by generating CALL signal and after executing sub-routine by
generating RET signal again program control is transferred to main program from where it
had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement (INTA)
to the peripheral which is requesting for its service. Interrupts can be classified into various
categories based on different parameters:
Interrupt are classified into following groups based on their parameter −
1. Vector interrupt – Vectored Interrupts are those which have fixed vector address
(starting address of sub-routine) and after executing these, program control is transferred
to that address
In this type of interrupt, the interrupt address is known to the processor.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 For example: RST7.5, RST6.5, RST5.5, TRAP.
2. Non-Vector interrupt – Non-Vectored Interrupts are those in which vector address is
not predefined. The interrupting device gives the address of sub-routine for these
interrupts.
In this type of interrupt, the interrupt address is not known to the processor so, the
interrupt address needs to be sent externally by the device to perform interrupts.
For example: INTR.
3. Maskable interrupt – Maskable Interrupts are those which can be disabled or ignored
by the microprocessor. These interrupts are either edge-triggered or level-triggered, so
they can be disabled
In this type of interrupt, we can disable the interrupt by writing some instructions into
the program. For example: RST7.5, RST6.5, RST5.5.
4. Non-Maskable interrupt – Non-Maskable Interrupts are those which cannot be disabled
or ignored by microprocessor
In this type of interrupt, we cannot disable the interrupt by writing some instructions
into the program. For example: TRAP.
5. Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt.
Software Interrupts are those which are inserted in between the program which means
these are mnemonics of microprocessor.
There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5,
RST6, and RST7.
6. Hardware interrupt − When microprocessors receive interrupt signals through pins
(hardware) of microprocessor, they are known as Hardware Interrupts.
There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5,
RST6.5, RST5.5, INTA.

Instruction for Interrupts –

1. Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are
enabled following the execution of next instruction followed by EI. No flags are
affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to enable the interrupts again (except TRAP).
2. Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop
hence disabling all the interrupts. No flags are affected by this instruction.
3. Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST
7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data
via the Serial Output Data (SOD) line. First the required value is loaded in
accumulator then SIM will take the bit pattern from it.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 4. Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte
which defines the condition of the mask bits for the interrupts. It also reads the
condition of SID (Serial Input Data) bit on the microprocessor.

Direct Memory Access (DMA):

DMA basically stands for Direct Memory Access. It is a process which enables data
transfer between the Memory and the IO (Input/ Output) device without the need of or you
can say without the involvement of CPU during data transfer.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 Working of DMA:
Following list of points will describe briefly about DMA and its working as follows.
 For DMA, you basically need a hardware called DMAC (Direct Memory Access
Controller) which will help in the throughout process of data transfer between the
Memory and IO device directly.
 First what happens is IO device sends the DMA request to DMA Controller, then
further DMAC device sends HOLD signal to CPU by which it asks CPU for several
information which are needed while transferring data.
 CPU then shares two basic information with DMAC before the Data transfer which
are: Starting address (memory address starting from where data transfer should be
performed) and Data Count (no of bytes or words to be transferred).
 CPU then sends HLDACK (Hold Acknowledgement) back to DMAC illustrating that
now DMAC can successfully pass on the information.
 Then further DMAC shares the DMA ACK (DMA Acknowledgement) to the IO
device which would eventually let IO device to access or transfer the data from
memory in a direct and efficient manner.
Modes of DMA Transfer:
Now after getting some brief idea about DMA and its working it’s the time to analyze
Modes of DMA Transfer.
 During the DMA Transfer CPU can perform only those operation in which it doesn’t
require the access of System Bus which means mostly CPU will be in blocked state.
 For how much time CPU remains in the blocked state or we can say for how much
time CPU will give the control of DMAC of system buses will actually depend upon
the following modes of DMA Transfer and after that CPU will take back control of
system buses from DMAC.
Mode-1: Burst Mode –
 In this mode Burst of data (entire data or burst of block containing data) is transferred
before CPU takes control of the buses back from DMAC.
 This is the quickest mode of DMA Transfer since at once a huge amount of data is
being transferred.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
  Since at once only the huge amount of data is being transferred so time will be saved
in huge amount.
Mode-2: Cycle Stealing Mode –
 Slow IO device will take some time to prepare data (or word) and within that time
CPU keeps the control of the buses.
 Once the data or the word is ready CPU give back control of system buses to DMAC
for 1-cycle in which the prepared word is transferred to memory.
 As compared to Burst mode this mode is little bit slowest since it requires little bit of
time which is actually consumed by IO device while preparing the data.
Mode-3: Interleaving Mode –
 Whenever CPU does not require the system buses then only control of buses will be
given to DMAC.
 In this mode, CPU will not be blocked due to DMA at all.
 This is the slowest mode of DMA Transfer since DMAC has to wait might be for so
long time to just even get the access of system buses from the CPU itself.
 Hence due to which less amount of data will be transferred.

Software and Hardware Interrupts

Processor handle interrupts
Whenever an interrupt occurs, it causes the CPU to stop executing the current
program. Then, comes the control to interrupt handler or interrupt service routine.
These are the steps in which ISR handles interrupts. These are as follows −
Step 1 − When an interrupt occurs let assume processor is executing i' th instruction
and program counter will point to the next instruction (i+1) th.
Step 2 − When an interrupt occurs the program value is stored on the process stack
and the program counter is loaded with the address of interrupt service routine.
Step 3 − Once the interrupt service routine is completed the address on the process
stack is popped and placed back in the program counter.
Step 4 − Now it executes the resume for (i+1)th line.
Types of interrupts
There are two types of interrupts which are as follows −
Hardware interrupts
The interrupt signal generated from external devices and i/o devices are made
interrupt to CPU when the instructions are ready.
Hardware Interrupt is caused by some hardware device such as request to start an I/O,
a hardware failure or something similar. Hardware interrupts were introduced as a way to
avoid wasting the processor’s valuable time in polling loops, waiting for external events.
For example − In a keyboard if we press a key to do some action this pressing of the
keyboard generates a signal that is given to the processor to do action, such interrupts are
called hardware interrupts.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
Hardware interrupts are classified into two types which are as follows −
 Maskable Interrupt − The hardware interrupts that can be delayed when a highest
priority interrupt has occurred to the processor.
 Non Maskable Interrupt − The hardware that cannot be delayed and immediately be
serviced by the processor.
Software interrupts
The interrupt signal generated from internal devices and software programs need to
access any system call then software interrupts are present.
Software Interrupt is invoked by the use of INT instruction. This event immediately
stops execution of the program and passes execution over to the INT handler. The INT
handler is usually a part of the operating system and determines the action to be taken. It
occurs when an application program terminates or requests certain services from the
operating system.
Software interrupt is divided into two types. They are as follows −
 Normal Interrupts − The interrupts that are caused by the software instructions are
called software instructions.
 Exception − Exception is nothing but an unplanned interruption while executing a
program. For example − while executing a program if we got a value that is divided
by zero is called an exception.

8259 PIC (Programmable Interrupt Controller ) Microcontroller:

Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware
interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors
respectively. But by connecting Intel 8259 with these microprocessors, we can increase their
interrupt handling capability.
Intel 8259 combines the multi-interrupt input sources into a single interrupt output.
Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.
For example, Interfacing of 8085 and 8259 increases the interrupt handling capability
of 8085 microprocessor from 5 to 8 interrupt levels.

Features of Intel 8259 PIC are as follows:

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading
further 8259 PICs.
5. Clock cycle is not required.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
 Pin Diagram of 8259 –
We can see through above diagram
that there are total 28 pins in Intel 8259
PIC where Vcc : 5V Power supply and
Gnd : ground. Other pins use are explained
below. Block Diagram of 8259 PIC
microprocessor –

T
he

Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic,
Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR,
IMR.
1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086
microprocessor by acting as a buffer. It takes the control word from the 8085 (let say)
microprocessor and transfer it to the control logic of 8259 microprocessor.
After selection of Interrupt by 8259 microprocessor (based on priority of the
interrupt), it transfer the opcode of the selected Interrupt and address of the Interrupt
service sub routine to the other connected microprocessor. The data bus buffer consists
of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8
bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is low (as this pin is
active low). This block is responsible for the flow of data depending upon the inputs of
RD and WR. These two pins are active low pins used for read and write operations.
3. Control logic – It is the center of the PIC and controls the functioning of every block. It
has pin INTR which is connected with other microprocessor for taking interrupt request
and pin INT for giving the output.
If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes
the value of the output INT pin high and in this way 8259 responds to the request made
by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level which are requesting
for Interrupt services.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.
5. Interrupt service register (ISR) – It stores the interrupt level which are currently being
executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which have to be masked
by storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the priority of interrupts
and according to the priority of the interrupts, interrupt with highest priority is set in ISR
register. Also, it reset the interrupt level which is already been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we can further cascade
more number of pins by using cascade buffer. So, during increment of interrupt
capability, CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode
else in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work
as master or slave and in Buffered mode, SP/EN pin is used as an output to enable data bus.

C. Maleappane Lawrence Vanangamoudiar, Assistant Professor in Computer Science Department,

Rajiv Gandhi Arts and Science College, Pondicherry.