Scribd
Upload
8 views4 pages

Chapter32-MS Exam Questions

The document contains a series of mark schemes for questions related to computer architecture and memory systems, focusing on understanding key concepts such as the roles of main memory, data buses, and different architectures like Harvard and von Neumann. Each question specifies the marks allocated for correct responses and includes criteria for acceptable answers. The document outlines the necessary components and processes involved in data transfer and memory operations within a computer system.

Uploaded by

KM Hedar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
8 views4 pages

Chapter32-MS Exam Questions

The document contains a series of mark schemes for questions related to computer architecture and memory systems, focusing on understanding key concepts such as the roles of main memory, data buses, and different architectures like Harvard and von Neumann. Each question specifies the marks allocated for correct responses and includes criteria for acceptable answers. The document outlines the necessary components and processes involved in data transfer and memory operations within a computer system.

Uploaded by

KM Hedar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

Mark schemes

Q1.
Marks are for AO1 (understanding)

Main memory stores the instructions to be executed (and any data required by those
instructions);

Main memory returns the instructions / data / value stored in a memory location
(specified on the address bus) (using the data bus);

Program is transferred from secondary storage into main memory (if program not
already in main memory) when program execution is requested;

Main memory stores any value / data resulting from the execution of the program;

MAX 2
[2]

Q2.
2 marks are for AO1 (understanding)

When data/instructions are needed/fetched they have to be transferred from


memory to the processor (using the data bus);
(after execution) result/data may need to be transferred back to memory (using the
data bus);

A. responses referring to I/O controllers instead of memory


[2]

Q3.
2 marks are for AO1 (understanding)

In the Harvard architecture:


Instructions and data have separate buses;
Instructions and data are stored in separate memories // Instructions and data have
separate memory/address spaces; NE. Places, locations, registers, areas of
memory
Instruction word size can be different to data word size // Instruction bus width can
be different to data bus width;
Instructions and data can be fetched simultaneously;

A. points made in reverse that state how the von Neumann architecture works

MAX 2
[2]

Page 1 of 4
Q4.
Marks are for AO1 (understanding)

• The address of the memory to be written to is placed on the address bus (by the
processor);
• The data to be written is placed on the data bus (by the processor);
• The signal to write is placed on the control bus (by the processor);
• The control bus carries a clock signal (to synchronise the memory and processor);
• When the write signal is received (by the memory) on the control bus; the data from
the data bus is stored; into the location identified by the address bus;

A. CPU for processor

NE. Implication that the busses are doing the ‘sending’ rather than ‘carrying’ of data /
addresses / signals

Max 2 per bus


Max 3 if only two buses referenced
Max 4 marks
[4]

Q5.

All marks AO1 (understanding)

Correct Name from List

B Visual display unit;

C Processor;

D Main memory;

E Keyboard;

1 mark per correct answer


A If same response used more than once
[4]

Q6.

(a) A set of / group of / parallel wires / lines;

Wires needs to be qualified with set / group

that are used to connect together components (inside the computer) //


connect different parts of the CPU

in order to pass signals between them;

R a wire
A connect different parts of the computer

Page 2 of 4
NE data
Max 2

(b) Instructions;
A Commands / machine-code
R signals

Examples of a control signal (Max 1):


NE an event that details when an interrupt would be caused

Clock / timing; reset; interrupt ACK; interrupt request; bus grant; bus request;
status; I / O write; I / O read; memory read; memory write; transfer ACK
A interrupt A transfer request
A read / write
NE load / store
NE clock speed
2

(c)

1 mark – one of processor, keyboard controller


or graphics controller identified correctly
2 marks – all three correctly identified

Address bus connects the 4 components;


Arrow from processor to the address bus;
Arrows from address bus to the three other components;

Mark this on where the candidate has put the components.


5
[9]

Q7.

(a) Address (bus);


1

Page 3 of 4
(b) 1;
R 33
1

(c) A – Visual display unit; A VDU


B – Processor; R CPU
C – (Main) memory;
D – Keyboard;
4
[6]

Page 4 of 4

You might also like