08 Architecture of 8085
08 Architecture of 8085
MICROPROCESSORS
ENR107
Accumulator: Flags:
The accumulator is an 8-bit 5 flip flops
register that is a part of 1- zero (Z),
arithmetic/logic unit (ALU). 2-carry (CY),
This register is used to store 8- 3-sign (S),
bit data and perform 4-parity (P)
arithmetical and logical 5-auxiliary carry (AC)
operations. The result of an
operation is stored in the
accumulator. The accumulator
is also identified as register A.
Register Unit
The register unit consists of six general purpose data registers B, C, D, E, H and L, two
internal registers W and Z, two 16-bit address registers PC and SP, one
increment/decrement counter register and one MUX/DEMUX.
W Z
Register Unit
MUX/DEMUX Unit
This unit is used to select a
register out of all the available
registers.
It behaves as a MUX when data
is going from the register to the
internal data bus.
It behaves as a DEMUX when
data is coming to a register from
the internal data bus of the
microprocessor.
The register select will behave as
the function selection lines of the
MUX/ DEMUX.
Control Unit
The control unit generates signals within microprocessor to carry out the instruction,
which has been decoded. In reality it causes certain connections between blocks of
the microprocessor to be opened or closed, so that the data goes where it is required
and the ALU operations occur.
The control unit itself consists of three parts;
1- the instructions register (IR),
This register holds the machine code of the instruction. When microprocessor executes a
program it reads the opcode from the memory, this opcode is stored in the instruction
register.
2- instruction decoder and machine cycle encoder,
The IR sends the machine code to this unit. This unit decodes the opcode and finds out
what is to be done in response of the coming opcode and how many machine cycles are
required to execute this instruction.
3- control and timing unit,
The control unit generates signals within microprocessor to carry out the instruction,
which has been decoded. In reality, it causes certain connections between blocks of the
microprocessor to be opened or closed, so that the data goes where it is required and the
ALU operations occur.
Control unit
Instruction register
Stores the Opcode
Instruction decoder
Decodes the instruction and hence decodes the
number of cycles required
Control and timing unit
Generates the signals to carry out the instruction
1.Memory read
2.Memory write
3.IOR
4.IOW
8085 Bus system
Bus
Six 4-bit combinations (1010, 1011, 1100, 1101, 1110, 1111) are unused.
BCD CODE
Decimal BCD Code
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 0001 0000
BCD CODE
Advantages:
i) Ease of Conversion: Simple and no complex calculations are required.
ii) Direct Display: Can be directly displayed on numeric displays without the need for additional
conversion.
Limitations:
i) Inefficient storage: Requires more bits to represent a value in comparison to binary representation.
Correction required when the nibble is an invalid combination (>9) or there is a carry from the
previous nibble. 0110 is added for correction.
Examples
3.Multiplexed address/data
bus
5. Serial IO signals
6. Externally or peripheral
initiated signals.
Group 1: Power Supply and Frequency Signals
Internal clock
X1, X2 (Input) two input lines across which a Crystal or R/C oscillator
circuit is connected to provide the required clock frequency to the
microprocessor. The frequency generated by the oscillator is divided by 2 to
give the internal operating frequency of the microprocessor. The input
frequency is divided by 2 because the frequency is applied to the system
through a T flip-flop which divides the incoming frequency by 2
Group 2: Higher Order Address Bus (Output)
(ADO-AD7) The 8085A uses a multiplexed data bus. These lines are time
multiplexed with the lower 8-lines of the address bus. Lower 8-bits of the
memory address or I/O address appear on the bus during the T1 state of a
machine cycle. It then becomes
SIM:
Set Interrupt Mask
instruction, controls
hardware interrupts by
setting masking bits to
enable or disable them
Group 6: Externally or Peripheral Initiated Signals
TRAP (Input) Trap is a nonmaskable interrupt which have the highest
priority. It is recognized at the same time as INTR. This interrupt cannot be
masked or disabled. This is a vectored interrupt. It is edge as well as level
triggered.
RST 5.5, RST 6.5, RST 7.5: RESTART interrupt (inputs) These three inputs
have the same timing as INTR except they cause an internal RESTART to be
automatically inserted. These interrupts are maskable. The mask can be set
to any of these interrupts by SIM instruction.
INTR (interrupt request) (input) INTR is used as a general purpose interrupt.
INTA (interrupt acknowledge) (output) This signal is generated by
microprocessor in response to the INTR.
….
Interrupts
Example
A temperature monitoring system
Main program keeps on sampling the temperature
and storing it.
A button is provided which when pressed allows
you to print ,say the latest 20 temperature values
Polling every time will waste time
Interrupt will save time
Interrupt- one more example
Can be used to provide battery low warning
Multiple interrupt lines
Priority policy required
Highest priority for critical operations
Low power indications for example
8085 interrupt lines will be studied in some detail later
Use of external IC for demultiplexing
Use of external IC for demultiplexing
Generation of control signals