IFET

COLLEGE OF ENGINEERING
CS6201- Digital Principles and System Design

UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC

(REGULATION-2013)
(For Second Semester B.E/B.Tech students)
Department of CSE/IT

Prepared by Approved by

Mr.U.Palani HOD/IT
Mr. D.Prabakaran/ ASP Mrs.R.Geetha HOD /ECE
Ms.M.Nishanthi/AP Mr.S.Viswanathan HOD/ CIVIL

Course Coordinator

Mrs.R.Geetha HOD
 COURSE OUTCOMES (COs)

CO 1: To able the students to understand different methods used for the simplification of
Boolean functions

CO 2: To able the students to understand the concepts of combinational circuits and code
converter.

CO 3: To able the students to design and implement the synchronous sequential circuits.

CO 4: To able the students to design and implement the Asynchronous Sequential Circuits.

CO 5: To able the students to study about different types of Memory devices.

PROGRAM OUTCOMES (POs)

a. Apply knowledge of mathematics, science, engineering fundamentals and an engineering

specialization to the conceptualization of computer science engineering models.
b. Identify, formulate, research literature and solve complex engineering problems reaching
substantiated conclusions using first principles of mathematics and engineering sciences.
c. Design solutions for complex engineering problems and design systems, components or processes
that meet specified needs with appropriate consideration for public health and safety, cultural,
societal, and environmental considerations.
d. Conduct investigations of complex problems including design of experiments, analysis and
interpretation of data, and synthesis of information to provide valid conclusions.
e. Create, select and apply appropriate techniques, resources, and modern engineering tools, including
prediction and modeling, to complex engineering activities, with an understanding of the limitations.
f. Function effectively as an individual, and as member or leader in diverse teams, and in
multidisciplinary settings.
g. Communicate effectively on complex engineering activities with the engineering community and with
the society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
h. Demonstrate understanding of the societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to engineering practice.
i. Understand and commit to professional ethics and responsibilities and norms of engineering practice.
j. Understand the impact of engineering solutions in a societal context and demonstrate knowledge of
and need for sustainable development.
k. Demonstrate a knowledge and understanding of management and business practices, such as risk and
change management, and understand their limitations.
l. Recognize the need for, and have the preparation and ability to engage in independent and life-long
learning in the broadest context of technologies.
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IFET COLLEGE OF ENGINEERING

GANGARAMPALAYAM,VILLUPURAM-605108.
DEPARTMENT OF CSE & IT.

SUBJECT CODE :CS6201 SEM : II

SUBJECT NAME : Digital Principles and System Design YEAR: I
Syllabus
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables –
Race-free State Assignment – Hazards.

Asynchronous Sequential Circuits: In asynchronous sequential circuit, the memory elements

are either unclocked flip flops or time delay elements. Therefore in asynchronous sequential
circuits, the change in the input signals can affect memory element at any instant of time.
Types of Asynchronous sequential circuits: Fundamental mode Asynchronous sequential
circuits, Pulse mode Asynchronous sequential circuits.
Advantage of Asynchronous sequential circuits:
The advantages of asynchronous sequential circuits are:
 Change in input signals may affect the memory element at any instant of time.
 More faster in operation.
Disadvantage of Asynchronous sequential circuits:
 Clock is absent and state change may occur according to time delay.
 Circuit is difficult to design.
State table: The state table representation of a sequential circuit consists of three sections
labeled present state, next state and output. The present state designates the state of flip-flops
before the occurrence of a clock pulse. The next state shows the states of flip-flops after the
clock pulse, and the output section lists the value of the output variables during the present state.
State diagram: In addition to graphical symbols, tables or equations, flip-flops can also be
represented graphically by a state diagram.

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Flow table: A flow table is similar to a transition table except that the internal states are
symbolized with letters rather than binary numbers. The flow table also includes the output
values of the circuit for each stable state.
Primitive flow table: A Primitive flow table is a special case of flow table. It is defined as a
flow table which has exactly one stable state for each row in the table.
Transition table: A state table with binary assignment is called transition table. Transition table
of asynchronous sequential circuits similar to the state table used for synchronous sequential
circuits.
Merger graph: Merger graph is a state reduction tool used to reduce states in the incompletely
specified machine.
Two methods to realize a flow table: Implementation using traditional method,
Implementation using SR latch.
State assignment: To determine the flip flop input functions, it is necessary to represent states
in the state diagram using binary values instead of alphabets. This procedure is known as state
assignment.
Race: Races exist in asynchronous sequential circuits when two or more binary start variables
change during a state transition. Races are classified as: Non-critical races, Critical races.
Cycle: A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to
stable to another, until the inputs are changed.
Race free state assignment: In asynchronous sequential circuits, the objective of state
assignment is to avoid critical races. In a race free state assignment, one state variable changes
during each state transition.
Shared Row state assignment: In shared row state assignment, an extra row is introduced in a
flow table that is shared between two stable states.
Multiple Row state assignment: The multiple row state assignment technique specifies that
each row in the original flow table be replaced with two rows.
One Hot state assignment: In this method, only one variable is active or hot for each row in
the original flow table. i.e. it requires one state variable for each row of the flow table.

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Hazards: Hazards are defined as unwanted switching transients that may appear at the output of
a circuit.
Types of Hazards: Static-0 Hazard, Static-1 Hazard, Dynamic hazard, Essential hazard.
Static Hazard: Static hazard is an condition which results in a single momentary incorrect
output due to change in a single input variable when the output is expected to remain in the
same state.
Dynamic Hazard: Dynamic hazards occur when the output of a network is to change between
its two logic states, but a momentary false output signal occurs during the transient behavior.
Essential hazard: Essential hazard is a type of hazard that exists only in asynchronous
sequential circuits with two or more feedbacks.
Two Marks
Analysis of Asynchronous Sequential Circuits:

1. What is meant by Asynchronous sequential circuit?

In asynchronous sequential circuit, the memory elements are either unclocked flip
flops or time delay elements. Therefore in asynchronous sequential circuits, the change in
the input signals can affect memory element at any instant of time. In asynchronous
sequential circuit, the designer has to consider the time delays involved to determine the
maximum operating speed of the clock. In this type of circuit, the clock signal is absent and
the state change occurs according to delay times of logic.
2. Differentiate between Synchronous and Asynchronous sequential circuits.
S.No Synchronous Sequential Circuits Asynchronous Sequential Circuits
1 Memory elements are clocked flip flops Memory elements are either unclocked flip
flops or time delay elements.
2 The operating speed of the clock depends Because of absence of clock, it can operate
on time delays involved. faster than synchronous sequential circuits
3 The change in input signals affects The change in input signals can affect
memory elements upon activation of clock memory elements at any instant of time.
signal.
4 Easier to Design. More difficult to Design.

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3. What are the components present in an Asynchronous sequential circuit?

The Asynchronous sequential circuit consists of following components.

 Combinational circuit.
 Delay elements.
 “n” Input variables.
 “m” Output variables.
 “k” Internal states.

4. What are the two types of Asynchronous sequential circuits?

The Asynchronous sequential circuits are typically classified into main types. They
are:
 Fundamental mode Asynchronous sequential circuits.
 Pulse mode Asynchronous sequential circuits.

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The classification is done according to how input variables are considered in the
Asynchronous sequential circuits.

5. What are the assumptions made in Fundamental mode circuit?

The assumptions made in the fundamental mode circuit are:
 Input changes should be spaced in time by atleast Δt, the time needed for the circuit
to settle into a stable state following an input change. That is, the input variables
should change only when the circuit is stable.
 Only one input variable can change at a given instant of time.
 Inputs are levels and not pulses.
 Delay lines are used as memory elements.

6. What are the assumptions made in Pulse mode circuit?

The assumptions made in the Pulse mode circuit are:
 The input variables are pulses instead of levels.
 The width of the pulses is long enough for the circuit to respond to the input.
 The pulse width must not be so long that it is still present after the new state is
reached.
 Pulses should not occur simultaneously on two or more input lines.
 Flip flops are commonly used as memory elements.
 Memory element transitions are initiated only by input pulses.
 Input variables are used only in the uncomplemented or the complemented forms,
but not both.

7. What are the steps followed in the analysis of Pulse mode asynchronous sequential
circuits?
In the analysis of Pulse mode asynchronous sequential circuit, circuit responds
immediately to pulse on their inputs, rather than waiting for the clock signal as in
synchronous sequential circuits. The steps followed in the analysis of Pulse mode
asynchronous sequential circuits are:

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 Write the excitation and output equation for the given circuit.
 Write the characteristic equation for the given flip flop. If no flip flop has been
specified, then use T flip flop.
 Construct the state variable transition table and state diagram.
 Draw the timing diagram for the given circuit.

8. What are the procedures to analyze of Fundamental mode asynchronous sequential

circuits?
The procedures followed to analyze the fundamental mode asynchronous sequential
circuits are:
 Write the excitation and output equation for the given circuit.
 Construct the state table for the given circuit and flip flop.
 Construct the transition table to find the stable and unstable states.
 From the transition table construct the output map table.

9. How does the operation of an asynchronous input differ from that of a synchronous
input?
In asynchronous sequential circuit, the memory elements are either unclocked flip
flops or time delay elements. Therefore in asynchronous sequential circuits, the change in
the input signals can affect memory element at any instant of time. In asynchronous
sequential circuit, the designer has to consider the time delays involved to determine the
maximum operating speed of the clock. In this type of circuit, the clock signal is absent and
the state change occurs according to delay times of logic. Due to this, asynchronous
sequential circuits are more difficult to design. However because of absence of clock,
asynchronous circuits are faster than synchronous circuits.

10. Differentiate between Fundamental mode and Pulse mode asynchronous circuit.
S.No Fundamental Mode circuit Pulse Mode circuit
1 Only One input is allowed to change at a Only One input is allowed to change at a
time. time.

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2 Inputs are considered as levels. Inputs are considered as Pulse.

3 Types of Input levels are: Types of Input pulses are:
“0” and “1”. False- True-False.
4 Input level changes can occur no faster Input pulses to be long enough to initiate
than allowed by the slowest propagation the state change.
path in circuit.
5 Delay lines are used as memory Flip Flops are used as memory elements.
elements

11. Why is the Pulse mode operation of asynchronous sequential circuits not very
popular?
The Pulse mode operation of asynchronous sequential circuits are not very popular
because of the input variables pulse width restrictions, pulse mode circuits are difficult to
design and hence they are not very popular.
But in the fundamental mode operation of asynchronous sequential circuits, the
levels are used and so the circuit design is not difficult. Hence the fundamental mode
operations of asynchronous sequential circuits are more popular when compared to the Pulse
mode operation.

12. Mention the advantages and disadvantage of asynchronous sequential circuits.

Advantage:
The advantages of asynchronous sequential circuits are:
 Change in input signals may affect the memory element at any instant of time.
 More faster in operation.
Disadvantage:
 Clock is absent and state change may occur according to time delay.
 Circuit is difficult to design.

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13. What are the problems occurs in asynchronous circuit?

Asynchronous logic is more difficult to design and is subject to problems not
encountered in synchronous designs. The main problem is that digital memory elements are
sensitive to the order that their input signals arrive; if two signals arrive at a logic gate at
almost the same time, which state the circuit goes into can depend on which signal gets to
the gate first. Therefore the circuit can go into the wrong state, depending on small
differences in the propagation delays of the logic gates. This is called a race condition. This
problem is not as severe in synchronous circuits because the outputs of the memory
elements only change at each clock pulse.

14. Define key debounce.

For interfacing keys in digital systems, usually push buttons are used. These push
buttons when pressed bounces a few times, closing and opening the contacts before
providing a steady reading. Reading taken during the bounce period will be faulty. This
problem is known as key debounce. The problem of key debounce is undesirable and it
must be avoided. This can be avoided by using SR latch. The circuit used to avoid key
bounce with SR latch is called as Switch or contact debouncer.

Design of Asynchronous Sequential Circuits:

15. What are the steps involved in design of Pulse mode asynchronous sequential circuits?
The steps involved in design of Pulse mode asynchronous sequential circuits are:
 Define the states of the circuit, draw the state diagram and state table.
 Minimize the state table.
 Then assign the states.
 Perform K map simplification method to obtain the equations.
 Based on the obtained equations, design the logic diagram.

16. What are the steps involved in design of Fundamental mode asynchronous sequential
circuits?

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The steps involved in design of Fundamental mode asynchronous sequential circuits

are:
 Construction of a primitive flow table from the problem statement. An immediate
step may include the development of the state diagram.
 Primitive flow table is reduced by eliminating redundant states by using state
reduction techniques.
 State assignment is made.
 The primitive flow table is realized using appropriate logic elements.

17. What is the characteristic equation of various flip flops?

The characteristics equation of various flip flops are:
 SR Flip flop : Qn+1 = S + R’Qn.
 D Flip flop : Qn+1 = D
 JK Flip flop : Qn+1 = J Qn’+ K’Qn.
 T Flip flop : Qn+1 = T Qn’+ T’ Qn.
Based on the characteristics equation, the designers usually prefer the D flip flop. This is
because of its characteristic equation. In this the next state output directly depends on its
input.

Reduction of State and Flow Tables:

18. Define state table.
The state table representation of a sequential circuit consists of three sections
labeled present state, next state and output. The present state designates the state of flip-
flops before the occurrence of a clock pulse. The next state shows the states of flip-flops
after the clock pulse, and the output section lists the value of the output variables during the
present state.
A state table is essentially a truth table in which some of the inputs are the current state, and
the outputs include the next state, along with other outputs. A state table is one of many
ways to specify a state machine, other ways being a state diagram, and a characteristic
equation.

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19. Define State diagram.

In addition to graphical symbols, tables or equations, flip-flops can also be
represented graphically by a state diagram. In this diagram, a state is represented by a circle,
and the transition between states is indicated by directed lines (or arcs) connecting the
circles. An example of a state diagram is shown in Figure below.

20. Define Flow table.

During the design of asynchronous sequential circuits, it is more convenient to name
the states by letter symbols without making specific reference to their binary values. Such a
table is called as flow table. A flow table is similar to a transition table except that the
internal states are symbolized with letters rather than binary numbers. The flow table also
includes the output values of the circuit for each stable state.

21. Define Primitive flow table.

A Primitive flow table is a special case of flow table. It is defined as a flow table
which has exactly one stable state for each row in the table.

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The design process of asynchronous sequential circuit begins with the construction
of primitive flow table.

22. Define Transition table.

A state table with binary assignment is called transition table. Transition table of
asynchronous sequential circuits similar to the state table used for synchronous sequential
circuits. It is constructed which shows the next states of the flip flops as a function of the
present state and inputs.
Example:

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23. Mention the need and steps involved in state reduction techniques.
The state reduction technique basically avoids the introduction of redundant states.
The reduction in redundant states reduces the number of required flip flops and logic gates,
reducing the cost of final circuit.
Steps Involved:
 Determine the state table for the given state diagram.
 Find equivalent states: If two present states that go to the same next states, one
present state can be removed.
 Reduced state diagram for the reduced state table.

24. Mention the steps involved in reducing Primitive flow table.

To reduce the primitive flow table using state reduction technique, we use Merger
graph to reduce the primitive flow table. According to merger graph, we have the same
number of vertices as the state in flow table. The complete line between state vertices is
drawn for compatible states. Recall that the states are compatible only when for every input
sequence the same input occurs. If two sequences are incompatible no line is drawn.

25. Define Merger graph.

Merger graph is a state reduction tool used to reduce states in the incompletely
specified machine. The Merger graph is defined as follows:
 It contains the same number of vertices as the stable state contains states.
 Each compatible pair is indicated by a line drawn between the two state vertices.

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 Every potentially compatible state pair, with outputs not in conflict but whose next
states are different, is connected by a broken line. The implied states are drawn in
the line break between the two potentially compatible states.
 If two states are incompatible no connecting line is drawn.

26. What is meant by Implication chart method?

While performing state reduction of machines having a large number of states, it
may be more convenient to find the compatible pair and their implications in a merger table
of form given below instead of using merger graph. The merger table method is also called
as Paull- Unger method or Implication chart method. The table shows the state table for
sequential machine and its merger table.

27. Mention the two methods to realize a flow table.

To understand the process of realization of flow table we use two methods of
implementation. They are:
 Implementation using traditional method
 Implementation using SR latch.
In both the above mentioned methods, the flow table is realized using Karnaugh map
method to obtain the Boolean expression. Then the Boolean expression in implemented in
terms of combinational logic or using SR latch.

28. What is meant by implementation using traditional method?

The traditional method is a method to design asynchronous sequential circuit in
which the boolean expressions for functions and the output are derived using K map

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simplification. Then each boolean expression is implemented using logic gates as shown in
below example.

29. What is meant by implementation using SR Latch?

The traditional method is a method to design asynchronous sequential circuit in
which we have to derive the expressions for S and R inputs of SR latch. To derive the input
expressions first we have to obtain the K map for S and R by referring the excitation table of
SR latch and then solve the K map for S and R individually.

30. Draw the logic diagram of SR and T flip flop.

The logic diagram of SR flip flop is:

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The logic diagram of T flip flop is:

31. Draw the logic diagram for the following Boolean function Y=X1X2+(X1+X2)Y.

32. What are the different notations of state machine?

In the state machine, the boolean variables have different names according to their
generation place. The different notations are:
 Input variable.
 Output variable.
 State variable.
 Excitation variable.

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In a mealy circuit, the input represents the input variable, output term represents the output
variable, the flip flop output Q represents the state variable and the intermediate variable
represents the excitation variable.

Race-free State Assignment:

33. Write short notes on mixed operating mode asynchronous circuits.
Critical races and hazards result from unequal propagation delay paths in the
combinational logic that realizes the state variable excitation equations. A technique called
mixed operating mode( MOM) or self-synchronization is used to solve such timing
problems in an asynchronous sequential circuits. In this approach each state variable is
partitioned so that it has both synchronous and asynchronous inputs.

34. What is meant by state assignment?

In sequential circuit we know that the behavior of the circuit is defined in terms of its
inputs, present states, next states and outputs. To generate desired next state at particular
present state and inputs, it is necessary to have specific flip flop inputs. To determine the
flip flop input functions, it is necessary to represent states in the state diagram using binary
values instead of alphabets. This procedure is known as state assignment. We must assign
binary values to the states in such a way that it is possible to implement flip flop input
functions using minimum logic gates.

35. Mention the two basic rules for making state assignment.
The two basic rules for making state assignment are:
 States having the same NEXT STATES for a given input condition should have
assignments which can be grouped into logically adjacent cells in a K map.
 States that are the NEXT STATES of a single state should have assignment which
can be grouped into logically adjacent cells in K map.

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36. What is meant by race?

Races exist in asynchronous sequential circuits when two or more binary start
variables change during a state transition. Races are classified as:
 Non-critical races.
 Critical races.
The races can be identified by:
 A two-bit (or more) change in a state variable.

37. What is meant by non critical race?

Races exist in asynchronous sequential circuits when two or more binary start
variables change during a state transition. If the final stable state that the circuit reaches does
not depend on the order in which the state variable change, the race is called Non-Critical
race. If a circuit, whose transition table starts in state table 000 and then change the input
from 0 to 1.The state variable must change from 00 to 11, which define a race condition.
The possible transitions are:
00 -> 01 -> 11 Or 00 ->10 -> 11

38. What is meant by critical race?

A race becomes critical if the correct next state is not reached during a state
transition. If it is possible to end up in two or more different stable states, depending on the
order in which the state variable change, then it is a critical race. For the proper operation,
the critical races must be avoided.

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39. What is a cycle? When does a cycle occur?

A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. If a cycle does not contain a stable state, the circuit will go from one
unstable to stable to another, until the inputs are changed. Races can be avoided by directing
the circuit through intermediate unstable states with a unique state variable change. When a
circuit goes through a unique sequence of unstable states, it is said to have a cycle. The
cycle should terminate with a stable state. If the cycle does not terminate with a stable state

40. What is race free state assignment?

The state assignment step in asynchronous sequential circuits is essentially the same
as it is for synchronous circuits, except for one difference. In synchronous circuits, the state
assignments are made with the objective of circuit reduction. In asynchronous sequential
circuits, the objective of state assignment is to avoid critical races. In a race free state
assignment, one state variable changes during each state transition.

41. Mention the techniques that are commonly used for making critical race free state
assignment.
In asynchronous sequential circuits, the objective of state assignment is to avoid
critical races. In a race free state assignment, one state variable changes during each state
transition. The techniques used for making critical race free-state assignment are:

 Share row state assignment.

 Multiple row state assignment.
 One hot state assignment.

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42. Differentiate between critical race and non critical race.

S.No Critical Race Non-Critical Race

1 If the circuit reaches a different final, If the circuit reaches the same final, stable
stable state depending on the order in state regardless of the order in which the
which the state variables change, then the state variables change, then the race in non-
race is critical. critical.
2 Possible transactions: Possible transactions:
00->01->11 Or 00->10->11 00->01->11 Or 00->10->11
3 For proper operation, critical race to be For proper operation, non-critical race to be
avoided. avoided.
4 A race becomes critical if the correct If the final stable state that the circuit
next state is not reached during state reaches does not depend on the order in
transition. which the state variables change.

43. What is shared Row state assignment?

In shared row state assignment, an extra row is introduced in a flow table that is
shared between two stable states. Races can be avoided by making a proper binary
assignment to the state variables. Here the state variables are assigned with binary numbers
in such a way that only one state variable can change at any one time when a state transition
occurs. To accomplish this, it is necessary that states between which transitions occur be
given adjacent assignments.

44. What is Multiple Row state assignment?

The multiple row state assignment technique specifies that each row in the original
flow table be replaced with two rows. Each new row or total state is equivalent to the
original state before splitting. For instance, state a=a1=a2. Row “a” existed in a flow table is
replaced by rows a1 and a2. The binary assignment for state a1(000) is the complement of
binary assignment for the state a1 (111). In a multiple row state assignment, the change
form one stable to another will always cause a change of only one binary state variable

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45. What is One Hot state assignment?

The one hot state assignment is another method for finding the race free state
assignment. In this method, only one variable is active or hot for each row in the original
flow table. i.e. it requires one state variable for each row of the flow table. Additional rows
are introduced to provide single variable changes between internal state transitions. One hot
state assignment is good for programmable devices as lots of flip flops available.

46. What are the significance of state assignment?

In synchronous circuits-state assignments are made with the objective of circuit
reduction Asynchronous circuits-its objective is to avoid critical races. The state assignment
step in asynchronous sequential circuits is essentially the same as it is for synchronous
circuits, except for one difference. In synchronous circuits, the state assignments are made
with the objective of circuit reduction. In asynchronous sequential circuits, the objective of
state assignment is to avoid critical races. In a race free state assignment, one state variable
changes during each state transition.

47. Why does the critical race to be avoided?

A race condition occurs in an asynchronous circuit when 2 or more state variables
change in response to a change in the value of a circuit input. Unequal circuit delays may
imply that the 2 or more state variables may not change simultaneously – this can cause a
problem. If the circuit reaches a different final, stable state depending on the order in which
the state variables change, then the race is critical. We need to avoid critical races for
predictability and to ensure our circuit does the intended function.

Hazards:
48. Define Hazards.
Hazards are defined as unwanted switching transients that may appear at the output
of a circuit. The hazard causes the circuit to malfunction. The main cause of hazard is the
different propagation delays at different paths. Hazards occur in the combinational circuits,
where they may cause a temporary false output value. When such combinational circuits are

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used in the asynchronous sequential circuits, they may result in a transition to a wrong stable
value.

49. What are the types of Hazards?

Hazard is an unwanted switching transient that may appear at the output of a circuit.
The hazard causes the circuit to malfunction.
 Static-0 Hazard.
 Static-1 Hazard.
 Dynamic hazard.
 Essential hazard.

50. Define Static Hazard.

Hazard is an unwanted switching transient that may appear at the output of a circuit.
The hazard causes the circuit to malfunction. Static hazard is an condition which results in a
single momentary incorrect output due to change in a single input variable when the output
is expected to remain in the same state. The two types of static hazard are:
 Static-0 Hazard.
 Static-1 hazard.

51. What is static-0 hazard?

Static hazard is a condition which results in a single momentary incorrect output due
to change in a single input variable when the output is expected to remain in the same state.
Static-0 Hazard: When the output is to remain at the value 0 and a momentary 1 output is
possible during the transition between the two input states, then the hazard is called a static-
0 hazard.

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52. What is static-1 hazard?

Static hazard is a condition which results in a single momentary incorrect output due
to change in a single input variable when the output is expected to remain in the same state.
Static-1 Hazard: If the two input states both produce a 1 output in the steady state and a
momentary 0 output is possible during the transition between the two input states, then the
hazard is called Static-1 Hazard.

53. Define Dynamic Hazard.

Dynamic hazards occur when the output of a network is to change between its two
logic states, but a momentary false output signal occurs during the transient behavior. A
dynamic hazard is defined as a transient change occurring 3 or more times at an output
terminal of logic network when the output is supposed to change only once during a
transition between two input states differing in the value of one variable.

54. What is Essential hazard?

Hazard is an unwanted switching transient that may appear at the output of a circuit.
The hazard causes the circuit to malfunction. Essential hazard is a type of hazard that exists
only in asynchronous sequential circuits with two or more feedbacks. An essential hazard is
caused by unequal delays along two or more paths that originate from the same input. An
excessive delay through an inverter circuit in comparison to the delay associated with the
feedback path may cause essential hazard.

55. How does the static hazard can be avoided?

A static hazard can be removed by covering the adjacent cell with a redundant
grouping that overlaps both groupings.

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In the K map shown, the static hazard can be eliminated by covering adjacent cells. In the
above example, the term 0100, 0101, 0111, 0110 are in multiple number of groups. This is
for the purpose of avoiding the static hazards in digital circuits.

56. What are the steps followed to eliminate the hazard?

The steps followed to eliminate the hazard in the digital circuits are:
 Static hazard elimination.
 Dynamic hazard elimination.
 Essential hazard elimination.
In all the above methods of elimination of hazard, Karnaugh map plays an important role.

57. What is gate delay?

The gate delay is also called as a Propagation delay which is the average transition
delay time for the signal to propagate from input to output when the signals change in value.
It is expressed in ns. This gate delay is an important factor to produce the hazard in the
digital circuits. The error due to the propagation delay can be eliminated by multiple
grouping method in K map. The delay in propagation of results causes Hazards in circuit.

58. What is meant by essential hazard elimination?

Essential hazard can be eliminated by adding redundant gates as in static hazards.
They can be eliminated by adjusting the amount of delay in the affected path. For this, each
feedback loop must be designed with extra care to ensure that the delay in feedback path is
long enough compared to the delay of other signals that originate from the input terminals.

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The redundant gates may be added through a redundant function and that has been created
by multiple grouping in K map.

59. Define Glitch.

The undesirable output is known as Glitch problem. In a digital circuit, the flip-
flops, are triggered by a pulse that must not be shorter than a specified minimum duration;
otherwise, the component may malfunction. A pulse shorter than the specified minimum is
called a glitch. A related concept is the runt pulse, a pulse whose amplitude is smaller than
the minimum level specified for correct operation, and a spike, a short pulse similar to a
glitch but often caused by ringing or crosstalk. A glitch can occur in the presence of race
condition in a poorly designed digital logic circuit.

60. Mention the advantages and disadvantage of designing Hazard free circuits.
The advantages of designing hazard free circuits are:
 The output of the circuit will be accurate.
The disadvantages of designing hazard free circuits are:
 More number of gates are used.
 The circuit complexity is more.
 Propagation delay is more.

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16 Marks
1. Analysis the given pulsed asynchronous sequential circuit. (16)

Solution:
Step 1: Determine the circuit excitation and output equations.
For given circuit excitation and output equations are
SA =x1 A
R A =x 2 A
Z=x1 A

Step 2: Determine the next state equation of state variable.

The characteristics equation for SR flip-flop is

Qn  S  RQn

Using the characteristic equation and excitation equations we have the state variable next state
equation is as follows

Q+A =x1 A+(x 2 A)A

Step 3: Construct the state variable transition table

From next state and output equations we can construct the state variable transition table indicating
state variables, input variables, next state values and the output value.

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Step 4: Derive the flow table and state diagram:

Flow table:

State diagram

Step 5: Draw the timing diagram:

2.Consider the asynchronous sequential circuit which is driven by the pulses, as shown in the
bellow figure. Analyze the circuit.

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Solution:
Step 1: Determine the circuit excitation and output equations.
SA  W  X , SA  W  X
RA  Y , R A  Y
SB  Y
RB  Z
C  (W  X ).B

Step 2: Determine the next state equations for state variables.

The characteristic equation for SR flip-flop is
Qn  S  RQn
QA  W  X  YA
QB  Y  ZB

Step 3: Construct the state variable transition table:

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Step 4: Derive the flow table and state diagram:

State diagram:

3.Design a pulse mode circuit having two inputs lines, x1 and x2 and output line z, as shown in
bellow figure. The circuit should produce an output pulse to coincide with the last input
pulse in the sequence x1-x2-x2. No other input sequence should produce an output pulse.
(16) May-08

Solution:
Step 1: Define the states and draw the state diagram and/or state table of the circuit:
S1=the last input was x1
S2=the sequence x1-x2 occurred
S3=the sequence x1-x2-x2 occurred.

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State diagram:

State table:

Step 2: Minimize the state table.

Step 3: Assign states: S0=00, S1=01, S2=10
Step 4:Flip-flop used is T
Step 5: Construct the execution table for the circuit.

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Step 6: K-map simplification for T inputs and z output.

TA =AX1 +BX 2
TB  BX 1  AX 2
Z  BX 2

Step 7: Draw the logic diagram

4. Analyze the fundamental mode asynchronous sequential circuit given in following fig.(16)

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Solution:
Step 1: Determine next secondary state and output equations.
X1=X0I’1+X0X1I0
X0=X0I0I1+X1I’0
Z=X0X1I0
Step 2: Construct state table:

Step 3: Transition table

Step 4: Output map

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5.An Asynchronous sequential circuit is described by the following excitation and output
function.Y=X1X2+(X1+X2)Y, Z=Y
i) Draw the logic diagram of the circuit.
ii) Derive the transition table and output map.
iii) Describe the behavior of the circuit. (16)
Solution:
i)Logic diagram:

ii) State table:

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Transition table:

Output Map:

iii) The circuit gives carry output of the full adder circuit.

6.Design an asynchronous sequential circuit with two inputs X and Y and with one output Z.
whenever Y is 1, input X is transferred to Z. When Y is 0, the output does not change for
any change in X. (16) May-03
Solution:
Step 1: Draw the state diagram

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Step 2: Reduction of Primitive flow table.

Primitive flow table:

Step 3: Reduced flow table

(A,B,C)=S0
(D,E,F)=S1
State assignment:
S0=0 S1=1
Reduced flow table:

Transition table:

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Step 4: Realization of circuit using logic elements:

K map simplification:

Logic diagram:

7.Design an asynchronous sequential circuit that has inputs X2 and X1 and one output Z.
When X1=0, the output Z is 0.the first change in X2 that occurs while X1 is 1 will cause
output Z to be 1. the output Z will remain 1 until X1 returns to 0. (16)Nov-08,May-09
Solution:
Step 1: Draw the state diagram

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Primitive flow table:

Step 2: Reduction of Primitive flow table.

(A,B)=S0
(C,E)=S1
(D,F)=S2
Reduced flow table:

Step 3: State assignment:

Flow table with state assignment:

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Transition table:

Step 4:Realization of circuit using logic elements:

K-map simplification:

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Logic diagram:

8. Design a T flip-flop from logic gates. (16) Nov-07,08,09

Solution:
Step 1: Step 1: Draw the state diagram

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Primitive flow table:

Step 2: Reduction of flow table:

(A,B,C)=S0 (E,F,H)=S2
D=S1 G=S3
Reduced Primitive flow table:

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Step 3: State assignment

S0=00, S1=01, S2=10 S3=11

Transition table:

Step 4: Realization of circuit using logic elements:

K-map simplification:

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Logic diagram:

9.Design a circuit with inputs A and B to give an output Z=1 when AB=11 but only if A
becomes 1 before B, by drawing total state diagram, primitive flow table and output map
in which transient state is included. (16) May-06
Solution:
Step 1: Draw state diagram and derive primitive flow table

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Primitive flow table:

Step 2: Reduction to primitive flow table:

(A,B,D)=S0
C=S1
E=S2
Step 3: State assignment:
S0=00, S1=01, S2=10

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Transition table:

Step 4: Realization of circuit using logic elements:

K-map simplification:

10. Obtain a primitive flow table for a circuit with two inputs x1 and x2 and two outputs z1
and z2 that satisfies the following four conditions.
i)When x1 x2=00 output z1z2=00
ii) When x1=1 and x2 changes from 0 to 1, the output z1z2=01.
iii) When x2=1 and x1 changes from 0 to 1, the output z1z2=10.
iv) Otherwise the output does not change. (16)

Solution:
State diagram:

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Primitive flow table:

11. Derive a circuit specified by the following flow table. May-11 (16)
00 01 11 10
A A,0 A,0 A,0 B,0
B A,0 A,0 B,1 B,1

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Solution: To obtain the circuit described by a flow table we assign a distinct binary value to
each state. Such an assignment converts the low table into a transition table. We assign binary 0
to state a and binary 1 to state b.
Transition table:

W=xy’+xw

Output map

Z=xw
Logic diagram:

12. With suitable example and diagram explain the concept of reduction of state and flow
tables. May-10, (16)
Solution:
Merger graph is state reducing tool used to reduce states in the completely specified machine.
The merger graph is defined as follows

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a. It contains the same number of vertices as the state table contains states.
b. Each compatible state pair is indicated by a line drawn between the two state
vertices.
c. Every potentially compatible state pair, with outputs nott in conflict but whose next
states are different, is connected by a broken line. The implied states are drawn in
line break between the two potentially compatible states.
d. If two states are incompatible, no connecting line is drawn.
Example: Design an asynchronous sequential circuit with two inputs X and Y and with one
output Z. whenever Y is 1, input X is transferred to Z. When Y is 0, the output does not
change for any change in X.
Step 1: Draw the state diagram

Step 2: Reduction of Primitive flow table.

Primitive flow table:

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Step 3: Reduced flow table using merger graph

(A,B,C)=S0
(D,E,F)=S1

State assignment:
S0=0 S1=1
Reduced flow table:

Step 4: Realization of circuit using logic elements:

K map simplification:

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13. Explain in detail about races and cycles with neat diagrams. Nov-11 (16)
Solution:
Races: When two or more binary state variables change their value in response to a change in
an input variable, race condition occurs in an asynchronous sequential circuit. In case of
unequal delays, a race condition may cause the state variables to change in an unpredictable
manner. For example, if there is a change in two state variables due to change in input variable
such that both change from 00 to 11.

In this situation the difference in delay may cause the first variable to faster than the second
resulting the state variables to change in sequence from 00 to 10 and then to 11. On the other
hand if the second variable changes faster than the first, the state variables change from 00 to
01 and then 11. If the final stable state that circuit reaches does not depend on the order in
which the state variable changes the race condition is not harmful and it is called a noncritical
race. but, if the final stable state depends on the order in which the state variable changes, the
race condition is harmful and it is called a critical race.

Non critical race: X is input variable and y1 y2 are the state variables. Consider a circuit is in a
stable state y1y2x=000 and there is a change in input from 0 to 1.with this change in the input.
there are three possibilities that the state variable may change . they can either change
simultaneously from 00 to 11, or they may change in sequence from 00 to 01 and then to 11, or
they may change in sequence from 00 to 10 and then to 11.

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Critical race: Consider a circuit is in a stable state y1y2x=000 and there is a change in input
from 0 to 1. If state variables change simultaneously, the final stable state is y1y2x=111. If Y2
changes to 1 before Y1because unequal propagation delay, then the circuit goes to the stable
state 011 and remain there. On the other hand, if Y1 changes faster than Y2then the circuit goes
to the critical because the circuit goes different stable states depending on the order in which
the state variables change.

Cycles: A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. When a state assignment is made so that it introduces cycles, care must be
taken to ensure that each cycle terminates on a stable state. If a cycle does not contain a stable
state, the circuit will go from one unstable state to another, until the inputs are changed.
Obviously ,such a situation must always be avoided when designing asynchronous circuits.

1.Shared row state assignment: Races can be avoided by making a proper binary assignment
to the state variables. Here the state variables are assigned with binary numbers in such a way
that only one state variable can change at any one time when a state transition occurs. To
accomplish this it is necessary that states between which transitions occur be given adjacent
assignments. Two binary values are said to be adjacent if they differ only in third bit.

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Transition diagram:

Transition diagram with race free state assignment:

2. One hot state assignment: The one hot state assignment is an another method for finding a
race free state assignment. In this method only one variable is active or hot for each row in the
original flow table. It requires one state variable for each row of the flow table. Additional
rows are introduced to provide single variable changes between internal state transitions.

Flow table:

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One hot state assignment flow table:

14. Describe the hazards that occur in asynchronous sequential circuits. Brief the procedure
to eliminate it. (16)
Solution:
Hazards: the unwanted switching transitions that may appear at the output of a circuit are
called hazards. The hazards cause the circuit to malfunction. The main cause of hazards is the
different propagation delays at different paths.
Hazards occur in the combinational circuits where they may cause a temporary false output
value. When such combinational circuits are used in the asynchronous sequential circuits, they
may result in a transition to a wrong stable state.
Two types of Hazards:
Static hazards: A static hazard exists if a signal is supposed to remain at particular logic value
when an input variable changes its value, but instead the signal undergoes a momentary change
in its required value
Two types of Static hazards:
Static-1 hazard: if output goes momentarily 0 when it should remain a 1, this hazard is known
as static-1 hazard.
Static-0 hazard: if output goes momentarily 1 when it should remain a 0, this hazard is known
as static-1 hazard.

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Dynamic hazards: Another type of hazard is dynamic hazard in which output changes three or
more times when it should change from 1 to 0 or from 0 to 1.
Eliminating Hazards: Hazards can be eliminated by enclosing two minterms or maxterms. If the
ircuit has minterm x1x2+x’2x3 then these two minterms must be enclosed by introducing another
minterm x1x3.

Y= x1x2+x’2x3 Y= x1x2+x’2x3 + x1x3

15. A. With suitable example and diagram explain the hazards in sequential logic circuits. (8)
Solution:
The combinational circuits are associated with them to drive the flip-flop inputs. In
synchronous sequential circuits, the hazards due to combinational circuits associated with them
are not of concern. This is because momentary erroneous signal are not generally troublesome
in synchronous circuits. However if a momentary incorrect signal is fed back in an
asynchronous sequential circuit to go to the wrong stable state.
Logic diagram:

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Transition table:

Such a hazard can be eliminated by enclosing two minterms by another minterms.

15.B. Explain in detail about mixed operating mode asynchronous circuits. (8)
Solution:
Critical races and hazards result from unequal propagation delay paths in the combinational
logic that realizes the state variable excitation equations. A technique called mixed operating
mode( MOM) or self-synchronization is used to solve such timing problems in an
asynchronous sequential circuits. In this approach each state variable is partitioned so that it
has both synchronous and asynchronous inputs.
Mixed operating mode sequential circuit model:

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16. Give hazard-free realization for the following Boolean function. (16)
f(A,B,C,D)=  m(0, 2,6,7,8,10,12)

Solution:

K-map:

Logical diagram:

17. Explain in detail about essential hazards and how to eliminate essential hazards. (16)
Solution:
One type of hazards that may occur in asynchronous sequential circuit is called essential
hazards. An essential hazard is caused by unequal delays along two or more paths that
originate from the same input. Such hazards can be eliminated by adjusting the amount of
delays in the affected path.

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Eliminating Essential hazards:

We can also avoid essential hazards in asynchronous sequential circuits by implementing
them using SR latches. A momentary 0 signal applied to the S or R inputs of a NOR latch will
have no effect on the state of the circuit. Similarly a momentary 1 signal applied to the S and R
inputs of a NAND latch will have no effect on the state of the latch.
Let us consider a NAND S Latch with the following function for S and R
S=AB+CD
R=A’C

The first leel consists of NAND gates that implement each product term in the orginal Boolean
expression of S and R.
The second level forms the cross coupled connection of the SR latch with inputs that come
from the outputs of each NAND gate in the first level.

18. Implement the switching function F=  m(1,3,5,7,8,9,14,15) by a static hazard free two

level AND-OR gate network. (16) Nov-12

Solution:
K-map simplification:

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Logical diagram:

19. A. Give hazard-free realization for the following Boolean functions. (8)
f(A,B,C,D)=  m(0,1,5, 6, 7,9,11)

Solution:

F=ABC+ABD+BCD+ACD+ABD+ABC

B. Give hazard-free realization for the following Boolean function. (8)

F(I,L,K,L)=  m(1,3, 4,5,6,7,9,11,15)

Solution:

F=JL+IJ+KL+IL

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20. Find a static and dynamic hazard free realization for the following function using
i)NAND gates. ii) NOR gates. f(a,b,c,d)=  m(1,5,7,14,15) (16) Nov-10

Solution:
i) Circuit realization using NAND gate

F=acd + abd + bcd + abc

Logical diagram:

ii) Circuit realization using NOR gate:

Steps:
a. Complement the inputs
b.Complement the output
c. Replace NAND gate by NOR gate

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Logical diagram:

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