IFET

COLLEGE OF ENGINEERING
CS6201- Digital Principles and System Design
UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES

(REGULATION-2013)
(For Second Semester B.E/B.Tech students)
Department of CSE/IT

Prepared by Approved by

Mr.U.Palani HOD/IT
Mr. D.Prabakaran/ ASP Mrs.R.Geetha HOD /ECE
Ms.M.Nishanthi/AP Mr.S.Viswanathan HOD/ CIVIL

Course Coordinator

Mrs.R.Geetha HOD
 COURSE OUTCOMES (COs)

CO 1: To able the students to understand different methods used for the simplification of
Boolean functions

CO 2: To able the students to understand the concepts of combinational circuits and code
converter.

CO 3: To able the students to design and implement the synchronous sequential circuits.

CO 4: To able the students to design and implement the Asynchronous Sequential Circuits.

CO 5: To able the students to study about different types of Memory devices.

PROGRAM OUTCOMES (POs)

a. Apply knowledge of mathematics, science, engineering fundamentals and an engineering

specialization to the conceptualization of computer science engineering models.
b. Identify, formulate, research literature and solve complex engineering problems reaching
substantiated conclusions using first principles of mathematics and engineering sciences.
c. Design solutions for complex engineering problems and design systems, components or processes
that meet specified needs with appropriate consideration for public health and safety, cultural,
societal, and environmental considerations.
d. Conduct investigations of complex problems including design of experiments, analysis and
interpretation of data, and synthesis of information to provide valid conclusions.
e. Create, select and apply appropriate techniques, resources, and modern engineering tools, including
prediction and modeling, to complex engineering activities, with an understanding of the limitations.
f. Function effectively as an individual, and as member or leader in diverse teams, and in
multidisciplinary settings.
g. Communicate effectively on complex engineering activities with the engineering community and with
the society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
h. Demonstrate understanding of the societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to engineering practice.
i. Understand and commit to professional ethics and responsibilities and norms of engineering practice.
j. Understand the impact of engineering solutions in a societal context and demonstrate knowledge of
and need for sustainable development.
k. Demonstrate a knowledge and understanding of management and business practices, such as risk and
change management, and understand their limitations.
l. Recognize the need for, and have the preparation and ability to engage in independent and life-long
learning in the broadest context of technologies.
Regulation-2013 Academic Year: 2014-15

IFET COLLEGE OF ENGINEERING

VILLUPURAM- 605108.

SUBJECT:CS6201- Digital Principles and System Design YEAR/SEM :I/ II

UNIT-1 BOOLEAN ALGEBRA AND LOGIC GATES (100% Numerical )
Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and
Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and
Tabulation Methods – Logic Gates – NAND and NOR Implementations.
Review of Number Systems
Decimal Number system: The decimal number system has 10 numerals or symbols. The
decimal number system is called as base-10 system.
Binary number system: This number system has two digits 0 and 1. The decimal number
system is called as base-2 system.
Octal number system: It has eight digits 0 to 7. The octal number system is a base 8 number
system.
Hexa decimal number system: It has sixteen digits 0 to 9,A,B,C,D,E,F. The hexa decimal
number system is a base 16 number system.
Difference between 1’s and 2’s complement method.
1. The 1‟s complement can be easily obtained using an inverter. The 2‟s complement is
obtained as adding 1 to the 1‟s complement.
2. The 2‟s complement system requires only one arithmetic operation, but the 1‟s
complement system requires two arithmetic operations.
3. The 1‟s complement is used in logical manipulation for inversion operation; the 2‟s
complement is used only for arithmetic applications.
Binary arithmetic: Binary addition Binary Subtraction Binary Multiplication

A+B Sum Carry A-B Difference Borrow 0x0=0

0+0 0 0 0-0 0 0 0x1=0
0+1 1 0 0-1 1 1 1x0=0
1+0 1 0 1-0 1 0 1x1=1
1+1 0 1 1-1 0 0

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Binary Codes: Weighted codes, Reflective codes, Non weighted codes, Sequential codes, Alpha
numeric codes, Error detecting and correcting code
Boolean Algebra and Theorems:
i)Commutative Law iii) Distributive Law
(A+B)= (B+A) A+(B.C)= (A+B) (A+C)
(A.B)= (B.A) A. (B+C) = (A.B) +(A.C)
ii)Associative Law
A+ (B+C) = (A+B) +C
(A.B).C=A. (B.C)
DeMorgan’s theorem.
1. The complement of a product is equal to the sum of the complements.(AB)' = A' + B'
2. The complement of a sum term is equal to the product of the complements. (A +B)' = A'B'

Boolean Functions:The two forms of Boolean expressions are:

i).Sum of Products Form (SOP)- It is defined as the group of product terms ORed together consists
of two or more product terms.
Y=AB+BC
ii).Product of Sum Form (POS)- It is defined as the group of sum terms ANDed together consists of
two or more sum terms.
Y=(A+B)(B+C)
Karnaugh map:A Karnaugh map is a method of minimizing the Boolean function by a systematic
approach. K map is a pictorial form of truth table, in which the map diagram is made up of squares,
with each squares representing one minterm of the function. It is of five types starting with one
variable k-map,two variable k-map,3 variable k-map,4 variable k-map and five variable k-map.
Don’t care conditions: In some logic circuits, certain input conditions never occur; therefore the
corresponding output never appears. In such cases the output level is not defined, it can be either
HIGH or LOW. These output levels are indicated by „X‟ or „d‟ in the truth tables and are called
don‟t care outputs or don‟t care conditions or incompletely specified functions. The Boolean
function in which don‟t care outputs exists is called incomplete Boolean function or incompletely
specified functions.
Quine-McCluskey method or Tabulation method: For increased number of input variable K-
Map method will be more complex. So for that we can adopt Quine Mc-cluskey method. It is most

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effective method which is used to simplify the Boolean functions. It is also called as the Tabulation
method. The fundamental principle is is that the minterms while binary equivalent differ only in one
place can be combined to reduce the minterms.
Prime Implicant: All the implicants of a function determined using a Karnaugh map are called
prime implicants.
Logic Gates: The logic gate is an electronic circuit that has one or more input binary variables but
only one output.
1. AND gate-(A.B) 4.NAND gate-(A.B)‟
2. OR gate-(A+B) 5.NOR gate-(A+B)‟
3. NOT gate-A‟ 6.EX-OR gate-A‟B+AB‟
NAND-NAND Implementation: The rules involved in obtaining the logic diagram from a Boolean
function are
1. Simplify the given Boolean function and express it in sum of product form.
2. Draw a NAND gate for each product term of the function that has two or more literals. The
inputs to each NAND gate are the literals of the term. This constitutes a group of first level
gates.
3. If Boolean function includes any single literal or literals draw NAND gate for each single
literal and connect corresponding literal as an input to the NAND gates.
4. Draw a single NAND gate in the second level, with inputs coming from output first level
gates.
NOR –NOR Implementation: The rules involved in obtaining the logic diagram from a Boolean
function are
1. Simplify the given Boolean function and express it in product of sum form.
2. Draw a NOR gate for each sum term of the function that has two or more literals. The inputs to
each NOR gate are the literals of the term. These constitute a group of first level gates.
3.If Boolean function includes any single literal or literals, draw NOR gate for each single literal
and connect corresponding literal as an input to the NOR gate.
4. Draw a single NOR gate in the second level, with inputs coming from output of first level gates

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Two Marks
Review of Number Systems
1. What are the types of number system in digital electronics? May-03
 Decimal Number system: The decimal number system has 10 numerals or
symbols. The decimal number system is called as base-10 system.
 Binary number system: This number system has two digits 0 and 1. The
decimal number system is called as base-2 system.
 Octal number system: It has eight digits 0 to 7. The octal number system is a
base 8 number system.
 Hexa decimal number system: It has sixteen digits 0 to 9,A,B,C,D,E,F. The
hexa decimal number system is a base 16 number system.
2. Find the binary equivalent of the decimal number 108.
2 108
2 54-0
2 27-0
2 13-1
2 6-1
2 3-0
1-1

Ans: (108)10=(1101100)2
3. Find (10010.011)2=(?)10
Solution:
(10010.011)2=(?)10
=(1x24)+ (0x23)+ (0x22)+ (1x21)+ (0x20). (0x2-1)+ (1x2-2)+ (1x2-3)
=(16+0+0+2+0)x(0+0.25+0.125) =(18.375)10
(10010.011)2=(18.375)10
4. Perform the following code conversion. Nov-11
(1010.10)16=(?)2=(?)8=(?)10
Solution:
Hexa decimal to binary:

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(1010.10)16=(0001000000010000.00010000)2
Binary to octal:
(0001000000010000.00010000)2=(10020.04)8
Octal to decimal:
(10020.04)8=(1x84)+ (0x83)+ (0x82)+ (2x81)+ (0x80). (0x8-1)+ (4x8-2)
=(4112.0625)10

5. Find (i) (1011011.01101)2=(?)8 (ii) (3574)8=(?)2 May-12

Solution:
(i) (1011011.01101)2=(?)8
001 011 011 . 011 010

1 3 3 . 3 2
(1011011.01101)2=(133.32)8
(ii) (3574)8=(?)2
3 5 7 4

011 101 111 100

(3574)8=(011101111100)2
Arithmetic Operations
6. Write the difference between 1’s and 2’s complement method.
i) The 1‟s complement can be easil obtained using an inverter. The 2‟s
complement is obtained as adding 1 to the 1‟s complement.
ii) The 2‟s complement system requires only one arithmetic operation , but
the 1‟s complement system requires two arithmetic operations.
iii) The 1‟s complement is used in logical manipulation for inversion
operation; the 2‟s complement is used only for arithmetic applications.

7. Mention the steps involved in 2’s complement subtraction.

The subtraction of a small number from a larger number by the 2‟s complement
method is as follows:

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1. Determine the 2‟s complement of the smallest number.

2. Add this is to the larger number
3. Omit the carry.
The subtraction of a larger number from a smaller number by the 2‟scomplement
method is as follows:
1. Determine the 2‟s complement of the larger number.
2. Add 2‟s complement to the smaller number
3. There is no carry. The result is in 2‟s complement form and is negative.
4. To get the true answer, take 2‟s complement of the result and change the
sign.
8. Perform subtraction using 1’s complement (11010)2-(10000)2. Nov-09
Solution:
1‟s complement of 10000=01111
11010
1 01001
1
Add end around carry 01010
(11010)2-(10000)2=(01010)2
9. Write short notes on binary arithmetic.
Binary addition Binary Subtraction
A+B Sum Carry A-B Difference Borrow
0+0 0 0 0-0 0 0
0+1 1 0 0-1 1 1
1+0 1 0 1-0 1 0
1+1 0 1 1-1 0 0
Binary Multiplication

0x0=0
0x1=0
1x0=0
1x1=1

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Binary Codes
10. List the types of binary codes in digital electronics.
i) Weighted codes
ii) Reflective codes
iii) Non weighted codes
iv) Sequential codes
v) Alpha numeric codes
vi) Error detecting and correcting code

11. What is meant by weighted codes?

In weighted codes, each digit position of the number represents a specific
weight.For example, in digital code, if number is 567 then weight of 5 is 100, weight of
6 is 10 and weight of 7 is 1. In weighted binary code each bit has a weight 8,4,2,1 and
each decimal digit is represented by a group of four bits.
Example: Binary, BCD
12. What is meant by reflective codes and non weighted codes?
A code is said to be reflective when the code for 9 is the complement ffor 0,
the code for 8 is complement for 1, 7 for 2, 6 for 3, and 5 for 4.
Example:2421, 5211 Excess -3 codes are reflective codes. The 8421 code is
not reflective.
Non weighted codes are not assigned with any eight to each digit position, i.e
each digit position within the number is not assigned fixed value.
Example: Gray code and Excess-3 code

13. What is meant by parity bit?

A parity bit is an extra bit included with a message to make the total number
of 1‟s transmitted either odd or even.
In even parity, the value of the parity bit is set such that the total number of
1‟s in the data word is even.
In odd parity, the value of parity bit is set such that the total number of 1‟s in
the data word is odd

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14. What are error detecting codes? Nov-07

When the digital information in the binary form is transmitted from one
circuit or system to another circuit or system an error may occur. This means a signal
corresponding to 0 may change to 1 or vice versa due to presence of noise. To
maintain the data integrity between transmitter and receiver,extra bit or more than
one bit are added in the data. These extra bits allow the detection and sometimes
correction of error in the data. The data along with the extra bit/bits forms the code.
Codes which allow only error detection are called error detecting codes and codes
which allow error detection and correction are called error detecting and correcting
codes.
Boolean Algebra and Theorems

15. Mention the various laws of Boolean algebra.

i) Commutative Law
(A+B)= (B+A)
(A.B)= (B.A)
ii) Associative Law
A+ (B+C) = (A+B) +C
(A.B).C=A. (B.C)
iii) Distributive Law
A+(B.C)= (A+B) (A+C)
A. (B+C) = (A.B) +(A.C)
16. State Commutative law of Boolean algebra.
1.The order in which the variables are OR-ed makes no difference in the output
(A+B)= (B+A)
2. The order in which the variables are AND-ed makes no difference in the output.
(A.B)= (B.A)

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Truth table: (A.B)= (B.A)

A B A.B B A B.A
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

17. State the associative law of Boolean algebra.

The associative property of Boolean algebra states that the OR ing of several
variables results in the same regardless of the grouping of the variables. The
associative property is stated as follows:
i) A+(B+C) = (A+B) +C
ii) (A.B).C=A. (B.C)
Truth table (A.B).C=A. (B.C)
A B C AB (AB)C A B C BC A(BC)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

18. State the distributive law of Boolean algebra.

The distributive property states that AND ing several variables and OR ing
the result with a single variable is equivalent to OR ing the single variable with each
of the the several Variables and then AND ing the sums.
The distributive property is: i)A+(B.C)= (A+B) (A+C)
ii)A.(B+C) = (A.B) + (A.C)

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Truth table: A.(B+C) = (A.B) + (A.C)

A B C B+C A(B+C) A B C AB AC AB+AC

0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1
1 1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1

19. Define DeMorgan’s theorem. May-03,04,11

De Morgan suggested two theorems that form important part of Boolean
algebra. They are,
1.The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'

A B (AB)‟ A‟+B‟
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

2. The complement of a sum term is equal to the product of the complements.

(A + B)' = A'B'

A B (A+B)‟ A‟.B‟
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

20. What is the principle of Duality theorem? Nov-02,03,09,10

The principles of duality says that starting with a Boolean relation, it is easy
to derive another Boolean relation by
 Changing each OR sign to an AND sign
 Changing each AND sign to an OR sign
 Complementing any 0 or 1 appearing in the expression

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Example: A+A‟=1,A.A‟=0
21. State consensus theorem in Boolean algebra.
In simplification of Boolean expression, an expression of the form
AB+A‟C+BC the term BC is redundant and can be eliminated to form the equivalent
expression AB-A‟C. The theorem used for this simplification is known as Consensus
theorem.
Example: AB+A‟C+BC=AB+A‟C

22. Simplify the Boolean function D=(A+B)(A+B’). May-11

Solution:

D=(A+B)(A+B‟)
=AA+AB+AB‟+BB‟
=A+AB+AB‟+BB‟
= A(1+B+B‟) [B.B‟=0]
=A.1
=A [B+B‟=1]

23. Prove that Z=A+A’B=A+B using Boolean algebra.

Solution:

Z=A+A‟B
=A+AB+A‟B [A+AB=A]
=A+B (A+A) [A+A‟=1]
=A+B
Boolean Functions
24. What do you meant by literal?
In Boolean function, the total number of variables in complemented or
uncomplemented form is called literals.
Example: The function F(A,B,C,D)=A+B‟C‟+ACD‟ contains 4 literals.
The function F(A,B)=AB‟ contains 2 literals.
The function F(X,Y)=XY+X‟Y‟ contains 2 literals.

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25. Mention the two basic types of Boolean expressions.

The two forms of Boolean expressions are:
i).Sum of Products Form (SOP)- It is defined as the group of product terms ORed
together consists of two or more product terms.
Y=AB+BC
ii).Product of Sum Form (POS)- It is defined as the group of sum terms ANDed
together consists of two or more sum terms.
Y=(A+B)(B+C)

26. What do you meant by standard SOP and POS forms.

A product term is any group of literals that are ANDed together. For example,
ABC, XY, and so on. A sum term is any group of literals that are ORed together such as
A +B + C, X + Y and so on. A sum of products (SOP) is a group of product terms ORed
together.
If each term in sum of product (SOP) form contains all the literals then the SOP
form is known as standard or canonical sum of products (SOP) form.
If each term in Product of sum (POS) form contains all the literals then the POS
form is known as standard or canonical product of sums (POS) form.

27. Mention the steps to convert POS to standard POS.

1.Find the missing literals in each sum term if any
2. OR each sum term having missing literals with terms form by ANDing the literal
and its complement
3. Expand the terms applying distributing law and reorder the literals in the
sum terms
4. Reduce the expression by omitting repeated sum if any because A.A=A

28. Convert the given expression in standard POS form.

f(A, B,C)=(A+B).(B+C)
Solution:

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f ( A, B, C )  ( A  B)  C.C  . ( B  C )  ( A. A) 

 ( A  B  C )(A  B C)( A  B  C )( A  B  C ) 

 ( A  B  C )( A  B  C )( A  B  C )

29. List the steps to convert SOP to standard SOP.

1. Find the missing literals in each product term if any
2. OR each product term having missing literals with terms form by OR ing the
literal and its complement
3. Expand the terms applying distributing law and reorder the literls in the sum terms
4. Reduce the expression by omitting repeated product if any because A+A=A

30. Convert the given expression in standard SOP form.

f(A, B,C)=AC+AB+BC
Solution:
Step 1: Finding missing literal in each product term
AC = Literal B is missing
AB = Literal C is missing
BC = Literal A is missing
Step 2: AND product term with (missing literal - its complement)
f (A, B, C ) = AC (B + B‟) + AB (C + C‟) + BC (A + A‟)
Step 3: Expand the terms and reorder literals
f (A, B, C) = ABC + AB‟C +ABC +ABC‟ + ABC +A‟BC
Step 4: Omit repeated product terms (allowing only one time):
f (A, B, C) = ABC + AB‟C +ABC + ABC‟ +ABC + A‟BC
f(A, B, C) = ABC + AB‟C + ABC‟ + A‟BC

31. Define Minterms and Maxterms.

Each individual term in standard SOP form is called min term and each
individual term in Standard POS form is called max term. The concept of min terms
and max terms allow us to introduce very convenient shorthand notations to express

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logical functions. Each minterm is represented by mi and each maxterm is

represented by Mi.
Example:Minterm:A‟B‟C‟
Maxterm:A+B+C

Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods

32. What is meant by Karnaugh map?

A Karnaugh map is a method of minimizing the Boolean function by a
systematic approach. K map is a pictorial form of truth table, in which the map
diagram is made up of squares, with each squares representing one minterm of the
function. It is of five types starting with one variable k-map,two variable k-map,3
variable k-map,4 variable k-map and five variable k-map.

33. Simplify the following Boolean function F using K-map method.

F(A,B,C)= Σm(0,1,3,,5,7) Nov-12

Solution:

F=C+A‟B‟

34. What is meant by don’t care conditions?

In some logic circuits, certain input conditions never occur; therefore the
corresponding output never appears. In such cases the output level is not defined, it
can be either HIGH or LOW. These output levels are indicated by „X‟ or „d‟ in the
truth tables and are called don‟t care outputs or don‟t care conditions or incompletely
specified functions. The Boolean function in which don‟t care outputs exists is called
incomplete Boolean function or incompletely specified functions.

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35. Distinguish between completely specified function and incompletely specified

function.

Completely Specified Function Incompletely Specified Function

All input conditions occur Certain input conditions never occur

Each output corresponding to input Outputs corresponding to non-occuring
conditions is defined input conditions are undefined
Each output has certain logical value, Undefined output doesn‟t have certain
either 0 or 1 logical value, but it is indicated by “x” or
“d” in truth table.

36. State the limitations of karnaugh map.

i)Generally it is limited to six variable map (i.e) more than six variable involving
expression are not reduced.
ii) The map method is restricted in its capability since they are useful for
simplifying only Boolean expression represented in standard form.
iii) the K map simplification is a manual technique and heavily depends on the
human abilities.
37. What is meant by Quine-McCluskey method of minimization?
For increased number of input variable K-Map method will be more
complex. So for that we can adopt Quine Mc-cluskey method. It is most effective
method which is used to simplify the Boolean functions. It is also called as the
Tabulation method. The fundamental principle is is that the minterms while binary
equivalent differ only in one place can be combined to reduce the minterms.

38. What is meant byprime implicant?

A prime implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map. If a min term is covered

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by only one prime implicant, the prime implicant is said to be essential. The sum
terms which appear in the k-map are called prime implicant groups.
All the implicants of a function determined using a Karnaugh map are called
prime implicants.

39. Mention the procedure for involved in QM method.

1.Find the prime implicants of the function.
2.Construct the prime implicant table and find the essential prime implicants of
the function.
3.Include the essential prime implicants in the minimal sum.
4.After all essential prime implicants are deleted from the prime implicant table,
determine the dominated rows and dominating columns in the tables, delete all
dominated rows and dominating columns and find the essential prime implicants.
5. Repeat step 3 and 4 as many times as they are applicable.

40. What do you meant by cyclic prime implicants?

A Prime implicant table is said to be semi cyclic if

1. It does not have any essential prime implicant ( essential row ), that is each
column contains at least two X‟s( don‟t cares)
2. NO dominance relation exists among rows and columns.
3. The costs of the rows are not the same.
o A semi cyclic prime implicant table is said to be cyclic if all the rows of that table
are of same cost.
o To solve such cases include any one of the rows to possible minimal sum and
proceed as if it were a normal case

41. Mention the advantages and disadvantages of Quine McCluskey method.

The Quine McCluskey method of simplification can be applied to any
number of variables and is algorithmic in nature.
The simplification process of Quine – McCluskey becomes lengthy and time
consuming as number of variables increase; however the algorithm can be easily

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programmed to run on a computer to identify prime implicant and implicants of any

function.

Logic Gates
42. What is meant by logic gates?
The logic gate is an electronic circuit that has one or more input binary
variables but only one output. It is called logic gate because of it ability to operate on
a number of binary inputs to perform a logical function, i.e its output is a logical
function of inputs.
The three basic logic gates are
1. AND gate
2. OR gate
3. NOT gate

43. Why NAND and NOR gates are called universal gates?
NAND and NOR are the gates that can be used alone to generate remaining gates
such as NOT, AND and OR gates. Thus, with only any of the two gates we can
implement the logic circuit. Hence they are called as Universal gates.

NAND Gate:

NOR Gate:

44. Draw the logic diagram and truth table for OR gate.
OR Gate logic diagram:

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Truth table:

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

45. Draw the truth table for NAND and NOR gate.
NAND Gate: NOR Gate:

Truth table:

A B Output A B Output

0 0 1 0 0 1

0 1 1 0 1 0

1 0 1 1 0 0

1 1 0 1 1 0

46. How can a NAND gate be used as an inverter? May-04

A NAND gate can be used as an inverter by giving same input signal to both the
input terminal.

Truth Table:

A B Output

0 0 1

0 1 1

1 0 1

1 1 0

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47. What do you meant by shared term?

Sometime, it may happen that simplified output functions may have common
terms. The common terms which are implemented only once and used by more than one
functions to generate final output are called shared terms.
Sharing of the terms reduces product terms. Sharing of common terms reduce the
total number of gates.

48. Why digital circuits are more frequently constructed with NAND and NOR
gates than with AND and OR gates?
Digital circuits are frequently constructed with NAND and NOR gates due to
following reasons,
If any simple combinational circuit we want to build and we are not using
universal gates then we want several AND, OR and NOT gates. This demands
number of ICs, one for each type of gate.
By using universal gates it is possible to reduce number of ICs required to
implement combinational circuit.

49. Write short notes on negative and positive logic. Nov-09

The two voltage levels used to represent two logic states in digital logic are
called logic levels.
The system in which the higher of the two voltage levels represent a 1 and
the lower voltage represents a 0 is called a positive logic system.
Positive Logic HIGH=1(+5V)
LOW=0 (0V)
The system in which the lower of the two voltage levels represent a 1 and the
higher of the voltage represents a 0 is called a negative logic system.
Negative logic HIGH=0(+5V)
LOW=1(0V)
NAND and NOR Implementations.
50. What are the steps involved in designing NAND-NAND logic?

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The rules involved in obtaining the NAND-NAND logic diagram from a

Boolean function as follows.

5. Simplify the given Boolean function and express it in sum of product form.
6. Draw a NAND gate for each product term of the function that has two or more
literals. The inputs to each NAND gate are the literals of the term. This
constitutes a group of first level gates.
7. If Boolean function includes any single literal or literals draw NAND gate for
each single literal and connect corresponding literal as an input to the NAND
gates.
8. Draw a single NAND gate in the second level, with inputs coming from output
first level gates.
51. Implement EX-OR gate using only NAND gates.

52. What is meant by NOR-NOR implementation?

The NOR function is a dual of the NAND function. The Implementation of a
Boolean function with NOR-NOR logic requires that the function be simplified in
the product of sum form. In product of sum form, we implement all sum terms using
OR gates. This constitutes the first level. In the second level all sum terms are
logically AND ed using AND gate.

53. Mention the steps involved in designing NOR –NOR logic.

The rules involved in obtaining the logic diagram from a Boolean function are

 Simplify the given Boolean function and express it in product of sum form.

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 Draw a NOR gate for each sum term of the function that has two or more literals.
The inputs to each NOR gate are the literals of the term. These constitute a group
of first level gates.
 If Boolean function includes any single literal or literals, draw NOR gate for
each single literal and connect corresponding literal as an input to the NOR gate.
 Draw a single NOR gate in the second level, with inputs coming from output of
first level gates.

54. Implement the following Boolean function with NOR-NOR logic

Y=AC+BC+AB+D
Solution:
Step 1: Express Boolean function in POS form.
Using duality theorem we get
Y‟=(A‟+C‟)(B‟+C‟)(A‟+B‟)D‟
Step 2: Implement Boolean function with OR-AND logic

Step 3:Convert OR-AND logic to NOR-NOR logic

55. Implement EX-NOR gate using NOR gate only.

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56. What are the characteristics of digital IC’s?

The characteristics of digital IC‟s are:
1. Propagation delay
2. Power dissipation
3. Fan-in
4. Fan-out
5. Noise Margin
6. Operating temperature
7. Power supply requirements

57. Define Fan-In and Fan-Out.

Fan -in is the number of inputs connected to the gate without any degradation
in the voltage level.
Example: An eight input gate requires one unit load (UL) per input. It‟s fan-in is 8
Fan- out specifies the number of standard loads that the output of the gate can
drive without impairment of its normal operation.
The fan-out is the maximum number of inputs that can be connected to the
output of a gate, and is expressed by a number.

58. What is meant by Noise margin?

It is the maximum noise voltage added to an input signal of a digital circuit that
does not cause an undesirable change in the output of the circuit. Noise margin is
expressed in terms of volts.
High state Noise Margin=VOH-VIH
Low state Noise Margin=VIL-VOL

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59. Define propagation delay.

Propagation delay is the average transition delay time for the signal to
propagate from input to output when the signals change in value. It is expressed in
terms of ns.
The delays for a standard TTL gate are
tPHl=7ns
tPLH=11ns
Average propagation delay=(7+11)/2=9ns
60. What are tri-state gates and Mention the advantages of CMOS logic?

The tri-state configuration utilizes the high speed operation of the totem-
pole arrangement while permitting outputs to be wired-AND. It is called tri-state
TTL because it allows three possible output stages: HIGH, LOW and high-
impedance.
Advantages of CMOS logic
 It consumes less power.
 It can be operated at high voltages, resulting in improved noise immunity.
 Fan out is more
 Better noise margin

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16 Marks
1. State and prove the fundamental laws of Boolean algebra. (16)
Fundamental laws of Boolean algebra:
a. Commutative law
b. Associative law
c. Distributive law
Commutative law:
1.The order in which the variables are OR-ed makes no difference in the output

(A+B)= (B+A)

A B A+B B A B+A
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1

2. The order in which the variables are AND-ed makes no difference in the output.

(A.B)= (B.A)

A B A.B B A B.A
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

Associative Law:
i)The associative property of Boolean algebra states that in the OR ing of several variables
results in the same regardless of the grouping of the variables.
A+(B+C) = (A+B) +C

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A B C A+B (A+B)+C A B C B+C A+(B+C)

0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 1 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 0 0 0 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

ii) The associative law of multiplication states that it makes no difference in what order the
variables are grouped when AND ing several variables.
(A.B).C=A. (B.C)
A B C AB (AB)C A B C BC A(BC)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

Distributive Law :
The distributive property states that AND ing several variables and OR ing the result
with a single variable is equivalent to OR ing the single variable with each of the the several
variables and then AND ing the sums.
i)A+BC= (A+B) (A+C)
The distributive law states that ORing several variables and AND ing the result with
a single variable is equivalent to AND ing the result with a single variable with each of the
several variables and ORing the products.
ii)A.(B+C) = (A.B) + (A.C)

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A B C B+C A(B+C) A B C AB AC AB+AC

0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 0 1 1 0 0 0
1 0 0 0 0 0 0 0
1 0 0
1 0 1 1 1
1 0 1 0 1 1
1 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1
1 1 1 1 1 1

DeMorgan’s theorem:De Morgan suggested two theorems that form important part of
Boolean algebra.
,
1.The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
Truth Table:
A B (AB)‟ A‟+B‟
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

2. The complement of a sum term is equal to the product of the complements.

(A + B)' = A'B'

A B (A+B)‟ A‟.B‟
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

2. Subtract the number (1110)-(1010) using 1’s and 2’s complement method.
Nov-03
Solution:
X=1110
Y=1010

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1’s complement
1‟s complement of Y =0101
X=1110
Sum=1 0011
End around carry= 1
0100
2’s complement
1‟s complement of Y =0101
1
2‟s complement of Y = 0110
X= 1110
1 0100
Carry discarded
(1110)-(1010)=(0100)2

ii)Perform (147-89) using 2’s complement binary arithmetic. May-11 (10)

Solution:
Binary equivalent of (89)10= 0 1 0 1 1 0 0 1

1‟s complement of (89)10= 1 0 1 0 0 1 1 0

Add1= 1

2‟s complement of (89)10= 10100111

Binary equivalent of (147)10=0 1 0 0 1 0 0 1 1

2‟s complement of (89)10= 1 10100111

1000111010

Discard carry
(147-89)=( 0 0 0 1 1 1 0 1 0)2

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3. a). Reduce XY +(XZ)' + XY’Z (XY + Z) (8)

Solution:

=XY + (XZ)' + XY‟Z (XY + Z)

= XY +(XZ)' +XXY'YZ +XY'ZZ
= XY + (XZ)' + XY'ZZ [X.X' = 0]
= XY +(XZ)' + XY'Z [X.X = X]
= XY + X' + Z' =XY'Z [(XY)' = X' + Y']
= X' + Y + Z' +XY'Z [X + XY' = X +Y]
= X' +Y'Z + Y + Z' [X + X'Y = X + Y]
= X' +Y +Z' + Y'Z =X' +Y +Z' + Y' =X' + Z' + 1
=1 [X + 1 =1]

b) Simplify the following expression Y = (X + Y) (X +Z’) (Y' + Z’) (8)

Solution:

Y = (X + Y) (X‟ +Z) (Y' +Z‟)

= (XX' + XZ +X'Y +YZ) (Y' + Z') [X.X' = 0]
= (XZ +X'Y + YZ) (Y' +Z‟)
= XY'Z +XZZ' +X'YY' +X'YZ' + YY'Z + YZZ'
= XY'Z + X'YZ'

4. a). Show that (X + Y' +XY) (X + Y') (X'Y) = 0 (8)

Solution:
=(X + Y' + XY)(X+ Y')(X'Y)
= (X + Y' + X) (X + Y‟) (X' + Y) [A + A'B = A + B]
= (X +Y‟) (X + Y‟) (X'Y) [A + A = A]
= (X +Y‟) (X'Y) [A.A = 1]
= X.X' +Y'.X'.Y = 0 [A.A' = 0]

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b) Prove that ABC +ABC' +AB'C + A'BC = AB +AC + BC (8)

Solution:
=ABC + ABC' + AB'C + A'BC
=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A(B + B'C)+ A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB+ AC +BC
ABC + ABC' + AB'C +A'BC = AB + AC + BC hence it‟s proved

5. Convert the given expression in standard POS form. (16)

(i) F(A,B,C)=(A+B).(B+C) Nov-07
1.Find the missing literals in each sum term if any
F(A,B,C)=(A+B).(B+C)
2. OR each sum term having missing literals with terms form by ANDing the literal
and its complement
F(A,B,C)=[(A+B)+(C.C‟)].[(B+C)+(A.A‟)]
3. Expand the terms applying distributing law and reorder the literals in the
sum terms
F(A,B,C ) =(A+B+C)(A+B+C‟)(A+B+C)(A‟+B+C)
4. Reduce the expression by omitting repeated sum
F(A,B,C )=(A+B+C)(A+B+C‟)(A‟+B+C)

(ii) F(A,B,C)=(A+B)(A+C)(B+C’) May-08

1.OR sum term of missing literal
F(A,B,C)=(A+B+(C.C‟))(A+C+(B.B‟))(B+C‟+(A.A‟))
2.Expand the terms and reorder literals.
F(A,B,C)=(A+B+C)(A+B+C‟)(A+B+C)(A+B‟+C)(A+B+C‟)(A‟+B+C‟)

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3. Omit repeated sum terms

F(A,B,C)=(A+B+C)(A+B+C‟)(A+B‟+C)(A‟+B+C‟)

(iii)F(A,B,C)=(A+B’)(B+C)(A+C’) Nov-08
1. OR each sum term having missing literals with terms form by ANDing the literal
and its complement.
F(A,B,C)=(A+B‟)+(C.C‟))(B+C+(A.A‟))(A+C‟+(B.B‟))
2. Expand the terms and reorder literals.
F(A,B,C)=(A+B‟+C)(A+B‟+C‟)(A+B+C)(A‟+B+C)(A+B+C‟)(A+B‟+C)
3. Reduce the expression by omitting repeated sum.
F=(A+B‟+C)(A+B‟+C‟)(A+B+C)(A‟+B+C)(A+B+C‟)

6. a) Reduce the following function using Karnaugh map Technique.

f ( A, B, C, D)   m(5,6,7,12,13)   d (4,9,14,15) May -09 (8)

Solution:

f ( A, B, C, D)  B

b) Minimize the following expression using Karnaugh map. May-11 (8)

Y=A’BC’D’+A’BC’D+ABC’D’+AB’C’D+A’B’CD’

Solution:

A‟BC‟D‟-0100

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A‟BC‟D-0101

ABC‟D‟-1100

AB‟C‟D-1001

A‟B‟CD‟-0010

Y=A‟B‟CD‟-A‟BC‟+BC‟D‟+AB‟C‟D

7. Simplify the following Boolean function F using K-map method. Nov-11(16)

i) F(A,B,C,D)= Σm(1,4,5,6,12,14,15)

Solution:

F=BD‟+A‟C‟D+ABC

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ii) F(A,B,C,D)= Σm(0,1,2,4,5,7,11,15)

F=A‟C‟-A‟BD+A‟B‟D‟+ACD

iii) F(A,B,C,D)= Σm(2,3,10,11,12,13,14,15)

F=AB+B‟C

8. (i) Find the prime implicants for the following function and determine which are
essential. F(w,x,y,z)= Σ (0,2,4,5,6,7,8,10,13,15) Nov-08,11 2-51 (8)

Solution:

The minterms of the given function are marked with 1‟s in the map. Fig 1 shows two
essential prime implicants. The term xz is essential because because there is only one
way to include minterms m13 and m15 within four adjacent squares. Similarly thereis
only one way that minterms m8 and m10 can be combined with four adjacent squares and

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this gives second term x‟z‟. the two essential prime implicants cover eight minterms.
The remaining two minterms m4 and m6 must be considered next.

Fig-1 Essential prime implicants x‟z‟ and xz

Fig-2 Prime implicants w‟x and w‟z‟

Fig 1 and 2 shows that the two ways of including remaining minterms with
prime implicants. Minterms m4 and m6 can be included with either w‟x and w‟z‟.
the simplified expression is obtained from the logical sum of the two essential prime
implicants and any one prime implicant that includes minterms m4 and m6. Thus
there are two possible ways that the function can be expressed in the simplified form

F=x‟z‟+xz+w‟x

=x‟z‟+xz+w‟z‟

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(ii) Find the reduced SOP form of the following function.

f(A,B,C,D)= Σm(1,3,7,1,15)+Σd(0,2,4) May-10 (8)

Solution:

F(A,B,C,D)=A‟B‟+CD

9. (i)Reduce the following function using K-map technique.

F(A,B,C,D)=(0,3,4,7,8,10,12,14)+d(2,6) Nov-09 (8)

Solution:

F(A,B,C,D)=D.(A+C‟)

(ii)Simplify using K-map to obtain a minimum POS expression. May-04 (8)

(A’+B’+C+D)(A+B’+C+D)(A+B+C’+D’)(A+B+C+D’)(A+B+C’+D)

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Y=(B‟+C+D)(B+C+D‟)(A+B+C‟)

10. a)Apply branching method to simplify the following function (6)

F ( A, B, C , D, E )   M (0,1, 4,5,9,11,13,15,16,17, 25, 27, 28, 29,31) 

d (20, 21, 22,30)

Solution:

E=0

E=1

F=(C+A)(A‟+D‟)(A‟+B‟+E‟)

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b) Simplify the following switching function using Karnaugh Map.

f ( A, B,C, D)   (0,5,7,8,9,10,11,14,15)   (1, 4,13) Dec-03 (10)

Solution:

f ( A, B,C, D)  AC  BD  AC  AB

11. Simplify the following Boolean function by using a Quine McCluskey method.
F(A,B,C,D) = Σm(0,2,3,6,7,8,10,12,13). (16)

Solution:

Step 1: List all minterms in the binary form and Arrange the minterms according to the
numbers of 1s.

Minterms Binary representaion Minterms Binary representaion

m0 0000 m0 0000

m2 0010 m2 0010

m3 0011 m8 1000

m6 0110 m3 0011

m7 0111 m6 0110

m8 1000 m10 1010

m10 1010 m12 1100

m12 1100 m7 0111

m13 1101 m13 1101

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Step 2: Compare each binary number with every term in the adjacent next higher category
and if they differ only by one position put a check mark‟-„.

Minterms Binary Minterms Binary

representaion representaion

0,2 00-0 0,2,8,10 -0-0

0,8 -000 2,3,6,7 0-1-

2,3 0001-

2,6 0-10

2,10 -010

8,10 10-0

8,12 1-00

3,7 0-11

6,7 011-

12,13 110-

Step 3: List the prime implicants.

Prime implicants Binary representation

AC‟D‟ 8,12 1-00

ABC‟ 12,13 110-

B‟D‟ 0,2,8,10 -0-0

A‟C 2,3,6,7 0-1-

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Step 4: Select the minimum number of prime implicants which cover the minterms.

Prime implicants m0 m2 m3 m6 m7 m8 m10 m12 m13

AC‟D‟ 8,12 . .

ABC‟
12,13

B‟D‟
0,2,8,10

A‟C
2,3,6,7

Thus the simplified expression from the tabulation method which is obtained from the prime
implicant selection chart is
F(A,B,C,D) = ABC‟+B‟D‟+A‟C.

12. Minimize the expression using Quine McCluskey method. (16)

Y=A’BC’D’+A’BC’D+ABC’D’+ABC’D+AB’C’D+A’B’CD’

Solution:

Step 1: List all minterms in the binary form and Arrange the minterms according to
the numbers of 1s.

Minterms Binary representaion Minterms Binary representaion

m4 0100 m2 0010

m5 0101 m4 0100

m12 1100 m5 0101

m13 1101 m9 1001

m9 1001 m12 1100

m2 0010 m13 1101

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Step 2: Compare each binary number with every term in the adjacent next higher
category and if they differ only by one position put a check mark‟-„.

Minterms Binary representaion Minterms Binary representaion

4,5 4,5,12,13 -1 0-
010-

4,12
-100

5,13
-101

9,13 1-01

12,13
110-

Step 3: List the prime implicants.

Prime implicants Binary representations

A‟B‟CD‟ 2 0010

AC‟D 9,13 1-01

BC‟ 4,5,12,13 -10-

Step 4: Select the minimum number of prime implicants which cover the minterms.

Prime implicants M2 M4 M5 M9 M10 M12 M13

A‟B‟CD‟
2

AC‟D
9,13

BC‟
4,5,12,13

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Thus the simplified expression from the tabulation method which is obtained from
the prime implicant selection chart is

Y= A‟B‟CD‟+AC‟D+BC‟.

13. Simplify the following Boolean expression using Quine McCluskey method
F= Σm(0,9,15,24,29,30)+d(8,11,31). Nov-09 (16)
Solution:

Step 1: List all minterms in the binary form and Arrange the minterms according to the
numbers of 1s.

Minterms Binary Minterms Binary

representaion representaion

m0 00000 m0 00000

m9 01001 dm8 01000

m15 01111 m9 01001

m24 11000 m24 11000

m29 11101 dm11 01011

m30 11110 m15 01111

dm8 01000 m29 11101

dm11 01011 m30 11110

dm31 11111 dm31 11111

Step 2: Compare each binary number with every term in the adjacent next higher
category and if they differ only by one position put a check mark‟-„.

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Minterm Binary Representation

0,8 0-000
8,9 0100-
8,24 -1000

9,11 010-1
11,15 01-11
15,31 -1111
29,31 111-1
30,31 1111-

Step 3: Select the minimum number of prime implicants which cover the minterms.

Prime implicants m0 m9 m15 m24 m29 m30 dm8 dm11 dm31

A‟C‟D‟E‟
0,8

A‟BC‟D‟ 8,9 . .

BC‟D‟E‟
8,24

A‟BC‟E
9,11

A‟BDE
11,15

BCDE 15,31 . .

ABCE
29,31

ABCD
30,31

F(A,B,C,D,E)=A‟C‟D‟E‟+BC‟D‟E‟+A‟BC‟E+A‟BDE+ABCE+ABCD

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14. Obtain the minimum SOP using Quine McCluskey’s method

F=m0+m2+m4+m8+m9+m10+m11+m12+m13. (16)

Solution:

Step 1: List all minterms in the binary form and Arrange the minterms according to the
numbers of 1s.

Minterms Binary representation Minterms Binary representation

m0 0000 m0 0000

m2 0010 m2 0010

m4 0100 m4 0100

m8 1000 m8 1000

m9 1001 m9 1001

m10 1010 m10 1010

m11 1011 m12 1100

m12 1100 m11 1011

m13 1101 m13 1101

Step 2: Compare each binary number with every term in the adjacent next higher
category and if they differ only by one position put a check mark‟-„.

Minterms Binary representation Minterms Binary representation

0,2 00-0 0,2,8,10 -0-0

0,4 0-00 0,8,4,12 --00

0,8 -000 8,9,10,11 10--

2,10 -010 8,9,12,13 1-0-

4,10 -100

8,9 100-

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8,12 -100

8,10 10-0

9,11 10-1

9,13 1-01

10,11 101-

12,13 110-

Step 3: List the prime implicants.

Prime Implicants Binary representation

9,13 AC‟D 10-1

8,9,12,13 AC‟ 1-0-

0,2,8,13 B‟D‟ -0-0

0,8,4,12 C‟D‟ --00

8,9,10,11 AB‟ 10--

Step 4: Select the minimum number of prime implicants which cover the minterms.

Prime implicants m0 m2 m4 m8 m9 m10 m11 m12 m13

AC‟D 9,13 . .

AC‟
8,9,12,13

B‟D‟
0,2,8,13

C‟D‟
0,8,4,12

AB‟
8,9,10,11

F (A, B, C, D) =C‟D‟+AC‟+AB‟+B‟D‟

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15. Simplify the following using tabulation method. (16)

Y(w,x,y,z)= Σm(1,2,3,5,9,12,14,15) + Σd(4,8,11).

Solution:

Step 1: List all minterms in the binary form and Arrange the minterms according to the
numbers of 1s.

Minterms Binary representation Minterms Binary representation

m1 0001 m1
0001

m2 0010 m2 0010

m3 0011 m4 0100

m5 0101 m8 1000

m9 1001 m3
0011

m12 110 m5 0101

m14 1110 m9 1001

m15 1111 m12 1100

dm4 0100 m11

1011

dm8 1000 m14 1110

dm11 1011 m15

1111

Step 2: Compare each binary number with every term in the adjacent next higher category
and if they differ only by one position put a check mark‟-„.

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Minterms Binary representation Minterms Binary representation

1,3 1,3,9,11 -0-1

00-1
1,5
0-01
1,9
-001
2,3
001-
4,5
010-
4,12
-100
8,9
100-
8,12
1-00

3,11
-011

9,11
10-1
12,14
11-0
11,15 1-11
14,15 111-

Step 3: List the prime implicants.

Prime implicants Binary representation

A‟C‟D 1,5 0-01

A‟B‟C 2,3 001-

A‟BC‟ 4,5 010-

BC‟D‟ 4,12 -100

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AB‟C‟ 8,9 100-

ACD‟ 8,12 1-00

ABD‟ 12,14 11-0

ACD 11,15 1-11

ABC 14,15 111-

B‟D 1,3,9,11 -0-1

Step 4: Select the minimum number of prime implicants which cover the minterms.

Prime implicants m1 m2 m3 m4 m5 m8 m9 m11 m12 m14 m15

A‟C‟D
T 1,5

A‟B‟C
2,3

A‟BC‟ 4,5 . .

BC‟D‟ 4,12 . .

AB‟C‟ 8,9 . .

ACD‟ 8,12 . .

ABD‟
12,14

ACD 11,15 . .

ABC
14,15

B‟D
1,3,9,11
t
Thus the simplified expression from the tabulation method which is obtained from
the prime implicant selection chart is

Y=A‟C‟D+A‟B‟C+ABD‟+ABC+B‟D.

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16. Draw the logic symbol and truth table for the following logic gates. (16)

Solution:

The logic gate is an electronic circuit that has one or more input binary
variables but only one output. It is called logic gate because of it ability to operate on
a number of binary inputs to perform a logical function, i.e its output is a logical
function of inputs.

OR Gate:

Truth table:

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
AND gate:

Truth table:

A B A.B
0 0 0
0 1 0
1 0 0
1 1 0

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NAND Gate:

Truth table:

A B Output
0 0 1
0 1 1
1 0 1
1 1 0

NOR gate:

Truth table:

A B Output
0 0 1
0 1 0
1 0 0
1 1 0

NOT gate:

Truth table:

A Output
0 1
1 0

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EX-OR gate:

Truth table:

A B Output
0 0 0
0 1 1
1 0 1
1 1 0

EX-NOR gate:

Truth table:

A B Output
0 0 1
0 1 0
1 0 0
1 1 1

17. i)Simplifythe following Boolean function using K-map.

F(x,y,z)= Σ(1,2,3,4,5,7) May-10 (6)

Solution:

F=XY‟+Z+Y‟Z

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ii)Implement the following Boolean function with NAND –NAND logic

Y=AC+ABC+A’BC+AB+D May-11 (10)

Solution:
Step 1: Simplify the given Boolean function

Y=AC+ABC+A‟BC+AB+D
=AC+BC(A+A‟)+AB+C
=AC+BC+AB+D
Step 2: Implement using AND-OR logic

Step 3:Convert AND-OR logic to NAND-NAND logic

18. a) Using K map simplify the following expressions and implement the same using
Basic gates. F= Σ(1,3,4,6) (8)

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Solution

Step 1: Enter the given minterms in the corresponding k map.

Step 2: The entered k map as to be grouped based on the system 2n

Step 3 : Based on the grouping the expression as been written for each grouping.

Step 4 : Hence by combining all the individual terms we get the final simplified
expression.

K-map:

F=A‟B+AB‟

Logic diagram:

b) Implement the following Boolean function with NAND-NAND logic.

F=(A,B,C)= Σm(0,1,3,5). (8)

Step 1:Simplify the given Boolean function

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F=A‟B‟+A‟C+B‟C

Step 2: Implement Boolean function with AND-OR logic

Step 3: Convert AND-OR logic to NAND-NAND logic

19. Minimize the following using k map and implement the resultant function using
NOR gate only. F(A,B,C,D,E) = Πm(2,4,7,9,26,38,29,31). (16)

Solution:

Step 1: Enter the given minterms in the corresponding k map.

Step 2: The entered k map as to be grouped based on the system 2n i.e ( numbers of
1,2,4,8….)
Step 3 : Based on the grouping the expression as been written for each grouping.
Step 4 : Hence by combining all the individual terms we get the final simplified
expression..
For this type i.e for 5 variable k map two k- map as to be considered and the grouping
was made based on the adjacent cell comparing both the k map.

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A=0

A=1

F=(A+B+C‟+D+E)(A+B+C‟+D‟+E‟)(A+B+C+D‟+E)(A+B‟+C+D+E‟)(A‟+B‟+C‟+D)

(A‟+B‟+C‟+E‟)(A‟+B‟+C+D‟+E).

Logic diagram:

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20. a)State the fundamental postulates of Boolean algebra. (8)

The postulates of a mathematical system form the basic assumption from which it is
possible to deduce the theorems, laws and properties of the system.
 Closure with respect to the operator . (dot) : When two binary elements are operated
by operator . (dot), the result is a unique binary element.
 Closure with respect to the operator +: When two binary elements are operated by
operator + the result is a unique binary element.
 An identity element with respect to +, designated by 0:
A+0=0+A=A
 An identity element with respect to . (dot), designated by 1:
A.1=1.A=A
 Commutative with respect to + : A + B = B + A
 Commutative with respect to . (dot) : A . B = B . A
 Distributive property of . (dot) over + :
A . (B + C) = (A . B) + (A . C)
 Distributive property of + over . (dot) :
A + (B . C) = (A + B) . (A + C)
 Associative property of + : A + (B + C) = (A + B) + C
 Associative property of . : A . (B . C) = (A .B) . C
 For every binary element, there exists complement element. For example, if A
is an element, we have A‟ is a complement of A i.e., if A = 0, then A‟ = 1 and vice
versa.
 There exist at least two elements, say A and B in the set of binary elements
such that A is not equal to B.

b) Explain the advantages of CMOS logic. (8)

CMOS has been and will remain the dominant technology is almost all VLSI design
areas.This is a direct result of the following advantages offered by CMOS processes.
 Low power consumption: CMOS process provides lower power consumption and is easy
to scaling down.

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 High input impedance: Gate of MOS needs much lower driving current than base current
of bipolar.
 Reduced silicon area: Scaling down increases the CMOS speed and reduces the area of the
chip.
 Mature technology: CMOS processes are well established and continue to become more
mature. The powerful trust by leading edge digital memory and processors has led to
continuous improvement and down scaling of CMOS processes.
 Design resources: Circuit and system design in CMOS is supported by a vast number of
resources. Many design techniques and design libraries for analog and digital design are
available.

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