Lab Viva Questions: Design of JK Flip-
Flop and D Flip-Flop Using JK Flip-Flop
A. Basic Viva Questions
B. Intermediate Viva Questions
C. Advanced Viva Questions
• 1. What is a JK Flip-Flop?
A: A JK flip-flop is a sequential logic circuit that has two inputs (J and K), one clock input,
and two outputs (Q and Q̅ ). It can set, reset, toggle, or hold the output based on input values.
• 2. What is the truth table of a JK Flip-Flop?
A: If J=0, K=0 → No Change; J=0, K=1 → Reset; J=1, K=0 → Set; J=1, K=1 → Toggle.
• 3. What is toggling in a JK Flip-Flop?
A: When both J and K are 1, the output changes state (Q becomes Q̅ ) at every clock pulse.
• 4. What is the characteristic equation of a JK Flip-Flop?
A: Q(next) = J·Q̅ + Q·K̅̅
• 5. What is a D Flip-Flop?
A: A D Flip-Flop is a circuit where the output Q follows the input D at the clock edge (Q = D).
• 6. What is the main difference between a JK and D Flip-Flop?
A: JK Flip-Flop has toggle functionality, while D Flip-Flop always stores the value of D at
clock edge.
• 7. How can you convert a JK Flip-Flop into a D Flip-Flop?
A: By connecting J = D and K = D̅.
• 8. What is the function of the clock in flip-flops?
A: It synchronizes the input and output changes to occur only on a clock transition.
• 9. What IC is used for JK Flip-Flop in lab?
A: IC 7476 – Dual JK Master-Slave Flip-Flop with preset and clear.
• 10. What is the timing diagram of a JK Flip-Flop?
A: A graphical representation showing how the output Q responds to different input
conditions (J, K) over clock cycles.
• 11. Why is the JK Flip-Flop preferred over the SR Flip-Flop?
A: JK Flip-Flop resolves the undefined state issue of SR when S=R=1 by toggling instead.
• 12. What is the role of preset and clear in IC 7476?
A: Preset sets Q to 1 regardless of input; Clear resets Q to 0 regardless of input.
• 13. What happens when clock is low in edge-triggered JK Flip-Flop?
A: The output does not change; it remains latched until a clock rising edge.
• 14. Can a JK Flip-Flop be used as a frequency divider?
A: Yes, when configured to toggle, it divides the clock frequency by 2.
• 15. How do you test a JK Flip-Flop circuit in the lab?
A: Apply all input combinations (J, K), observe output Q on clock edge using LED or logic
probe.
• 16. What are race conditions in flip-flops?
A: When output changes multiple times within one clock cycle due to feedback delay; mostly
seen in level-triggered flip-flops.
• 17. How can D Flip-Flop remove the problem of toggling?
A: Since it only stores D, it avoids multiple transitions in one cycle.
• 18. Why is D Flip-Flop called a 'data' flip-flop?
A: Because it simply stores the data input D on the clock edge.
• 19. What happens if J = 1 and K = 1 continuously?
A: The flip-flop toggles on each clock pulse.
• 20. Can we implement SR, T, and D Flip-Flops using JK Flip-Flop?
A: Yes, all flip-flops can be derived from the JK Flip-Flop with proper input configuration.