Introduction to FPGA Design Using MATLAB and Simulink
Eric Cigan MathWorks
Jordon Inkeles Altera
2011 The MathWorks, Inc. 1
Separate Views of FPGA Design
System Designer FPGA Designer
Algorithm Design
Fixed-Point Timing and Control Logic Architecture Exploration Algorithms / IP
System Test Bench
Environment Models Analog Models Digital Models Algorithms / IP
RTL Design
IP Interfaces Hardware Architecture
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Implement Design FPGA Requirements
Hardware Specification
Back Annotation
Synthesis
Map
Place & Route
Test Stimulus
FPGA Hardware
Model-Based Design for FPGAs
MATLAB and Simulink System and Algorithm Design
Algorithm Design
Fixed-Point Timing and Control Logic Architecture Exploration Algorithms / IP
System Test Bench
Environment Models Analog Models Digital Models Algorithms / IP
RTL Design
IP Interfaces Hardware Architecture
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Implement Design FPGA Requirements
Hardware Specification Place & Route Test Stimulus Synthesis Map
Back Annotation
FPGA Hardware
Model-Based Design for FPGAs
MATLAB and Simulink Algorithm and System Design
RTL Design
IP Interfaces
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Automatic HDL Code Generation
Hardware Architecture
RTL
Implement Design
Synthesis Map Place & Route
Back Annotation
FPGA Hardware
Model-Based Design for FPGAs
MATLAB and Simulink Algorithm and System Design
Verification
Behavioral Simulation
Automatic HDL Code Generation
Behavioral Cosimulation
Functional Simulation Static Timing Analysis Timing Simulation
RTL
Implement Design
Synthesis Map Place & Route
Back Annotation
FPGA Hardware
Model-Based Design for FPGAs
MATLAB and Simulink Algorithm and System Design
Verification
Automatic HDL Code Generation
Behavioral Cosimulation
Functional Simulation Static Timing Analysis Timing Simulation
RTL
Implement Design
Back Annotation Synthesis Map
Back Annotation
Implement Design
Synthesis
Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
Place & Route
FPGA Hardware
Model-Based Design for FPGAs
MATLAB and Simulink Algorithm and System Design
Automatic HDL Code Generation
Behavioral Cosimulation
RTL
Back Annotation
Implement Design
Synthesis
Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
FPGA Hardware
FPGA Hardware
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Model-Based Design with FPGA Workflows
MathWorks
HDL Coder
Altera
DSP Builder DSP Builder Advanced Blockset
HDL Coder
HDL code generation from MATLAB code, Simulink models, and Stateflow charts
Target-independent HDL code IEEE 1376 compliant VHDL IEEE 1364-2001 compliant Verilog
MATLAB, Simulink , Stateflow Algorithm and System Design
HDL Coder Link for ModelSim HDL Verifier
Verification
Generate HDL test bench Cosimulate with Mentor Graphics ModelSim or Cadence Incisive
Workflow integration
Integration with FPGA implementation tools
e.g., Quartus II
Optimize for area/speed Generate bit stream Back-annotation of timing to Simulink model
HDL
FPGA
Verify
ASIC
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Generate
Digital Down Converter
MATLAB/Simulink Algorithm Model
DDC accepts
A high sample rate passband signal (may be 50 to 100 Msps)
DDC produces
A low sample-rate baseband signal ready for demodulation
Fixed-Point Model
HW Implementation Model
HDL
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Fixed-Point Analysis
Digital Down Converter
Convert floating-point to fixed-point models
Automatic tracking of signal range (also intermediate quantities) Fraction lengths recommendation
Bit-true models in the same environment
Quantify the impact of fixed point quantization
Find and fix issues with fixed point easily
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Automatic HDL Code Generation
Digital Down Converter
Automatically generate bit true, cycle accurate HDL code from Simulink, MATLAB, and Stateflow
Full traceability between model and HDL code
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Simulink Library Support for HDL
HDL Supported Blocks
Over 170 blocks supported Core Simulink Blocks
Basic and Array Arithmetic, Look-Up Table, Signal Routing (Mux/Demux, Delay, Selector), Logic & Bit Operations, Dual and single port RAM, FIFO, CORDIC
Signal Processing Blocks
NCO, FFT, Digital Filters (FIR, IIR, Multi-rate, Adaptive), Rate Change (Up-/Down-sample), Statistics (Min/Max)
Communications Blocks
Psuedo-random Sequence Generator, Modulator / Demodulator, Interleaver / Deinterleaver, Viterbi Decoder
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MATLAB and Stateflow
HDL Supported Blocks
MATLAB Function Block
Subset of the MATLAB language for modeling and generating HDL implementations MATLAB Function Block Design Patterns for HDL
Stateflow
Tool for graphical modeling of Mealy / Moore finite state machines
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Use Cases for HDL Coder
System-level designers new to hardware design
Companies/design teams that have adopted Model-Based Design
MATLAB, Simulink , Stateflow Algorithm and System Design
HDL Coder Link for ModelSim HDL Verifier
Target-independent HDL is needed
Safety-critical applications (DO-254) Retargeting algorithm between software and hardware Model includes MATLAB code or Stateflow charts
HDL
FPGA
Verify
ASIC
Generate
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Altera DSP Builder
Generates HDL optimized for Altera FPGAs from Simulink
Key Optimizations
Silicon Architecture Aware Constraint Driven Design
Simulink Algorithm and System Design
Link forBuilder DSP ModelSim
Generate
Single Precision Double Precision
Verification
Generate HDL test bench Cosimulate with ModelSim
Altera FPGA FPGA
HDL HDL Altera ASIC HardCopy ASIC
Verify
Supports Floating Point
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Altera DSP Builder
Simulink
Sources Sinks Continuous Discrete Nonlinear Math
Altera DSP Builder Advanced Blockset Altera DSP Builder Blockset Fixed-Point Blockset DSP System Blockset Simulink Coder Communications System Blockset Image Acquisition Toolbox others
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Altera DSP Builder Design Flow
MATLAB / Simulink (System simulation and verification)
HDL / Hardware Domain ( Hardware implementation / RTL simulation)
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Constraint-Driven Design (1)
1. Choose your type Fixed or Floating Point
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Constraint-Driven Design (2)
2. Create Model
Use ModelIP or ModelPrim libraries
ModelIP
ModelPrim
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Constraint-Driven Design (3)
3. Select Device
Device-independent modeling up to this level
Stratix II AUTO
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Constraint-Driven Design (4)
4. Set Frequency
Automatic pipelining or time sharing (ModelIP)
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Constraint-Driven Design (5)
5. Compile
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Math.h Functions
Math.h
- SIN - COS - TAN - ASIN - ACOS - ATAN - EXP - LOG - LOG10 - POW(x,y) - LDEXP - FLOOR - CEIL - FABS - SQRT - DIVIDE - 1/SQRT
Implemented in Floating Point
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Complex Functions Easily Realized in FPGA
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Supports Single and Double Precision
Including complex (c)
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Supports Fixed Point and Floating Point
Within the same model
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Loop Block for For i Loops
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Nested Looping Functionality
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Use Cases Summary
HDL Coder
Altera DSP Builder
System-level designers new to hardware design Companies that have adopted Model-Based Design Target-independent HDL needed Safety-critical applications
Hardware designers new to Model-Based Design Optimized for all Altera devices even ones we havent built yet Constraint driven for high performance designs
Retargeting algorithm between software and hardware
Model includes MATLAB code or Stateflow charts
Supports floating-point implementation
Supports integration into larger systems with Altera Qsys
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Next Steps
1.
Visit mathworks.com/fpga
Get free FPGA Design Information Kit
View webinar Accelerate FPGA Design Using Simulink HDL Coder
Request trial of HDL Coder
2.
Visit altera.com/dspbuilder
Technical resources Request trial
3.
Questions?
Write to [email protected]
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