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23 October 2024 Lab Class

Chapter 3 covers computer architecture, focusing on the central processing unit (CPU) and the Von Neumann architecture. Key topics include the components of the CPU, system buses, and the Fetch-Decode-Execute cycle. The chapter also outlines homework and test dates related to the material discussed.

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9 views16 pages

23 October 2024 Lab Class

Chapter 3 covers computer architecture, focusing on the central processing unit (CPU) and the Von Neumann architecture. Key topics include the components of the CPU, system buses, and the Fetch-Decode-Execute cycle. The chapter also outlines homework and test dates related to the material discussed.

Uploaded by

yiyadok303
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 3 Hardware 3 .

1 C O M P U T E R AR C H I T E C T U R E
CLASS NINE
2 3 O C T O B E R 2 0 2 4 , W E D N E S D AY
Course Outline

Lesson 3.1.1 The central processing unit - CPU

Lesson 3.1.2 Von Neumann architecture

Lesson 3.1.3 Cores, cache and internal clock

Lesson 3.1.4 Instruction set

Lesson 3.1.5 Embedded systems

TEACH A COURSE 2
First Lesson
We will cover the following:
▪ Concept of Von Neumann
Architecture
▪ Components of the central
processing unit –CPU
▪ System buses and memory
▪ Fetch-Decode-Execute Cycle

TEACH A COURSE 3
Von Neumann Architecture Features

▪ The concept of a central processing ▪ Stored programs were made up of


unit –CPU or processor. instructions which could be
executed in sequential order.
▪ The CPU was able to access the
memory directly.
▪ Computer memory could store
programs and data.

TEACH A COURSE 4
Basic Von Neumann Computer
Architecture Block Diagram 1

TEACH A COURSE 5
TEACH A COURSE 6
Register is a temporary memory component in the CPU which can be a general or specific
in its use; it holds data or instructions as part of the Fetch-Decode-Execute cycle.
Registers – Registers refer to high-speed storage areas in the CPU. The data processed by

Components the CPU are fetched from the registers. There are different types of registers used in
architecture :-
Accumulator: Stores the results of calculations made by ALU. It holds the intermediate of

▪ CPU arithmetic and logical operations. it acts as a temporary storage location or device.
Program Counter (PC): Keeps track of the memory location of the next instructions to be
▪ CONTROL UNIT
dealt with. The PC then passes this next address to the Memory Address Register (MAR).
▪ ARITHMETIC AND LOGIC UNIT
Memory Address Register (MAR): It stores the memory locations of instructions that need
▪ SYSTEM CLOCK to be fetched from memory or stored in memory.
▪ REGISTERS – CIR, Memory Data Register (MDR)/Memory Buffer Register (MBR): It stores instructions
ACC,MAR,MDR/MBR,PC,IR, fetched from memory or any data that is to be transferred to, and stored in, memory.
▪ SYSTEM BUSES AND MEMORY Current Instruction Register (CIR): It stores the most recently fetched instructions while it

▪ REFER TO Figure 3.1, 3.2 is waiting to be coded and executed.


Instruction Buffer Register (IBR): The instruction that is not to be executed immediately is
▪ Table 3.1
placed in the instruction buffer register IBR.
Immediate Access Store (IAS) : it is a memory that holds all data and programs needed to
be accessed by the control unit. It is similar to the functioning of RAM.

TEACH A COURSE 7
TEACH A COURSE 8
TEACH A COURSE 9
System Buses
Buses – Data is transmitted from one part of a computer to another, connecting all major internal components to
the CPU and memory, by the means of Buses. Types:
◦ Data Bus: It carries data among the memory unit, the I/O devices, and the processor.
◦ Address Bus: It carries the address of data (not the actual data) between memory and processor.
◦ Control Bus: It carries control commands from the CPU (and status signals from other devices) in order to control and
coordinate all the activities within the computer.

TEACH A COURSE 10
Diagram of System Buses

TEACH A COURSE 11
READ AND WRITE OPERATION

TEACH A COURSE 12
Fetch-Decode-Execute Cycle

TEACH A COURSE 13
Detailed Diagram of Von Neumann Architecture

TEACH A COURSE 14
Thank You!
HOMEWORK

Notice –
MCW – 28 October 2024, Monday on ONLY Section 3.1.1
and 3.1.2
Class Test 3 – 04 November 2024, Monday on whole of
Section 3.1
Read and Learn pages 75 to 87 – the sentences highlighted
in the class and the figures and tables

TEACH A COURSE 16

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