ECEN620: Network Theory

Broadband Circuit Design

Fall 2014

Lecture 3: PLL Analysis

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Agenda & Reading
• PLL Overview & Applications
• PLL Linear Model
• Phase & Frequency Relationships
• PLL Transfer Functions
• PLL Order & Type

• Reading
• Chapter 2, 3, 5, & 12 of Phaselock Techniques,
F. Gardner, John Wiley & Sons, 2005.
2
References
• M. Perrott, High Speed Communication Circuits
and Systems Course, MIT Open Courseware

• Chapter 2 of Phase-Locked Loops, 3rd Ed., R.

Best, McGraw-Hill, 1997.

• Chapter 2, 3, 5, & 12 of Phaselock Techniques, F.

Gardner, John Wiley & Sons, 2005.

3
PLL Block Diagram

[Perrott]

• A phase-locked loop (PLL) is a negative feedback system

where an oscillator-generated signal is phase AND
frequency locked to a reference signal

4
PLL Applications
• PLLs applications
• Frequency synthesis
• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation
• Phase aligning an internal clock to an I/O clock
• Clock recovery
• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation
• Wireless systems
• Spread-spectrum clocking

5
Forward Clock I/O Circuits
• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit
• DLL/PI
• Injection-Locked Oscillator

6
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

7
Linear PLL Model

• Phase is generally the key variable of interest

• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain operation in
lock range
8
Phase Detector

φref φe

φfb

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output, thus to characterize
phase detector gain, extract average output voltage (or current for
charge-pump PLLs)
9
Loop Filter
VDD

I
Charging VCO Control
Voltage

C1 C2
Discharging
I R
F(s)
VSS

• Lowpass filter extracts average of phase

detector error pulses
10
Voltage-Controlled Oscillator

KVCO
ω0 1

0 VDD/2 VDD

ω out (t ) = ω 0 + ∆ω out (t ) = ω 0 + K VCO vc (t )

• Time-domain phase relationship

Laplace Domain Model
φout (t ) = ∫ ∆ωout (t )dt = KVCO ∫ vc (t )dt

φout(t)

11
 Loop Divider

φout(t) φfb(t)

[Perrott]

• Time-domain model
ω fb (t ) = ωout (t )
1
N

φ fb (t ) = ∫ ωout (t )dt = φout (t )

1 1
N N
12
Phase & Frequency Relationships
Angular Frequency is the first derivative (rate of change vs time) of phase
dφ (t )
= ω (t )
dt
t
φ (t ) = ∫ ω (τ )dτ
o

Consider a sinusoid u1 (t ) with angular frequency ω1 (t ) and phase φ1 (t )

u1 (t ) = sin (ω1 (t )t + φ1 (t ))
[Best]
• Phase Step
φ1 (t ) = ∆Φu (t )
u1 (t ) = sin (ω1 (t ) + ∆Φu (t ))

No change in frequency
∆Φ

13
Phase & Frequency Relationships
• Frequency Step ω1 (t ) = ω0 + ∆ω
u1 (t ) = sin (ω0t + ∆ωt ) = sin (ω0t + φ1 (t ))

where φ1 (t ) = ∆ωt

A frequency step produces a ramp in phase

[Best]

φ1 (t ) = ∆ωt

14
 Phase & Frequency Relationships
•

• Frequency Ramp ω1 (t ) = ω0 + ∆ ω t

t   ∆
•
ω 
•
 
u1 (t ) = sin  ∫  ω0 + ∆ ω τ dτ  = sin ω0t + 2
t = sin (ω0t + φ1 (t ))
0     2 
 
•
∆ω 2
where φ1 (t ) = t
2
[Best] A frequency ramp produces a quadratic change in phase

•
ω0 ω0 + ∆ ω t

•
∆ω 2
φ1 (t ) = t
2
15
 Understanding PLL Frequency Response
• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain operation in
lock range
• Frequency domain analysis can tell us how well the PLL tracks the input
phase as it changes at a certain frequency
• PLL transfer function is different depending on which point in the loop
the output is responding to
Input phase response VCO output response

[Fischette]
16
Open-Loop PLL Transfer Function

Φ out (s ) K PD KVCO F (s )
G (s ) = =
Φ e (s ) s
• Open-loop response generally decreases with frequency
17
 Closed-Loop PLL Transfer Function

Forward Path Gain = G (s )

Φ out (s ) G (s ) K PD KVCO F (s )
Loop Gain
K PD KVCO F (s ) G (s ) H (s ) = = =
l1 = −
sN
=−
N Φ ref (s ) 1 + G (s ) s + K PD KVCO F (s )
Forward Path Determinant ∆1 = 1 − 0 = 1 N N
 G (s )  G (s )
System Determinant ∆ = 1 −  −
 N 
 + 0 =1+
N
• Low-pass response whose
overall order is set by F(s) 18
 PLL Error Transfer Function

Forward Path Gain = 1 Φ e (s ) 1 s

E (s ) = = =
Loop Gain Φ ref (s ) 1 + G (s ) s + K PD KVCO F (s )
K PD KVCO F (s ) G (s ) N N
l1 = − =−
sN N
Forward Path Determinant ∆1 = 1 − 0 = 1 • Ideally, we want this to be zero
 G (s )  G (s ) • Phase error generally increases with
System Determinant ∆ =1−  −  + 0 = 1+
 N  N frequency due to this high-pass response
19
PLL Order and Type
• The PLL order refers to the number of poles in the
closed-loop transfer function
• This is typically one greater than the number of loop
filter poles

• The PLL type refers to the number of integrators

within the loop
• A PLL is always at lease Type 1 due to the VCO
integrator

• Note, the order can never be less than the type

20
First-Order PLL

F (s ) = K1

K PD KVCO K1 NK DC
Forward Path Gain : G (s ) = =
s s
 sG (s )  K PD KVCO K1
DC Loop Gain Magnitude : K DC = lim =
s →0
 N 
• Simple first-order low-
N
Nω3dB
pass transfer function
K PD KVCO K1 NK DC
Transfer Function : H (s ) = = =
s + PD VCO 1 s + ω3dB s + K DC
K K K
N
K PD KVCO K1
• Closed-loop bandwidth Closed - Loop Bandwidth : ω3dB =
N
= K DC

is equal to the DC loop s s s

Error Function : E (s ) = = =
gain magnitude s + PD VCO 1 s + ω3dB s + K DC
K K K
N

21
First-Order PLL Tracking Response
• The PLL’s tracking behavior, or how the phase error responds to an input
phase change, varies with the PLL type
• Phase Step Response [Best]
φ1 (t ) = ∆Φu (t )
u1 (t ) = sin (ω1 (t ) + ∆Φu (t ))

No change in frequency
• The final value theorem can be used to find the steady-state phase error
 ∆Φ  ∆Φs
lim  ( sE (s )) = lim
s →0 s + K
=0
s →0
 s  DC

• All PLLs should have no steady-state phase error with a phase step error
• Note, this assumes that the frequency of operation is the same as the VCO
center frequency (Vctrl=0). Working at a frequency other than the VCO
center frequency is considered having a frequency offset (step).

22
 First-Order PLL Tracking Response
[Best]
• Frequency Offset (Step)
ω1 (t ) = ω0 + ∆ω
u1 (t ) = sin (ω0t + ∆ωt ) = sin (ω0t + φ1 (t ))

where φ1 (t ) = ∆ωt

A frequency step produces a ramp in phase

• The final value theorem can be used to find the steady-

state phase error
 ∆ω  ∆ω ∆ω
lim 2 (sE (s )) = lim =
s →0
 s 
s →0 s + K DC K DC

• With a frequency offset (step), a first-order PLL will lock

with a steady-state phase error that is inversely
proportional to the loop gain
23
First-Order PLL Issues
• The DC loop gain directly sets the PLL bandwidth
• No degrees of freedom

• In order to have low phase error, a large loop gain is

necessary, which implies a wide bandwidth
• This may not be desired in applications where we would like to filter
input reference clock phase noise

• First-order PLLs offer no filtering of the phase detector

output
• Without this filtering, the PD may not be well approximated by a
simple KPD factor
• Multiplier PDs have a “second-harmonic” term
• Digital PDs output square pulses that need to be filtered

24
Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter

Passive Lag-Lead Loop Filter

[Allen]

1 + sτ 2
F (s ) =
1 + s(τ 1 + τ 2 )

τ 1 = R1C τ 2 = R2C
25
 Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter
1 + sτ 2  τ  1
F (s ) = K K (1 + sτ 2 )
NK DC  2  s + 
1 + s(τ 1 + τ 2 ) Forward Path Gain : G (s ) = PD VCO =  τ 1 + τ 2  τ 2 
s(1 + s(τ 1 + τ 2 ))  1 
s s + 
τ 1 = R1C τ 2 = R2C  τ 1 + τ 2 

 sG (s )  K PD KVCO
DC Loop Gain Magnitude : K DC = lim =
s →0
 N  N
K PD KVCOτ 2  1  Nω n 
 s +  ωn  2ζ −  s + ωn2
τ1 + τ 2  τ 2   K PD KVCO 
Transfer Function : H (s ) = =N
 1 + K PD KVCOτ 2 N  K K s 2 + 2ζω n s + ωn2
s + 
2
 s + PD VCO
 τ1 + τ 2  N (τ 1 + τ 2 )
 τ  1
K DC  2  s + 
=N  τ 1 + τ 2  τ 2 
 1 + K DCτ 2  K
s 2 +   s + DC
 τ1 + τ 2  τ1 + τ 2
K PD KVCO
Natural Frequency : ωn =
N (τ 1 + τ 2 )
ωn  N 
Damping Factor : ζ = τ 2 + 
2  K PD KVCO 
 Nωn2 
s s + 
 K PD KVCO 
Error Function : E (s ) = 2
s + 2ζω n s + ωn2 26
Second-Order Type-1 PLL Tracking Response
• Phase Step Response
 Nωn2 
∆Φs s + 
 ∆Φ  PD VCO 
sE (s )) = lim 2 
K K
lim  ( =0
s →0
 s  s → 0 s + 2ζω n s + ωn2

Again, phase error should be zero with a phase step

• Frequency Offset (Step)

 Nωn2 
∆ω  s + 
 ∆ω  K PD KVCO  ∆ω
lim 2 (sE (s )) = lim 2  =
s →0
 s  s →0 s + 2 ζω n s + ω 2
n K DC

• A second-order type-1 PLL will still lock with a phase error if

there is a frequency offset!

27
Second-Order Type-1 PLL Properties
• While the second-order type-1 PLL will still lock
with a phase error with a frequency offset, it is
much more useful than a first-order PLL
• There are sufficient design parameters (degrees of
freedom) to independently set ωn, ζ, and KDC
• The loop filter conditions the phase detector
output for proper VCO control
• Loop stability needs to be considered for the
second-order system

28
Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter

Passive Series-RC Loop Filter

 1 
R s + 
F (s ) =  RC 
s

• Note, this type of loop filter is typically used with a charge-

pump driving it. Thus, the filter transfer function is equal
to the impedance.
29
 Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter
 1 
R s + 
 RC  DC Loop Gain Magnitude : K DC = ∞ (ideally)
F (s ) =
s
 1 
K PD KVCO R s + 
Forward Path Gain : G (s ) =  RC 
s2

 1   ωn 
K PD KVCO R s +  N 2ζω  s + 
 
n
 2ζ 
Transfer Function : H (s ) =
RC
= 2
K K R K K s + 2ζω n s + ωn 2
s 2 +  PD VCO  s + PD VCO
 N  NC

K PD KVCO
Natural Frequency : ωn =
NC
ωn
Damping Factor : ζ = RC
2
s2
Error Function : E (s ) =
s 2 + 2ζω n s + ωn2

30
Second-Order Type-2 PLL Tracking Response
• Phase Step Response
 ∆Φ  ∆Φs 2
lim (sE (s )) = lim
s → 0 s 2 + 2ζω s + ω 2
=0
s →0
 s  n n

Again, phase error should be zero with a phase step

• Frequency Offset (Step)

 ∆ω  ∆ωs
lim 2 (sE (s )) = lim 2 =0
s → 0 s + 2ζω s + ω 2
s →0
 s  n n

• A second-order type-2 PLL will lock with no phase error with

a frequency offset!

31
Second-Order Type-2 PLL Properties
• A big advantage of the type-2 PLL is that it has
zero phase error even with a frequency offset
• This is why type-2 PLLs are very popular

• A type-2 PLL requires a zero in the loop filter for

stability.
• Note, this is not required in a type-1 PLL

• This zero can cause extra peaking in the

frequency response
• Important to minimize this in some applications, such
as cascaded CDR systems

32
Next Time
• PLL System Analysis
• PLL Stability
• Noise Transfer Functions
• Transient Response

33