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Question Bank

The document is a comprehensive question bank focused on digital electronics and logic design. It includes various problems related to number conversions, Boolean algebra, Karnaugh maps, circuit design, and flip-flops. The questions cover a wide range of topics, providing a thorough assessment of knowledge in the field.

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kangirene9705
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9 views3 pages

Question Bank

The document is a comprehensive question bank focused on digital electronics and logic design. It includes various problems related to number conversions, Boolean algebra, Karnaugh maps, circuit design, and flip-flops. The questions cover a wide range of topics, providing a thorough assessment of knowledge in the field.

Uploaded by

kangirene9705
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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QUESTION BANK

DIGITAL ELECTRONICS AND LOGIC DESIGN

1. Develop the decimal equivalent of (1011100.10101)2.


2. Solve for the following operation (4A6 )16 + (1B3)16
3. Convert the binary number (11000110)2 to Gray code
4. Perform (13AF)16 to octal conversion
5. Convert the following binary number (1100101001010111)2 to hexadecimal and octadecimal
6. Solve using 2’s complement method 56 – 27
7. Convert the binary number 10111101.011 to decimal.
8. Apply Boolean algebra rules to simplify and prove the expression
9. Using a 4 variable K-map simplify,
f(A,B,C,D)=∑m(1,3,9,10,11,13,14)+d(2,5,15)
10. Realize the function using NAND gates only

11. Prove the following Boolean expression:


(A+B)(A ̅C ̅+C) ((B ̅+AC)) ̅=A ̅B
12. Develop the single error correcting code for the BCD number 1001using even Parity
13. Solve each of the following conversions
i) F4C16 to decimal
ii) 89410 to hexadecimal
iii) 74.12310 to binary
iv) 10111.10112 to decimal
v) 3468 to binary
14. Solve for the following operation (2B)16 + (84)16
15. Solve for 67-53 and 67+53 where 67 and 53 are BCD numbers.
16. Solve the following operation of BCD numbers.
a) 357-294 b)67+53
17. Perform the (58)16 + (22)16
18. Develop the signed magnitude form of +100 and -100 in 2’s complement form.
19. Develop the single-error correcting code for the information code 10110 for odd parity.
20. Perform the following conversions of the decimal number 215 to the following codes
(i) Binary (ii) BCD code (iii) Excess 3 code (iv) Gray code v) Octal

21. Simplify the following Boolean expression


22. Using K-map derive the reduced Boolean expression for the following function:
23. f(A, B, C,D) = ∑m(0,1,3,4,6,9,11) + d(2,5). Realize the function using NAND gates only.
24. Develop the canonical sum of product of the function: Y=AB+ACD
25. Develop the following functions in a canonical form
F(X, Y, Z) = (X+Y)(Y ̅+Z) in product of maxterms.
F(A, B, C)= A+B ̅C in sum of minterms
26. Design a 1 bit magnitude comparator and realize it using logic gates.
27. Construct a full adder circuit using logic gates.
28. Develop a circuit using NAND gates for implementing EXCLUSIVE-OR function
29. Draw the truth table and logic diagram for a Decimal to BCD Encoder.
30. Develop a code converter circuit for converting binary number to BCD number
31. Explain the architecture of Arithmetic Logic Unit with a neat diagram.
32. Solve the following functions using K-map
f (A,B,C,D)=∑▒m(0,1,3,7,15) + ∑▒〖d (2,11,12)〗
Implement the simplified function using basic gates.
33. Simplify the following expression using K map and realize the function using NAND gates
F (A, B, C, D) = ∑ m (1,3,7,9,8,10,12,14) + d (0,4,6,13)
34. Simplify the boolean expression

35. Reduce the expression F = πM (1,3,12,13,14) + d (2,4,5) and implement the real minimal
expression in universal logic.
36. Solve the following function using K mapping F= πM (2,8,9,10,11,12,14). and
implement using universal logic gates.
37. Develop the canonical sum of product of the function Y= AB+ACD.
38. Construct a Karnaugh map to minimize the standard POS expression:

39. Prove the following Boolean expression:


(A+B)(A ̅C ̅+C) ((B ̅+AC)) ̅=A ̅B
40. Design a 1 bit magnitude comparator and realize it using logic gates.
41. Construct a 2 bit magnitude comparator.
42. Draw the truth table of a full adder. Reduce it using K map. Implement it using NAND gates.
43. Implement a BCD to seven segment decoder.
44. Implement the function F(A,B,C,D) = ∑(0,1,3,4,8,9,15) using a suitable multiplexer.
45. Model the following function F(A,B,C,D)=∑m(0,1,3,4,8,9,15) using an 8 x 1 MUX.
46. Implement the function F(A, B, C) = ∑ m(2, 3, 6, 7) using a suitable multiplexer.
47. Design a gray to binary code converter and draw its logic diagram.
48. Develop a 3 to 8 decoder circuit.
49. Implement binary to grey code converter
50. Design a gray to binary code converter and draw its logic diagram.
51. Realize an S-R flip flop using nand gates.
52. Develop JK flipflop using D flipflop
53. Show the implementation of SR flipflop using D flipflop
54. Realize an S-R flip flop using nand gates.
55. Explain race around condition in JK flip flop.
56. Show the implementation of SR flipflop using D flipflop
57. Implement a 4:1 multiplexer using HDL.
58. Implement a half adder using HDL
59. Implement a full adder using HDL.
60. Implement the boolean expression F(A, B, C) = ∑ m(0, 2, 5, 6) using 4 : 1 multiplexer.
61. Implement a D flipflop using HDL.
62. Illustrate the working of 4-bit parallel in serial out shift register
63. Explain with a logic diagram a serial in parallel out shift register.
64. Illustrate the working of 4-bit serial in serial out shift register
65. Explain the working principle of a 4-bit Johnson counter.
66. Develop an asynchronous decade up counter with necessary diagram and waveform.
67. Develop a synchronous mod-5 counter by identifying the excitation table and implementing its
circuit diagram.
68. Develop synchronous up/down counter with necessary diagram and waveforms.
69. Construct a 3-bit asynchronous (ripple) counter using JK flip-flops and illustrate its operation
with a timing diagram
70. Compare Moore and Mealy machines
71. Explain any three types of PLD’s with necessary block diagram.
72. Construct a combinational circuit using a Programmable Logic Array (PLA) to implement the
given functions F1=∑m(3,5,7) and F2=∑m(4,5,7).
73. Implement the following Boolean functions using PLA.
A=XY+XZʹ
B=XYʹ+YZ+XZʹ
74. Explain the working of FPGA with necessary block diagram.
75. Compare Mealy and Moore type circuit with block level diagram.
76. Compare PAL and PLA.
77. Develop the state diagram of JK flipflop.
78. Develop a asynchronous up/down counter with necessary diagram and waveforms.
79. Develop the truth table and logic diagram for a Decimal to BCD Encoder.
80. Implement the following Boolean functions using PAL
A=XY+XZʹ
B=XYʹ+YZʹ
81. Explain the working of various Programmable logic devices with the help of neat diagrams.

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