The document is a question bank containing various tasks related to digital logic design and implementation. It includes designing comparators, decoders, flip-flops, counters, and multiplexers, as well as explaining concepts like FPGA and programmable logic devices. Additionally, it involves implementing functions using hardware description languages (HDL) and logic gates.
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Question Bank Cat2
The document is a question bank containing various tasks related to digital logic design and implementation. It includes designing comparators, decoders, flip-flops, counters, and multiplexers, as well as explaining concepts like FPGA and programmable logic devices. Additionally, it involves implementing functions using hardware description languages (HDL) and logic gates.
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Question Bank
1. Design a 1 bit magnitude comparator and realize it using logic gates.
2. Implement a BCD to seven segment decoder. 3. Develop a 3 to 8 decoder circuit. 4. Implement the function F(A, B, C) = ∑ m(2, 3, 6, 7) using a suitable multiplexer. 5. Implement the function F(A,B,C,D) = ∑(0,1,3,4,8,9,15) using a suitable multiplexer. 6. Implement binary to grey code converter 7. Design a gray to binary code converter and draw its logic diagram. 8. Realize an S-R flip flop using nand gates. 9. Develop JK flipflop using D flipflop 10.Show the implementation of SR flipflop using D flipflop 11.Illustrate the working of 4-bit parallel in serial out shift register 12.Illustrate the working of 4-bit serial in serial out shift register 13.Develop synchronous up/down counter with necessary diagram and waveforms. 14.Develop an asynchronous decade up counter with necessary diagram and waveform. 15.Compare Mealy and Moore type circuit with block level diagram. 16.Implement the following Boolean functions using PLA. A=XY+XZʹ B=XYʹ+YZ+XZʹ 17.Explain the working of FPGA with necessary block diagram. 18.Explain the working of various Programmable logic devices with the help of neat diagrams. 19.Implement a 4:1 multiplexer using HDL. 20.Implement a half adder using HDL 21.Implement a full adder using HDL.