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Module4_ARM_Detailed_Answers_Clean

The document outlines the ARM processor's exception handling, including types of exceptions, modes, and the vector table. It discusses interrupt latency, prioritization, and the handling of IRQ and FIQ exceptions, along with code for enabling/disabling interrupts. Additionally, it covers firmware concepts, execution flow, and the ARM firmware suite components, providing diagrams for better understanding.

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101 views

Module4_ARM_Detailed_Answers_Clean

The document outlines the ARM processor's exception handling, including types of exceptions, modes, and the vector table. It discusses interrupt latency, prioritization, and the handling of IRQ and FIQ exceptions, along with code for enabling/disabling interrupts. Additionally, it covers firmware concepts, execution flow, and the ARM firmware suite components, providing diagrams for better understanding.

Uploaded by

gloryrp58
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MICROCONTROLLER (BCS402) - MODULE 4 Detailed Answers

1. ARM Processor Exceptions and Modes with IVT

The ARM processor has several exceptions that interrupt normal program execution.
These include Reset, Undefined Instruction, SWI, Prefetch Abort, Data Abort, IRQ, and FIQ.
The processor switches to special modes to handle these exceptions.

Modes: User, System, Supervisor (SVC), IRQ, FIQ, Abort, and Undefined. Each has its own
stack pointer (r13) and link register (r14).

Vector Table: Located at 0x00000000, contains addresses of handlers (Reset: 0x00, IRQ: 0x18,
FIQ: 0x1C, etc.).
On an exception, CPSR is saved to SPSR, PC to LR, and processor mode changes to the exception
mode.

Draw diagrams of the exception modes and vector table.

2. Exception Priorities and Link Register Offsets

ARM exceptions have a priority order: Reset > Data Abort > FIQ > IRQ > Prefetch Abort >
SWI/Undefined.
When an exception occurs, the Link Register (LR) is set to PC+4 or +8 due to pipeline effects.

On return, the handler subtracts 4 from LR to get the accurate resume address.
Draw a priority diagram and PC-LR offset diagram.

3. Interrupt Latency with Nested Interrupt Handler and Prioritization

Interrupt latency is the delay from interrupt request to ISR execution.


Nested interrupt handlers let higher-priority interrupts preempt lower ones.
Prioritization ensures critical tasks are never delayed.

Draw a nested interrupt flow diagram.


4. IRQ and FIQ Exception Handling

On IRQ: Processor disables further IRQs, saves CPSR to SPSR_irq, PC to LR_irq, enters IRQ
mode,
and jumps to 0x18. After handler, resumes using LR-4.

On FIQ: Disables both IRQ and FIQ, saves CPSR to SPSR_fiq, uses banked registers r8-r12 for
speed,
jumps to 0x1C. After handler, resumes similarly.

Draw diagrams showing IRQ and FIQ exception handling flow.

5. Code for Enabling and Disabling IRQ and FIQ

Enable IRQ:
MRS r1, cpsr
BIC r1, r1, #0x80
MSR cpsr_c, r1

Disable IRQ:
MRS r1, cpsr
ORR r1, r1, #0x80
MSR cpsr_c, r1

Use #0x40 for FIQ and #0xC0 for both IRQ and FIQ.
Draw a diagram of CPSR register highlighting I and F bits.

6. Basic Interrupt Stack Design and Implementation

Each mode has its own stack pointer (r13) to save registers during exceptions.
Stack layouts (A and B) show where stack memory is placed.

Separate stacks prevent data corruption and make debugging easier.


Draw stack layout diagrams A and B.
7. What is Firmware? Explain Firmware Execution Flow

Firmware is permanent software stored in ROM that starts on power-up.


It initializes hardware, loads OS/application, and provides an abstraction layer.

Execution Flow: Reset -> Init -> HAL -> Load OS/App -> Relinquish control.
Draw a firmware execution flow diagram.

8. ARM Firmware Suite: uHAL and Angel

uHAL: Hardware Abstraction Layer - standard API, drivers for serial, LEDs, timers.
Angel: Debug monitor - allows host debugger to control target via SWI/IRQ/FIQ.

Draw a block diagram of uHAL and Angel in firmware stack.

9. Sandstone Directory Layout and Execution Flow

Directory: /src (source), /obj (object), /image (firmware), /payload (OS/app).


Execution Flow: Reset -> Dummy Handlers -> Init Hardware -> Remap Memory -> Init Serial ->
Copy Payload -> Relinquish Control.

Draw a directory structure diagram and execution flow diagram.

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