B.M.

S COLLEGE OF ENGINEERING
(Autonomous college Affiliated to Visvesvaraya Technology University, Belgaum)
BullTemple Road, Basavanagudi, Bangalore-560019

AAT - 1 Assignment
Submitted for the partial fulfillment of the requirement of Alternate Assessment for the
course

System Verilog and Verification [23EC6PESV]

BACHELOR OF ENGINEERING
In

ELECTRONICS AND COMMUNICATION

ENGINEERING
by

SAHARSHA 1BM22EC211

2024 – 2025
Course Co-ordinator

Dr. Kiran Bailey

Assistant Professor, Dept. of ECE, BMSCE

Acknowledgement: This work was carried out with the EDA tools provided by Meity, Govt. of India,
under C2S funding.

1
Assignment 1

Implement T flipflop and test it using system Verilog test bench with
interface, modport clocking block and top module

Introduction:

This project focuses on the implementation and verification of a T (Toggle) flip-flop using
Verilog and a structured SystemVerilog testbench. The T flip-flop toggles its output on each
clock edge when the T input is high, making it useful in counters and control systems.

The testbench uses SystemVerilog features like interface, modport, and clocking block to
organize signal connections and ensure accurate timing. A top module integrates the T flip-
flop and testbench components, providing a clean and reusable design structure.

This setup enables thorough and efficient verification of the T flip-flop’s behavior under
various conditions.

Codes:

T_Flipflop:

// T_FF module with asynchronous active high reset and synchronous active high set
module T_FF(T_inter.RTL R1);

// Always block triggered on the rising edge of clock or asynchronous reset

always @(posedge R1.clk, posedge R1.reset)
begin
// Asynchronous reset: if reset is high, immediately reset q to 0
if (R1.reset)
R1.q <= 0;

// Synchronous set: if set is high, set q to 1 on clock edge

else if (R1.set)
R1.q <= 1;

// Toggle operation: if T is high, toggle q; else hold previous value

else
R1.q <= R1.t ^ R1.q;
end

endmodule

Interface block:

// Interface for T Flip-Flop design and testbench interaction

interface T_inter(input bit clk); // Clock is passed as an input to the interface

// Internal signals used by both DUT and testbench

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 logic t; // Toggle input
logic set; // Synchronous set input
logic reset; // Asynchronous reset input
logic q; // Output of T flip-flop

// Modport for RTL (Design Under Test)

// Defines signal directions from the perspective of the T_FF module
modport RTL (
input clk, // Clock input
input t, // T input
input set, // Set input
input reset, // Reset input
output q // Output
);

// Modport for Testbench

// Defines signal directions from the perspective of the testbench
modport TB (
input q, // Observes output
output t, // Drives T input
output set, // Drives set input
output reset // Drives reset input
);

endinterface

Testbench :

//Test bench
module Test(T_inter.TB T1);
initial
begin
T1.set=0;T1.reset=0;T1.t=0;
#10 T1.reset=1;
#10
T1.reset=0;
#10
T1.set=1;
#10
T1.set=0;
#10
T1.t=1;
#10
T1.t=0;
#10
T1.t=1;
#100 $finish;
end
endmodule

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Top module:
// Top module to connect T Flip-Flop DUT and Testbench via interface
module Top;

bit clk; // Clock signal for the entire design

// Instantiate the interface and bind it to the clock signal

T_inter I1(clk);

// Instantiate the Test module and bind it to the TB modport of the interface
Test inst1(I1.TB);

// Instantiate the T_FF module (Design Under Test) and bind to RTL modport of the
interface
T_FF DUT(I1.RTL);

// Clock generation: toggle every 5 time units to create a 10-time-unit period clock
always #5 clk = ~clk;

// Dump waveform data for simulation viewing

initial begin
$dumpfile("T_ff.vcd"); // VCD file for waveform
$dumpvars; // Dump all variables
end

endmodule

Simulation output:

4
Coverage report:

5
Assignment 2

Implement 8-bit ALU and test it using system Verilog test bench with
interface, mod port, clocking block and top module

Introduction:

This project focuses on the design and verification of an 8-bit Arithmetic Logic Unit (ALU)
using Verilog and SystemVerilog. The ALU is capable of performing a range of arithmetic and
logical operations such as addition, subtraction, AND, OR, XOR, and more, based on a control
input.

To ensure a modular and scalable verification environment, the testbench is built using
SystemVerilog constructs such as interface, modport, and clocking block. The interface
groups related signals, while modports define directionality for design and testbench roles. The
clocking block ensures proper synchronization of stimulus with the clock signal. A top module
integrates the ALU, interface, and test logic for simulation.

This approach not only verifies the correctness of the ALU under various input conditions but
also demonstrates best practices in structured digital design and verification.

Codes:

ALU block:

// 8-bit ALU module using an interface port

module alu(alu_if.DUT port); // Uses the DUT modport from the interface

// Combinational logic block

always_comb begin
port.valid = 1'b1; // By default, mark output as valid

// Operation selection based on 3-bit op code

case (port.op)
3'b000: port.result = port.a + port.b; // Addition
3'b001: port.result = port.a - port.b; // Subtraction
3'b010: port.result = port.a & port.b; // Bitwise AND
3'b011: port.result = port.a | port.b; // Bitwise OR
3'b100: port.result = port.a ^ port.b; // Bitwise XOR
3'b101: port.result = ~port.a; // Bitwise NOT (on operand A only)
3'b110: port.result = port.a << 1; // Logical left shift by 1
3'b111: port.result = port.a >> 1; // Logical right shift by 1

// Default case: Invalid operation code

default: begin
port.result = 8'h00; // Default result = 0
port.valid = 1'b0; // Mark output as invalid
end
endcase

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 end

endmodule

Interface block:

// Interface definition for 8-bit ALU

interface alu_if(input logic clk); // Clock input to synchronize testbench operations

// ALU signals
logic [7:0] a, b; // 8-bit input operands
logic [2:0] op; // 3-bit opcode to select the ALU operation
logic [7:0] result; // 8-bit result output
logic valid; // Output valid signal

// Modport for ALU (Design Under Test)

modport DUT(
input a, b, op, clk, // Inputs to the ALU
output result, valid // Outputs from the ALU
);

// Modport for Testbench

modport TB(
output a, b, op, // Testbench drives inputs
input result, valid // Testbench reads outputs
);

// Clocking block for synchronization on the rising edge of clk

clocking cb @(posedge clk);
output a, b, op; // Drive inputs to the DUT
input result, valid; // Sample outputs from the DUT
endclocking

endinterface

Testbench :

// Simple testbench for ALU using random inputs

module alu_tb(alu_if.TB T1);

bit [7:0] a, b;

bit [2:0] op;

bit [7:0] opcode_covered = 8'b0; // Track which opcodes were tested

int i = 0;

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 initial begin

// Repeat tests until all 8 opcodes are tested at least once

while (opcode_covered != 8'b1111_1111) begin

// Generate random inputs

a = $urandom_range(0, 255);

b = $urandom_range(0, 255);

op = $urandom_range(0, 7);

// Apply to interface

T1.a = a;

T1.b = b;

T1.op = op;

// Mark this opcode as tested

opcode_covered[op] = 1'b1;

end

$finish;

end
endmodule

Top module:

// Top module that integrates the ALU, interface, and testbench

module Top;

bit clk; // Clock signal for synchronization

// Instantiate the interface and connect it to the clock

alu_if I1(clk);

// Instantiate the testbench using the interface (uses TB modport)

alu_tb TB_inst(I1);

// Instantiate the ALU (Design Under Test) using the same interface (uses DUT modport)
alu DUT_inst(I1);

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 // Clock generation: toggles every 5 time units
always #5 clk = ~clk;

// Initial block to dump simulation waveforms

initial begin
$dumpfile("alu.vcd"); // Name of VCD (waveform) file
$dumpvars(0, Top); // Dump all variables in the Top module hierarchy
end

endmodule

Simulation output:

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Coverage report:

10
ASSIGNMENT 3

Implement a 4-bit ALU and develop a randomized test bench with the
following :

1. Driver class to derive data.

2. Transactor class for declaring random variables.
3. Virtual Interface.

ALU Module:

module ALU (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [2:0] ALUOp, // ALU Operation selector
output reg [3:0] Result // 4-bit output result
output reg Zero // Zero flag
);

always @(*) begin

case(ALUOp)
3'b000: Result = A + B; // ADD
3'b001: Result = A - B; // SUB
3'b010: Result = A & B; // AND
3'b011: Result = A | B; // OR
3'b100: Result = A ^ B; // XOR
3'b101: Result = ~(A | B); // NOR
3'b110: Result = A << B; // Shift Left
3'b111: Result = A >> B; // Shift Right
default: Result = 4'b0000;
endcase
Zero = (Result == 4'b0000) ? 1 : 0; // Set Zero flag
end

endmodule

Interface module :

interface ALU_if;
// Inputs to ALU
logic [3:0] A, B;
logic [2:0] ALUOp;

// Outputs from ALU

logic [3:0] Result;
logic Zero;
endinterface

11
Transactor class :

class ALU_Transactor;
// Declare the virtual interface
virtual interface ALU_if vif;

// Constructor to bind interface

function new(virtual interface ALU_if vif);
this.vif = vif;
endfunction

// Randomize ALU inputs

task drive_random_input();
// Randomize A, B and ALUOp
vif.A = $random;
vif.B = $random;
vif.ALUOp = $random % 8; // ALUOp range: 0 to 7

// Apply the values

#5; // Wait for 5 time units for the ALU to process
endtask
endclass

Driver class :

class ALU_Driver;
// Declare the virtual interface
virtual interface ALU_if vif;
ALU_Transactor transactor;

// Constructor to bind virtual interface and transactor

function new(virtual interface ALU_if vif);
this.vif = vif;
transactor = new(vif); // Create transactor
endfunction

// Task to drive random inputs

task drive_data();
// Call transactor to drive random data
transactor.drive_random_input();
endtask
endclass

Testbench :

module ALU_tb;

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 // Declare the virtual interface
ALU_if alu_if();

// ALU instance
ALU alu_inst (
.A(alu_if.A),
.B(alu_if.B),
.ALUOp(alu_if.ALUOp),
.Result(alu_if.Result),
.Zero(alu_if.Zero)
);

// Driver instance
ALU_Driver driver;

// Randomize ALU operation, inputs, and run multiple tests

initial begin
// Set up VCD dumping
$dumpfile("alu_simulation.vcd"); // Specify the name of the VCD file
$dumpvars(0, ALU_tb); // Dump all signals in the ALU_tb module

// Bind the virtual interface to the driver

driver = new(alu_if);

// Run a series of random tests to cover all ALU operations

// We will run 50 iterations to ensure random coverage
repeat(50) begin
// Randomize the inputs A and B
alu_if.A = $random;
alu_if.B = $random;

// Randomly select an ALU operation (ALUOp from 0 to 7)

alu_if.ALUOp = $random % 8;
// Apply the values and wait for some time for ALU to process
#10;
end

// Explicitly test the default case for ALUOp

// Setting ALUOp to a value greater than 7 to trigger the default case
alu_if.A = 4'b1111; // Set A to a known value
alu_if.B = 4'b0000; // Set B to a known value
alu_if.ALUOp = 3'b1000; // Set ALUOp to a value greater than 7 (trigger default case)
#10; // Wait for processing

// End simulation after all tests

$finish;
end

endmodule

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Simulation output

Coverage report

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