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Memory Interfacing - 20th Jan

The document discusses memory interfacing in microprocessor systems, specifically focusing on the 8085 microprocessor. It explains the types of memory, the role of tri-state buffers, and the process of writing to memory, including chip selection and memory mapping. Additionally, it covers the classification of address lines and how they are used for memory chip selection and location identification.

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kumar.ayana2005
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8 views17 pages

Memory Interfacing - 20th Jan

The document discusses memory interfacing in microprocessor systems, specifically focusing on the 8085 microprocessor. It explains the types of memory, the role of tri-state buffers, and the process of writing to memory, including chip selection and memory mapping. Additionally, it covers the classification of address lines and how they are used for memory chip selection and location identification.

Uploaded by

kumar.ayana2005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Memory interfacing……………8085

Memory in a microprocessor system is where information (data and instructions) is


kept. It can be classified into two main types:

➢Main memory (RAM and ROM)

➢Storage memory (Disks , CD ROMs, etc.)

Accessing Information in Memory:

For the microprocessor to access (Read or Write) information in memory (RAM or


ROM), it needs to do the following:

➢Select the right memory chip (using part of the address bus).
➢Identify the memory location (using the rest of the address bus).
➢Access the data (using the data bus).
Tri-State Buffers:

An important circuit element that is used extensively in memory.


This buffer is a logic circuit that has three states:
➢Logic 0, logic1, and high impedance.
➢When this circuit is in high impedance mode it looks as if it is disconnected from
the output completely.

The Tri-State Buffer


This circuit has two inputs and one output.
➢The first input behaves like the normal input for the circuit.
➢The second input is an “enable”.
●If it is set high, the output follows the proper circuit behavior.
●If it is set low, the output looks like a wire connected to nothing.
A: input ; B: enable ; C: output Hi-Z: high
impedence
The Basic Memory Element

The basic memory element is similar to a D latch.


This latch has an input where the data comes in. It has an enable input and an output on
which data comes out.
The Basic Memory Element
However, this is not safe. Data is always present on the input and the output is
always set to the contents of the latch.
To avoid this, tri-state buffers are added at the input and output of the latch.

The WR signal controls the input buffer.


➢The bar over WR means that this is an active low signal.
➢So, if WR is 0 the input data reaches the latch input.
➢If WR is 1 the input of the latch looks like a wire connected to nothing.

The RD signal controls the output in a similar manner.


The steps of writing into Memory:

What happens when the programmer issues the STA (copy accumulator content in
memory) instruction?

➢The microprocessor would turn on the WR control (WR = 0) and turn off
the RD control (RD = 1).

➢The address is applied to the address decoder which generates a single


Enable signal to turn on only one of the memory registers.

➢The data is then applied on the data lines and it is stored into the enabled
register.
Dimensions of Memory

Memory is usually measured by two numbers:


its length and its width (Length X Width).
●The length is the total number of locations.
●The width is the number of bits in each location.

The length (total number of locations) is a function of the number of address


lines.
number of memory locations = 2 (number of address lines)
So, a memory chip with 10 address lines would have
2 10 = 1024 locations (1K)

Looking at it from the other side, a memory chip with 4K locations would need
Log2 (4096)=12 address lines
The 8085 and Memory:

The 8085 has 16 address lines. That means it can address


2 16 = 64K memory locations.

Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each,
or 4 with 16 K each or 16 of the 4 K chips, etc.

how would we use these address lines to control the multiple chips?

Chip Select
Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an
active signal is applied on that input.
To allow the use of multiple chips in the make up of memory, we need to use a
number of the address lines for the purpose of “chip selection”.

These address lines are decoded to generate the 2n necessary CS inputs for the
memory chips to be used.
Chip Selection Example
➢Assume that we need to build a memory system made up of 4 of the 4 X 4 memory
chips we designed earlier.
➢We will need to use 2 inputs and a decoder to identify which chip will be used at what
time.

A0 A0 A0 A0
A1 A1 A1 A1

2 X4
Decoder
Memory Map and Addresses
The memory map is a picture representation of the address range and shows where the
different memory chips are located within the address range.
Address Range of a Memory Chip
The address range of a particular chip is the list of all addresses that are mapped to the
chip.

The 8085 and Address Ranges


The 8085 has 16 address lines. So, it can address a total of 64K memory locations.

➢ If we use memory chips with 1K locations each, then we will need 64 such chips.
➢ The 1K memory chip needs 10 address lines to uniquely identify the 1K locations.
(log 2 1024=10)
➢ That leaves 6 address lines which is the exact number needed for selecting between
the 64 different chips (log 2 64=6).
Now, we can break up the 16-bit address of the 8085 into two pieces:

Chip selection lines Memory range: lines for selecting


memory location within selected
chip
Depending on the combination on the address lines A15-A10 , the address range of the
specified chip is determined.
High-Order vs. Low-Order Address Lines

The address lines from a microprocessor can be classified into two types:

●High-Order: Used for memory chip selection


●Low-Order: Used for location selection within a memory chip.

This classification is highly dependent on the memory system design.

High- Low-
Order Order
Chip Select Example:

A chip that uses the combination A15 to A10 = 001000 would have addresses that range
from 2000H to 23FFH.

➢Keep in mind that the 10 address lines on the chip gives a range of 000000 0000 to
11 1111 1111 or 000H to 3FFH for each of the chips.

➢The memory chip in this example would require the following circuit on its chip
select input:

0 1
0 1
1 Active low: enabled
0 1 when 0
1 1
1
0
0
Chip Select Example
If we change the previous combination to the following:

Now the chip would have addresses ranging from: 2400 to 27FF.
Changing the combination of the address bits connected to the chip select changes the
address range for the memory chip.
Chip Select Example
To illustrate this with a picture:in the first case, the memory chip occupies the
piece of the memory map identified as before.
In the second case, it occupies the piece identified as after.
EN
D

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