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Micro Assignment 5

The document explains various assembler directives of the 8086 microprocessor, detailing their functions with examples. It outlines the steps for developing an assembly language program and describes the roles of key tools such as editors, assemblers, linkers, and debuggers. Additionally, it discusses I/O interfacing methods, the block diagrams and modes of operation for the 8255 and 8253/8254, control word formats, and the functionalities of the 8259 PIC and 8237 DMA controller.

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2 views

Micro Assignment 5

The document explains various assembler directives of the 8086 microprocessor, detailing their functions with examples. It outlines the steps for developing an assembly language program and describes the roles of key tools such as editors, assemblers, linkers, and debuggers. Additionally, it discusses I/O interfacing methods, the block diagrams and modes of operation for the 8255 and 8253/8254, control word formats, and the functionalities of the 8259 PIC and 8237 DMA controller.

Uploaded by

er.devanshpathak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1. Explain any six assembler directives of 8086 with suitable example.

(5
Marks)

Assembler directives guide the assembler on how to process the source code. They are not
executable instructions but help in organizing the code. Six common directives:

1. DB (Define Byte): Reserves a byte of memory and optionally initializes it.


o Example: NUM DB 0AH – reserves 1 byte initialized to 0AH.
2. DW (Define Word): Reserves two bytes (a word) of memory.
o Example: COUNT DW 1234H
3. EQU (Equate): Defines a constant without occupying memory.
o Example: MAX EQU 09H
4. ORG (Origin): Sets the starting address for code or data.
o Example: ORG 1000H
5. SEGMENT/ENDS: Marks the beginning and end of a segment.
o Example:
o DATA SEGMENT
o VAR1 DB 10
o DATA ENDS
6. END: Indicates the end of the program to the assembler.
o Example: END START

2. Explain steps of developing an Assembly Language Program. (5 Marks)

1. Problem Definition: Clearly understand the problem and its requirements.


2. Algorithm Design: Convert the problem into a logical sequence of operations.
3. Program Coding: Translate the algorithm into assembly instructions using
mnemonics.
4. Assembly: Use an assembler to convert source code into object code.
5. Linking: Combine multiple object files into an executable if needed.
6. Testing and Debugging: Use debugging tools to verify correctness and fix errors.

3. Explain the function of (i) Editor, (ii) Assembler, (iii) Linker, (iv) Debugger.
(5 Marks)

 Editor: A software tool to write and edit source code (e.g., Notepad++, Turbo
Editor).
 Assembler: Converts assembly language code into machine code (.obj files).
Examples: TASM, MASM.
 Linker: Combines object files and resolves addresses to create a final executable file.
 Debugger: Helps trace and fix logical and runtime errors by allowing step-by-step
execution.
4. Discuss difference between I/O Mapped I/O interfacing and Memory
Mapped I/O interfacing. (5 Marks)

Feature I/O Mapped I/O Memory Mapped I/O


Address Space Separate I/O address space Uses same space as memory
Uses IN/OUT instructions
Instruction Set Uses all memory access instructions
only
Address Lines
8 address lines (256 devices) Full address lines (up to 1MB space)
Used
Speed Faster due to simpler access Slower due to full memory decoding
More flexible due to full instruction
Flexibility Limited
support

5. Explain block diagram of 8255 and explain its different modes of operation.
(10 Marks)

Block Diagram Components:

 Data Bus Buffer: Interfaces 8255 with the data bus.


 Read/Write Control Logic: Manages read/write operations.
 Control Register: Stores control word for port configuration.
 Ports: 3 ports – Port A, Port B, Port C (can be used for control too).

Modes of Operation:

1. Mode 0 (Basic I/O):


o Simple input/output.
o No handshaking.
o Each port can be independently programmed.
2. Mode 1 (Strobed I/O):
o Input or output with handshaking.
o Uses control signals (STB, IBF, OBF, INTR).
o Synchronization with peripheral devices.
3. Mode 2 (Bidirectional):
o Only Port A supports.
o Two-way data transfer with handshaking.

6. Explain control word format of 8255. (5 Marks)

The control word (for I/O mode) is an 8-bit data written to the control register to configure
the ports:

Bit Function
D7 Mode Set Flag (1 = I/O Mode)
D6-D5 Group A Mode Selection (00-11)
Bit Function
D4 Port A Direction (1 = Input)
D3 Group B Mode Selection (0/1)
D2 Port B Direction
D1 Port C Upper (PC7-PC4) Dir
D0 Port C Lower (PC3-PC0) Dir

Example: 10011010B configures ports accordingly.

7. Write an ALP of finding smallest number program through 8086. (5


Marks)
MOV CX, 05 ; Number of elements
LEA SI, ARRAY ; Load address of array
MOV AL, [SI] ; Load first element
NEXT: INC SI
CMP AL, [SI] ; Compare with next
JBE SKIP
MOV AL, [SI] ; Update if smaller
SKIP: LOOP NEXT
; AL contains smallest number

8. Write an ALP using directives to find even and odd numbers from the given
array. (5 Marks)
LEA SI, ARRAY
MOV CX, 05
REPEAT:
MOV AL, [SI]
TEST AL, 01 ; Check LSB
JZ EVEN
; Handle ODD
JMP SKIP
EVEN:
; Handle EVEN
SKIP:
INC SI
LOOP REPEAT

9. Explain the different hand shake signals in mode 1 of 8255 interface for
input and output device interfacing both. (10 Marks)

Input Handshaking:

 STB (Strobe): Activated by peripheral to indicate data is ready.


 IBF (Input Buffer Full): Set when data is latched.
 INTR: Sent to CPU after data is received.
Output Handshaking:

 OBF (Output Buffer Full): Set when data is available to peripheral.


 ACK (Acknowledge): Peripheral signal to confirm data receipt.
 INTR: Sent to CPU after acknowledgment.

These signals ensure data integrity and synchronization.

10. Explain block diagram of 8253/8254 and explain its different modes of
operation. (10 Marks)

Block Diagram Includes:

 Data Bus Buffer: Interface to system data bus.


 Read/Write Logic: Controls access.
 Control Word Register: Receives mode and counter information.
 Three Independent Counters: Each has CLK, GATE, and OUT pins.

Modes:

1. Mode 0 (Interrupt on Terminal Count): Counter decrements and sets OUT high on
zero.
2. Mode 1 (Hardware Retriggerable One-Shot): OUT goes low on GATE, high after
count.
3. Mode 2 (Rate Generator): Periodic low pulse output.
4. Mode 3 (Square Wave Generator): Generates square wave output.
5. Mode 4 (Software Triggered Strobe): Single low pulse after count.
6. Mode 5 (Hardware Triggered Strobe): Similar to Mode 4, but triggered via GATE.

11. Explain control word format of 8253/8254. (5 Marks)

Bit Description
D7-D6 Counter Select (00: Counter 0, etc.)
D5-D4 Read/Write (00 = Latch, 11 = LSB+MSB)
D3-D1 Mode Select (000 to 101)
D0 BCD/Binary Mode (0 = Binary, 1 = BCD)

Example: 00110110B sets Counter 0, Mode 3, Binary, LSB+MSB access.

12. Write a program to generate a square wave of 1 KHz using 8253 timer.
Assume the clock frequency of 8253 is 2 MHz. (10 Marks)
Required Count: 2MHz / (2*1kHz) = 1000 = 03E8H

MOV AL, 36H ; Mode 3, LSB+MSB, Counter 0


OUT 43H, AL
MOV AX, 03E8H ; Load count 1000
OUT 40H, AL ; Send LSB
MOV AL, AH
OUT 40H, AL ; Send MSB

This generates a square wave of 1 kHz.

13. Explain block diagram of 8259 PIC. (10 Marks)

Components:

 Interrupt Request Register (IRR): Stores incoming IRQs.


 In-Service Register (ISR): Tracks which IRQ is being serviced.
 Interrupt Mask Register (IMR): Masks unwanted interrupts.
 Priority Resolver: Determines priority among requests.
 Control Logic: Manages operation with CPU.

Supports cascading (up to 64 IRQs), edge/level triggering, and priority management.

14. Explain different operating modes of 8259. (5 Marks)

1. Fully Nested Mode: Default; highest priority is IRQ0.


2. Special Mask Mode: Allows interrupt servicing despite masking.
3. Rotating Priority Mode: Priority shifts after each interrupt.
4. Polling Mode: CPU checks status instead of automatic interrupt handling.

15. Explain DMA Controller 8237 in details. (10 Marks)

Components:

 4 DMA Channels: For independent transfers.


 Address/Count Registers: Track memory and byte count.
 Command/Status Registers: Control operation.
 Request and Acknowledge Lines: Interface with peripherals.

Features:

 Memory-to-memory transfer
 Automatic address increment/decrement
 Priority control
 Cascade for expansion

Reduces CPU overhead for large data transfers.

16. Explain data transfer modes of 8237 DMA Controller. (5 Marks)

1. Single Transfer Mode: One byte per request cycle.


2. Block Transfer Mode: Continuous block transfer.
3. Demand Mode: Transfer continues while DREQ is active.
4. Cascade Mode: Chains multiple DMA controllers.

Used to optimize data throughput in I/O intensive applications.

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