DUAL MODE TRANSMITTER WITH ADAPTIVELY CONTROLLED SLEW
RATE AND IMPEDANCE SUPPORTING WIDE RANGE DATA RATES
Hongjiang Song
Intel Corporation, Chandler, Arizona 85226, USA,
Phone: 480-554-3187, Fax: 480-554-2241, email: lzsong @sedona.intel.coin
Abstract-A novel dual mode transmitter that can be The paper is organized as follows. In section 11, the
configured either in rail-to-rail voltage mode supporting dual-mode transmitter architecture is given. The on-
lJMb/s and 12Mb/s data rate or in a 400mV low-swing chip adaptive slew rate control scheme and terminate
current mode supporting 480Mb/s data rate is presented. impedance control scheme are described in Section 111
In addition, adaptive control schemes for the output and Section IV. The silicon implementation and
impedance and the slew rate are also integrated. The test
experiment results are given in Section V, followed by
circuit is implemented using a 0.25um standard CMOS
process technology. It occupies an area of about SOOum x the conclusion in Section VI.
200um and consume less than 70mW power. A better than
BER was measured at 480Mb/s data rate over a USB
cable with a 215-1pseudo-random data stream 11. DUAL-MODE TRANSMITTER
ARCHITECTURE
The proposed dual mode transmitter circuit architecture
I. INTRODUCTION is shown in Fig. 1, which consists of a pre-driver and a
main driver.
Traditional full-swing voltage-mode signaling U 0 has
been limited to data rates of 100Mb/s or lower and the
speed generally does not scaled with improving process
technologies. This type of transmitter usually dissipates
4
large amount of power per transition and introduces
large switching noise [ 11 [2]. Common ways to improve
the U 0 performance includes reducing the signal swing Re-driver
on the output driver, using differential current-mode M3 M d F -
switching, using better termination scheme, and using
accurately controlled output signal slew rate [3] [41 [ 5 ]
[6] [7]. However, system upgrade across different
signaling types associated with the performance
Mode control 7
advancing has created U 0 design challenges, mainly
due to the legacy support requirement for various Fig. 1 Dual mode transmitter architecture
signaling types, and data rates. Design constraints
resulted from the backward compatibility across the The pre-driver provides the mode control logic and
wide date rate range requires the transmitter to be fully necessary level shift for the main driver. The two
integrated to minimize load capacitance. In addition, operation modes of the transmitter are shown Fig.2. In
transmitter impedance and slew rate need to be tightly the voltage operation mode (Fig.2a). M2 and Mq gates
controlled over all operation speeds. are switched together in phase with the data, and the
This paper describes a novel dual mode transmitter MI, M3 are switched together in the opposite phase. RI,
architecture with integrated on-chip adaptive slew rate R2 serve as the pull-down terminate resistor, and MO,
and terminate resistor control circuit, supporting which operates in the linear mode as the output
1.SMb/s, 12Mb/s full-swing voltage mode signaling, approaches rail, serves as the pull-up terminate resistor
and 48OMb/s current mode signaling. (Ro).
0-7803-6741-3/901/$10.000 2001 IEEE
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In the current mode transmission mode (Fig.2b), MI,
M2 switch differentially and both M3, M4 are always in Txo+
the on operation mode, which keeps transistor MO in
saturation mode as a current source. Similarly, RI and TXO-
R2 serve as the terminate resistors.
* * Fig.3 The adaptive slew rate control scheme
a) voltage mode b) current mode
Fig.2 dual mode transmitter operation
111. ADAPTIVE SLEW RATE CONTROL
SCHEME
r
The adaptive slew rate control principle is shown Fig.3. Time
The circuit consists of N bit-slices of sequential switch
elements (SE). Each element includes a switch structure Fig.4 waveform synthesis principle
shown in either Fig.2a or Fig.2b. The switching timing
of these switch elements is controlled by a delay-
locked loop (DLL). With sequential switching of the IV. TERMINATE RESISTOR CONTROL
SEs, a desired output ramp can be generated through SCHEME
waveform synthesis concept (Fig.4).
This architecture offers several attractive properties. The on-chip transmitter termination scheme is shown in
The slew rate of the output'now only depends on the Fig.5. It uses a negative feedback loop to adaptively
number of the SE N, and the unit delay t+ Both of them control the transmitter impedance R1, R2 through an
can be accurately selected by design or by using the identical MOS-only reference resistor R,I.
DLL. As the result, the slew rate will be relatively
constant even with process, supply voltage and
temperatures variations, and it will scale with data rate T T
used. In addition, the output impedance uncertainty and
the switch di/dt noise is improved by approximately a
factor of N as only one switch element is in the
switching state at a time. Furthermore, the sequential
element switch scheme allows the SE to operate at the
highest speed while still maintaining a proper output
slew rate and low switching noise. These properties
make it very attractive for the VLSI/ULSI circuit
implementation, and very suitable for SOC
*
applications.
Fig.5 transmitter impedance control scheme
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With matched current reference Irefrthe value of the
transmitter impedance can be measured through the
voltage drop across REf. This voltage drop is compared
with a voltage reference V,f from the bandgap circuit.
With the help of the negative feedback loop, the output
impedance of the transmitter will be adaptively control
to the value given in (1).
Fig.8 Measured eye diagram at 480Mb/s rate
Shown in Fig.9 is the measured transmitter output
impedance with adaptive circuit enabled and bypassed.
In the bypass operation, the impedance can be
V. EXPERIMENT
RESULTS controlled by a 5-bit digital control code. It shows that
the adaptive impedance control circuit can achieve
The transmitter was implemented in a test chip using a better than +/-lo% of control accuracy.
0.25um CMOS technology. It occupied an area of
800um x 200um, and consumes less than 70mW power,
mainly for driving the 450hm impedance load. Sown in
Fig. 6, 7, and 8 are measurement eye diagrams of the
transmitted signal operated at low (l.SMb/s), full
(12Mb/s), and high (480Mb/s) speeds, through a USB
cable.
.- adaptive
0.00
0 4 8 12 16 20 24 28 32
digital control code
Fig.9 Measured transmitter output impedance
Shown in Fig. 10, 11, and 12 are the measured slew
rates of the transmitter at l.SMb/s, 12Mb/s, and
Fig.6 Measured eye diagram at 1.5Mb/s rate 48OMb/s data rate, across PVT corners and various
spec required loading conditions.
140 1 I
Fig.7 Measured eye diagram at 12Mb/s rate 0 20 40 60 80
measurement No.
Fig. 10 measure slew rate at l.SMb/s rate
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ACKNOWLEDGEMENT
20
The author would like to thank Nello Tanner for his
help in the silicon measurement.
REFERENCE:
Dally, W.J.; Ming-Ju Edward Lee; Fu-Tai An; Poulton, J.;
0 1 Tell, S. “High-performance electrical signaling”, Proceedings.
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measurement No.
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Electrical Signaling: Overview and Limitations”, ZEEE Micro,
Fig. 11 measure slew rate at 12Mb/s rate Vol.: 18, no: lpp.12-24, Jan.-Feb. 1998.
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Fig. 12 measure slew rate at 48OMb/s rate H. J. Song, “Dual Mode Transmitter”, US Patent Pending.
2000.
It demonstrated that the slew rates are controlled to
within +/-25% of the target. It is noticed that major
variation of the slew rate is due to the variation in the
external loading capacitors (0 to 600pf for low speed, 0
to 5Opf for full speed, and 0 to lOpf for high speed).
VI. CONCLUSION
We have developed a circuit architecture that integrates
voltage and current mode transmitters, slew rate and
impedance control for serial data link supporting
l.SMb/s, 12Mb/s and 480Mb/s data rates. Based on the
waveform synthesis, delay-locked loop, and impedance
feedback control techniques, this circuit requires none
of the critical analog components. The limited in
performance only by the speed of the bit slice. The
CMOS-only implementation assures high scalability
along with the speed of the CMOS process technology.
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