😀 COA Manual

SHREE PAREKH ENGINEERING COLLEGE

MAHUVA

DEPARTMENT OF
INFORMATION & TECHNOLOGY

LAB MANUAL

Computer Organization & Architecture

 SHREE PAREKH ENGINEERING COLLEGE

MAHUVA

CERTIFICATE

This is to certify that

Mr.Rana Jaypalsinh P. Arman A. Enrollment No. 241473107001 of

Semester-4 Computer Engineering and Batch 2023-27 has satisfactorily
completed his/her practical work as prescribed in syllabus of the subject
COMPUTER ORGANISATION AND ARCHITECTURE (3140707) as
prescribed by Gujarat Technological University during the academic
term 2024-25.

Date:

Head of Department Faculty In-Charge

Prof . Krishna Rathod Prof . Gunjan Dashore
Sr. Experiments List Date of Date of Sign.
No. assign submission
1 To Study and Verify The Truth Table of Basic and 07/01/2025 21/01/2025
Universal Logic Gates.

2 To Write and Execute C Program for NAND & NOR 21/01/2025 28/01/2025
Gate.

3 Construction of Half Adder Using Logic Gates and 28/01/2025 04/02/2025

Verification of its Truth Table.

4 Construction of Full Adder Using Logic Gates and 04/02/2025 11/02/2025

Verification of its Truth Table.

5 Construction of Half Substractor Using Logic Gates 11/02/2025 18/02/2025

and Verification of its Truth Table.

6 Construction of Full Subtractor Using Logic Gates 18/02/2025 04/03/2025

and Verification of its Truth Table.

7 Implementation of 4 x 1 Multiplexer using basic logic 04/03/2025 11/03/2025

gates.
8 Implementation of 1 x 4 Demultiplexer using basic 11/03/2025
logic gates.
9 To Implement 1’s Complement Using 18/03/2025
GNUSim8085.
10 To Implement 2’s Complement Using 25/03/2025
GNUSim8085.
11 01/04/2025
12 Write an Assembly code to print a Message using 08/04/2025
Dosbox.
13 Write an Assembly Language Program to take input
from the user and print it to screen using Dosbox.
AIM 1 :
To Study and Verify The Truth Table of Basic and Universal Logic
Gates.

AND Gate :
An AND gate is a basic digital logic gate that produces an output of 1
(true) only when all of its inputs are 1 (true). For any other
combination of inputs, the output is 0 (false). It’s commonly used in
circuits where multiple conditions must be satisfied simultaneously.
The truth table for a 2-input AND gate shows that the output is 1 only
when both inputs are 1, otherwise, the output is 0. The Boolean
expression for a 2-input AND gate is represented as A ⋅ B, and it plays
a key role in decision-making processes, arithmetic operations, and
more complex digital circuits like multiplexers and decoders.

Logic Symbol : AND Gate (all operation).

TRUTH TABLE

Input Output

A B R
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate :
An OR gate is a fundamental digital logic gate that outputs a 1 (true) if at least one of its inputs is
1 (true). The output is 0 (false) only when all of its inputs are 0. It is often used in circuits where a
decision is made based on multiple conditions, where only one condition needs to be true for the
output to be true. The truth table for a 2-input OR gate shows that the output is 1 in three cases:
when either input is 1, or both inputs are 1. The Boolean expression for a 2-input OR gate is
represented as A + B. OR gates are widely used in applications such as control systems, decision-
making circuits, and building more complex logic functions like adders and multiplexers.

Logic Symbol : OR Gate (all operation).

TRUTH TABLE

Input Output

A B R
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate :
A NOT gate, also known as an inverter, is a basic digital logic gate that outputs the opposite
(inverted) value of its input. If the input is 1 (true), the output will be 0 (false), and if the input is
0 (false), the output will be 1 (true). It is a unary gate, meaning it only has one input. The truth
table for a NOT gate shows that it inverts the input signal: if the input is 0, the output is 1, and if
the input is 1, the output is 0. The Boolean expression for a NOT gate is represented as ¬A or
simply A'. NOT gates are widely used in digital circuits for signal inversion, inverting control
lines, and implementing other complex logic functions in combination with other gates like AND
and OR.

Logic Symbol : NOT Gate (all operation).

TRUTH TABLE

Input Output
A R
0 1
1 0
NAND Gate :
A NAND gate is a digital logic gate that outputs 0 (false) only when all
of its inputs are 1 (true); in all other cases, the output is 1 (true).
Essentially, it is the inverse of an AND gate, meaning it combines the
behavior of an AND gate followed by a NOT operation. The truth table
for a 2-input NAND gate shows that the output is 1 except when both
inputs are 1, in which case the output is 0. The Boolean expression for
a NAND gate is represented as (A ⋅ B)' or ¬(A ⋅ B). NAND gates are very
important in digital electronics because they are considered
universal gates, meaning any other logic gate (AND, OR, NOT, etc.) can
be constructed using just NAND gates. They are widely used in digital
systems for creating more complex circuits, memory storage, and
processors.

Logic Symbol : NAND Gate (all operation).

Input Output

A B R
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate :
A NOR gate is a digital logic gate that outputs 1 (true) only when all of its inputs are 0 (false). If
any of the inputs are 1 (true), the output will be 0 (false). It is essentially the inverse of an OR gate,
combining the behavior of an OR gate followed by a NOT operation. The truth table for a 2-input
NOR gate shows that the output is 1 only when both inputs are 0, and 0 for all other input
combinations. The Boolean expression for a NOR gate is represented as (A + B)' or ¬(A + B).
NOR gates are considered universal gates, meaning they can be used to implement any other type
of logic gate (AND, OR, NOT, etc.). They are widely used in digital circuits for creating complex
logic functions, control systems, and memory elements.

Logic Symbol : NOR Gate (all operation).

 Input Output

A B R
0 0 1
0 1 0
1 0 0
1 1 0

AIM 2 : To Write and Execute C Program for NAND & NOR Gate.

NAND Gate (C Program) :

#include <stdio.h>
#include<conio.h>
#include <stdlib.h>
void main()
{
clrscr();
int a[4] = { 1, 0, 1, 0 };
int b[4] = { 0, 1, 1, 0 };
int i, ans;
for (i = 0; i < 4; i++)
{
if (a[i] == 1 && b[i] == 1)
ans = 0;
else
ans = 1;

printf("\n %d NAND %d = %d", a[i], b[i], ans);

}
getch();
}
OutPut :

NOR Gate (C Program):

#include <stdio.h>
#include<conio.h>
#include <stdlib.h>
void main()
{
Clrscr();
int a[4] = { 1, 0, 1, 0 };
int b[4] = { 0, 1, 1, 0,};
int i, ans;

for (i = 0; i < 4; i++)

{
ans = !(a[i] + b[i]);

printf("\n %d NOR %d = %d", a[i], b[i], ans);

}
getch();
}
OutPut :

AIM 3 :
Construction of Half Adder Using Logic Gates and Verification of its
Truth Table.

HALF Adder :
A half adder is a digital circuit used to perform binary addition of two single bits. It produces two
outputs: the sum (S) and the carry (C). The sum is the result of the addition, while the carry
indicates whether a '1' needs to be carried over to the next column in multi-digit addition. Half
adders are fundamental building blocks in arithmetic logic units (ALUs) within computers and
other digital systems.
TRUTH TABLE
INPUT OUTPUT

A B S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1
AIM 4 :
Construction of Full Adder Using Logic Gates and Verification of its
Truth Table.

Full Adder :
A full adder is a digital circuit that performs the addition of three binary digits (bits): two operands
(A and B) and a carry-in (Cin) from a previous stage of addition. It produces two outputs: the sum
(S) and the carry-out (Cout). The sum is the result of the addition, while the carry-out represents a
carry that needs to be propagated to the next stage of addition when performing multi-bit addition.
Full adders are essential components in arithmetic logic units (ALUs) of computers and other
digital systems, enabling the addition of binary numbers of any length.

Circuit Diagram of Full Adder Using Logic Gates:

 TRUTH TABLE

INPUT OUTPUT

A B C-IN SUM C-OUT

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 0
1 1 1 1 1
`1.
2.

3.
4.

5.
6.

7.
8.

AIM 5 :
Construction of Half Substractor Using Logic Gates and Verification
of its Truth Table.

Half Substractor :
A half subtractor is a digital logic circuit used to perform binary subtraction on two single bits. It
produces two outputs: the difference (the result of the subtraction) and the borrow (indicating if a
1 was borrowed from the next higher bit position). While simple, the half subtractor has a
limitation: it cannot handle a 'borrow in' from a previous stage, making it unsuitable for multi-bit
subtraction.
 TRUTH TABLE

INPUT OUTPUT

A B D B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1
AIM 6 :
Construction of Full Subtractor Using Logic Gates and Verification
of its Truth Table.

Full Substractor :
A full subtractor is a digital logic circuit that performs binary subtraction on three bits: two input
bits (minuend and subtrahend) and a borrow-in bit from a previous stage. It produces two outputs:
the difference bit and a borrow-out bit, which indicates whether a borrow is needed for the next
stage of a multi-bit subtraction. Unlike a half subtractor, the full subtractor can handle the borrow-
in, making it suitable for multi-bit binary subtraction.

TRUTH TABLE

A B B-IN DIFFERENCE B-OUT

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
1.

2.

3.

4.
5.

6.

7.
8.

AIM 7 :
Implementation of 4 x 1 Multiplexer using basic logic gates.
Multiplexer : Multiplexer is a combinational circuit that has a maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.

4 x 1 Multiplexer : 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1
& s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

1.
2.

3.
4.

AIM 8 :
Implementation of 1 x 4 DeMultiplexer using basic logic gates.
1 x 4 DEMultiplexer : A Demultiplexer is a combinational logic circuit that accepts a single
input and distributes it over several output lines. Demultiplexer is also termed as DEMUX in short.
As Demultiplexer is used to transmit the same data to different destinations, hence it is also known
as a data distributor.

SELECT LINE OUTPUT

S0 S1 Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D

1.
2.

3.
4.

AIM 9 :
To Implement 1’s Complement Using GNUSim8085.

Source code:
;IMPLEMENTATION A 1'S COMPLEMENT
MVI A,15
CMA
STA 2000
HLT

Execution of 1’s complement.

STEP 1 : Executing “MVI A,15” Instruction and Data In Accumulator After

Execution.

STEP 2 :Executing “CMA” Instruction and Data In Accumulator After Execution.

STEP 3 :Executing “CMA” Instruction and Data In Accumulator After Execution.
AIM 10 : To Implement 2’s Complement Using GNUSim8085.

Source code:
;IMPLEMENTATION A 1'S COMPLEMENT
MVI A,15
CMA
ADI 01
STA 2000
HLT

Execution of 2’s complement.

STEP 1 :
STEP 2 :

STEP 3 :

STEP 4 :