350+ Most Asked

Digital Electronics Interview

Questions
with Detailed Answers

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VLSI — Embedded Systems — Core Electronics Interviews

Edition: 2025
Based on Real Interview Experiences from Top Companies

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Digital Electronics Interview Guide i

Contents

1 Logic Gates & Boolean Algebra – 50 Questions 1

Chapter 2: Combinational Circuits 7

Combinational Circuits (Q41–Q50) . . . . . . . . . . . . . . . . . . . . . . . . 9
Combinational Circuits (Q51–Q60) . . . . . . . . . . . . . . . . . . . . . . . . 11
Combinational Circuits (Q61–Q70) . . . . . . . . . . . . . . . . . . . . . . . . 13
Combinational Circuits (Q71–Q80) . . . . . . . . . . . . . . . . . . . . . . . . 15
Combinational Circuits (Q81–Q100) . . . . . . . . . . . . . . . . . . . . . . . 18
Sequential Circuits (Q101–Q130) . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sequential Circuits (Q131–Q140) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Digital Electronics Interview Guide 1

1 Logic Gates & Boolean Algebra – 50 Questions

Q1. What is the difference between NAND and NOR gates in terms of
universality?
Asked in: Intel, Texas Instruments
Answer:
Both NAND and NOR gates are considered universal gates, meaning any digital logic
circuit can be implemented using either of them alone. The difference lies in their oper-
ation:

• NAND is a combination of AND + NOT: Output is LOW only when all inputs are
HIGH.

• NOR is a combination of OR + NOT: Output is HIGH only when all inputs are
LOW.

In practical implementation, NAND gates are more commonly used due to better transistor-
level efficiency in CMOS design.

Q2. Realize the EX-OR gate using only NAND gates.

Asked in: Qualcomm, Micron
Answer:
The EX-OR gate expression: A ⊕ B = (A · B) + (A · B)
Using NAND gates only:
X1 = A NAND B
X2 = A NAND X1
X3 = B NAND X1
Y = X2 NAND X3
This final output Y behaves like an EX-OR gate.

Q3. Prove that DeMorgan’s Theorems hold true for three variables.
Asked in: ON Semiconductor
Answer:
DeMorgan’s Theorems:
A·B·C =A+B+C
A+B+C =A·B·C
Verified using a truth table of all 8 combinations of (A, B, C). The results on both sides
of the equations are the same for every combination.

Q4. What is the Boolean expression for the following logic circuit? (Text-
based description)
Asked in: NXP Semiconductors
Answer:
Assuming a circuit has two AND gates with inputs A, B and C, D respectively, both
outputs going into an OR gate:

Y = (A · B) + (C · D)
Digital Electronics Interview Guide 2

Q5. Why NAND gate is considered more efficient than NOR gate in VLSI?
Asked in: AMD, GlobalFoundries
Answer:
NAND gates require fewer transistors than NOR gates for CMOS implementation. Pull-
down networks in NAND are faster than pull-up networks in NOR. This makes NAND
preferable in critical path design.

Q6. Simplify the Boolean function: F = AB + AB

Asked in: LT, STMicroelectronics
Answer:

F = AB + AB = A(B + B) = A(1) = A

Q7. Define the term ’Idempotent Law’ in Boolean algebra.

Asked in: Samsung, Synopsys
Answer:
In Boolean algebra:
A + A = A and A · A = A
This is called the Idempotent Law – repeating the same input doesn’t change the output.

Q8. What is the dual of the expression: A + A · B?

Asked in: Cadence
Answer:
To find the dual, replace:

• OR (+) with AND (·)

• AND (·) with OR (+)

Dual = A · (A + B)

Q9. State and prove the Absorption Law.

Asked in: Intel, HCL
Answer:

A + AB = A and A(A + B) = A
Proof:
A + AB = A(1 + B) = A · 1 = A
A(A + B) = AA + AB = A + AB = A

Q10. What are canonical SOP and POS forms?

Asked in: Wipro, Bosch
Answer:
- SOP (Sum of Products): Sum of minterms (ANDed literals ORed together) - POS
(Product of Sums): Product of maxterms (ORed literals ANDed together) Canonical
form ensures each term contains all variables in true or complemented form.
Digital Electronics Interview Guide 3

Q11. Realize a 2-input XOR gate using only NOR gates.

Asked in: Broadcom, MediaTek
Answer:
XOR = (A ·B) + (A · B)
X1 = A NOR A = A
X2 = B NOR B = B
U singN OR : X3 = A NOR X2 = A + B
X4 = B NOR X1 = B + A
Y = X3 NOR X4 = A ⊕ B

Q12. What are minterms and maxterms? Give example.

Asked in: Infineon, Nvidia
Answer:

• Minterm: A product (AND) term where each variable appears once. E.g., for A,
B: AB

• Maxterm: A sum (OR) term where each variable appears once. E.g., A + B

Q13. Use Boolean algebra to simplify: A + AB

Asked in: Honeywell, BEL
Answer:
Using Absorption Law:

A + AB = A(1 + B) = A · 1 = A

Q14. What logic function is implemented by the expression: AB + AB?

Asked in: DRDO, Analog Devices
Answer:
That is the expression of XOR gate: A ⊕ B

Q15. How do you express the logic function of a 3-input majority gate?
Asked in: Cadence, Intel
Answer:
A 3-input majority gate outputs 1 when two or more inputs are 1.
Expression:
F = AB + BC + AC

Q16. Design a logic circuit that outputs 1 only when an odd number of
inputs are high (3-input case).
Asked in: MathWorks, TCS
Answer:
Use 3-input XOR:
Y =A⊕B⊕C
Digital Electronics Interview Guide 4

Q17. Simplify the Boolean expression: AB + AC + BC

Asked in: Cisco, IBM
Answer:
No direct simplification possible beyond expression optimization using K-map. Expres-
sion used in error detection circuits.

Q18. What is a literal in Boolean expression?

Asked in: Xilinx, Renesas
Answer:
A literal is a variable or its complement. For variable A, literals are: A, A

Q19. Prove: AB + C = A + B · C
Asked in: Wipro, Mindtree
Answer:
This is incorrect as written. Using DeMorgan:

AB + C = AB · C = (A + B) · C

Q20. Is Boolean algebra associative and commutative? Justify.

Asked in: Infosys, TI
Answer:
Yes.
• Commutative: A + B = B + A, A · B = B · A

• Associative: A + (B + C) = (A + B) + C, A · (B · C) = (A · B) · C

Q21. Implement the function F = AB + AC using only NAND gates.

Asked in: Texas Instruments, Qualcomm
Answer:
Convert into NAND form:
F = (AB) + (AC)
Implement NOT, AND, OR using NAND gates:
• NOT: A = A NAND A

• AND: A AND B = A NAND B

• OR: A + B = A · B
Circuit can be constructed accordingly.

Q22. What is the difference between canonical and standard form?

Asked in: Broadcom, Bosch
Answer:
• Standard Form: Terms may not include all variables.

• Canonical Form: Each term (minterm/maxterm) contains all variables in true or

complemented form.
Digital Electronics Interview Guide 5

Q23. State and prove the Consensus Theorem.

Asked in: AMD, Google Hardware Team
Answer:
Consensus Theorem: AB + AC + BC = AB + AC
Proof:
F = AB + AC + BC
= AB + AC (Since BC is redundant)

Q24. Convert SOP expression F = AB + AC + BC to POS form.

Asked in: Samsung, Cypress Semi
Answer:
Use K-map or apply algebraic transformation. Convert to canonical form, find comple-
ment, then apply DeMorgan to revert back.

Q25. What is the dual of the expression AB + AC

Asked in: HCL, LT Semiconductors
Answer:
Dual: Replace + with · and · with +
Dual of AB + AC = (A + B)(A + C)

Q26. What is a universal gate? Why is NAND called one?

Asked in: ON Semiconductor, Philips
Answer:
A universal gate can implement any Boolean function.
NAND is universal because it can be used to build NOT, AND, OR, XOR, etc.

Q27. How can you detect a stuck-at-0 fault using a simple logic gate?
Asked in: Cadence, Marvell
Answer:
Apply logic 1 to the input. If output remains 0, it confirms a stuck-at-0 fault. Use XOR
to compare expected vs observed outputs.

Q28. Realize the function F = (A + B)(A + C) using basic gates.

Asked in: Synopsys, TSMC
Answer:
1. Use OR gates to realize A + B and A + C
2. Invert A using NOT gate
3. Final AND gate for the product

Q29. Define an inverter and its truth table.

Asked in: STMicroelectronics, Bosch
Answer:
An inverter (NOT gate) outputs the complement of the input.

Input Output
0 1
1 0
Digital Electronics Interview Guide 6

Q30. Which logic gate has the property of output being false only when
all inputs are true?
Asked in: Honeywell, Vedanta
Answer:
NAND Gate — Truth table shows that it outputs 0 only when all inputs are 1.
Digital Electronics Interview Guide 7

Chapter 2: Combinational Circuits

Q31. What is a combinational circuit? Give examples.

Asked in: Intel, MediaTek
Answer:
A combinational circuit is one whose output depends only on the present input values,
not on past inputs.
Examples: Adders, Subtractors, Multiplexers, Encoders, Decoders.

Q32. Differentiate between combinational and sequential circuits.

Asked in: Qualcomm, Broadcom
Feature Combinational Circuit Sequential Circuit
Dependency Present Input Present + Past Inputs
Answer: (Memory)
Memory Element Not Required Required (Flip-flops)
Examples MUX, Decoder, Adder Counters, Registers, FSMs

Q33. Design a 2-to-4 line decoder with truth table and logic diagram.
Asked in: LT, Texas Instruments
Answer:
A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Logic: D0 = A1 · A0, D1 = A1 · A0, D2 = A1 · A0, D3 = A1 · A0

Q34. What is the difference between encoder and decoder?

Asked in: Bosch, Marvell
Answer:
• Encoder: Converts input lines to binary code (2 inputs → n outputs)

• Decoder: Converts binary input to a single active output (n inputs → 2 outputs)

Q35. Design a 4:1 multiplexer using basic gates.

Asked in: STMicroelectronics, Infineon
Answer:

Y = S1 · S0 · I0 + S1 · S0 · I1 + S1 · S0 · I2 + S1 · S0 · I3

Q36. How can a multiplexer be used to implement logic functions?

Asked in: Intel, Qualcomm
Answer:
By applying control lines as the variables and mapping outputs for respective input
conditions, a MUX can mimic any logic function.
Digital Electronics Interview Guide 8

Q37. Design a half adder with logic diagram and truth table.
Asked in: Synopsys, Samsung
Answer:

• Sum = A XOR B

• Carry = A AND B

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Q38. Extend the half adder to build a full adder.

Asked in: Vedanta, ARM
Answer:
Sum = A ⊕ B ⊕ Cin Carry = AB + BCin + ACin

Q39. What is the function of a parity generator?

Asked in: MediaTek, Qualcomm
Answer:
A parity generator adds a parity bit to data to ensure either even or odd number of 1s,
enabling error detection during transmission.

Q40. Design a BCD to Excess-3 code converter.

Asked in: Intel, NXP
Answer:
Add 3 (0011) to the BCD input:

If BCD = 0101 (5), Excess-3 = 1000 (8)

This can be achieved using a 4-bit binary adder.

Digital Electronics Interview Guide 9

Combinational Circuits (Continued)

Q41. What is a comparator? Design a 1-bit comparator.

Asked in: Qualcomm, Texas Instruments
Answer:
A comparator compares two binary values and outputs whether they are equal or not.

Equal = A ⊕ B, Greater = A · B, Less = A · B

Q42. Design a 2-bit magnitude comparator with logic expression.

Asked in: AMD, STMicroelectronics
Answer:

A > B = A1 B1 +(A1 ⊙B1 )·A0 B0 A < B = A1 B1 +(A1 ⊙B1 )·A0 B0 A = B = (A1 ⊙B1 )·(A0 ⊙B0 )

Q43. Define priority encoder. How is it different from a normal encoder?

Asked in: Intel, NXP
Answer:
A priority encoder gives output corresponding to the highest-priority active input.
Normal encoders don’t handle multiple active inputs, whereas priority encoders resolve
conflicts.

Q44. Draw the truth table for an 8:3 priority encoder.

Asked in: Analog Devices, TI
Answer:
Input (D7–D0) Output (Y2 Y1 Y0) Valid
10000000 111 1
01000000 110 1
00100000 101 1
00010000 100 1
00001000 011 1
00000100 010 1
00000010 001 1
00000001 000 1
00000000 XXX 0

Q45. What are the applications of multiplexers?

Asked in: Nvidia, Cadence
Answer:
• Data routing

• Logic function implementation

• Switching networks

• Communication and telemetry

Digital Electronics Interview Guide 10

Q46. Design a 4-bit binary to Gray code converter.

Asked in: Wipro, LT
Answer:
G3 = B3 G2 = B3 ⊕ B2 G1 = B2 ⊕ B1 G0 = B1 ⊕ B0

Q47. Why is Gray code preferred in some digital systems?

Asked in: Synopsys, Cypress
Answer:
Gray code ensures only one-bit changes between successive values, reducing errors in
analog-to-digital conversion and rotary encoders.

Q48. What is a look-ahead carry adder? How is it better than ripple carry
adder?
Asked in: Qualcomm, Broadcom
Answer:
It computes carries in advance using propagate and generate functions, reducing propa-
gation delay.
Ripple Carry Adder: O(n) delay, Look-Ahead Carry: O(log n) delay.

Q49. What is the function of a demultiplexer?

Asked in: Intel, NXP
Answer:
A demultiplexer takes a single input and routes it to one of many outputs depending on
the select lines. It’s the inverse of a multiplexer.

Q50. Implement Full Subtractor using only NAND gates.

Asked in: TI, Microchip
Answer: Full Subtractor:

Diff = A ⊕ B ⊕ BinBorrow = AB + (A ⊕ B)Bin

This can be implemented using gate-level NAND logic expansions.

Digital Electronics Interview Guide 11

Combinational Circuits (Q51–Q60)

Q51. Implement a 4:1 MUX using basic logic gates.

Asked in: Qualcomm, Wipro
Answer:
Y = S1 · S0 · I0 + S1 · S0 · I1 + S1 · S0 · I2 + S1 · S0 · I3

Q52. Design a 3-to-8 decoder using two 2-to-4 decoders.

Asked in: Intel, Bosch
Answer:
Use one decoder for enable control based on MSB, and two 2-to-4 decoders for generating
8 outputs.
• When MSB is 0: Enable lower 2-to-4 decoder
• When MSB is 1: Enable upper 2-to-4 decoder

Q53. Explain the concept of carry-save adder.

Asked in: AMD, Cadence
Answer:
Carry-Save Adders (CSAs) handle multiple operand additions by saving intermediate
carry values, avoiding carry propagation until final addition. Useful in multipliers.

Q54. What is the use of parity generators and checkers?

Asked in: STMicroelectronics, TCS
Answer:
They are used in digital communication systems to detect errors.
Even parity: Adds a bit to make total 1’s even.
Odd parity: Adds a bit to make total 1’s odd.

Q55. Realize XOR using only NAND gates.

Asked in: Texas Instruments, Infosys
Answer:
A ⊕ B = ((A · B) + (A · B)) = ((A NAND B) NAND (A NAND B)) with rearrangement

Q56. What is a universal gate? Why are NAND and NOR universal?
Asked in: MediaTek, Synopsys
Answer:
Universal gates can implement all basic logic functions (AND, OR, NOT).
NAND and NOR can form any logic gate, making them universal.

Q57. Implement a 2-bit binary multiplier.

Asked in: Microchip, LT
Answer: Let inputs be A1 A0 and B1 B0 .
Partial products:
P0 = A0 ·B0 P1 = (A0 ·B1 )⊕(A1 ·B0 )P2 = (A0 ·B1 )·(A1 ·B0 )⊕(A1 ·B1 )P3 = (A1 ·B1 )·(A0 ·B1 )·(A1 ·B0 )
Digital Electronics Interview Guide 12

Q58. Design a BCD to Excess-3 code converter.

Asked in: ON Semiconductor, HCL
Answer: Excess-3 code = BCD + 0011
Add binary 3 to BCD input using a 4-bit binary adder.

Q59. Define fan-in and fan-out. Why are they important?

Asked in: Broadcom, Intel
Answer:

• Fan-in: Number of inputs a gate can handle

• Fan-out: Number of gates driven by an output

Important for ensuring signal strength and avoiding delays.

Q60. What are hazards in combinational circuits? How can they be

avoided?
Asked in: TI, Samsung
Answer:

• Static hazard: Output changes momentarily when it should not.

• Dynamic hazard: Output changes multiple times instead of once.

• Avoidance: Use K-map with overlapping groups or redundant logic.

Digital Electronics Interview Guide 13

Combinational Circuits (Q61–Q70)

Q61. Differentiate between a decoder and a demultiplexer.

Asked in: Intel, Cognizant
Answer:
• Decoder: Converts binary input to a single high output line among many (e.g.,
3:8 decoder).

• Demultiplexer: Routes a single input to one of many output lines using select
inputs.

• Key difference: Decoder has no data input, only enable. Demux has data input.

Q62. Design a 2-bit comparator using logic gates.

Asked in: Infineon, Capgemini
Answer: Let inputs be A1 A0 and B1 B0

• A > B: A1 B1 + A0 B0 · A1 ⊕ B1

• A < B: A1 B1 + A0 B0 · A1 ⊕ B1

• A = B: A1 ⊕ B1 · A0 ⊕ B0

Q63. What is priority encoder? How is it different from a normal encoder?

Asked in: TCS, Mindtree
Answer:
• Priority encoder: Assigns output to the highest-priority active input.

• Normal encoder: Assumes only one input is active at a time.

• Key use: Resolves multiple active signals in systems like interrupt handling.

Q64. What are minterms and maxterms?

Asked in: Qualcomm, IBM
Answer:
• Minterm: AND combination of all input variables where function = 1

• Maxterm: OR combination of all input variables where function = 0

• Used in SOP (Sum of Products) and POS (Product of Sums) expressions

Q65. Realize a half-adder using only NAND gates.

Asked in: TI, Infosys
Answer:
• Sum (S) = A XOR B
Digital Electronics Interview Guide 14

• Carry (C) = A AND B

Implement both XOR and AND using NAND combinations:

S = (A NAND (A NAND B)) NAND (B NAND (A NAND B))

Q66. Explain the working of look-ahead carry adder.

Asked in: Xilinx, Tata Elxsi
Answer:

• Speeds up addition by generating carry signals in advance using:

Gi = Ai · Bi (Generate), Pi = Ai + Bi (P ropagate)

• Reduces delay compared to ripple carry adder.

Q67. Define and design a parity checker for 4-bit input.

Asked in: Cypress Semiconductor, TCS
Answer:
P =A⊕B⊕C ⊕D
If P = 0, then even parity; else odd.

Q68. What are programmable logic devices (PLDs)? Give types.

Asked in: Intel, Microsemi
Answer:

• PLDs: ICs that can be programmed to perform specific logic functions.

• Types: PROM, PAL, PLA, CPLD, FPGA.

Q69. Implement a logic circuit for majority function of 3 inputs.

Asked in: Analog Devices, Bosch
Answer:
Y = AB + AC + BC
Output is 1 if majority inputs are 1.

Q70. What is a logic hazard? How can it be resolved?

Asked in: LT, Synopsys
Answer:

• Logic hazard: Unwanted glitch in output due to input change.

• Resolution: Use redundant logic and analyze with timing diagrams and K-maps.
Digital Electronics Interview Guide 15

Combinational Circuits (Q71–Q80)

Q71. Explain how a 4-bit binary to Gray code converter can be designed
using logic gates. Derive the logic expressions and draw the truth table.
Asked in: Broadcom, Texas Instruments
Answer:
• Gray Code: Only one bit changes between two successive numbers.
• Logic Design:
G3 = B3
G2 = B3 ⊕ B2
G1 = B2 ⊕ B1
G0 = B1 ⊕ B0
where B3 B2 B1 B0 is binary input and G3 G2 G1 G0 is Gray output.
• Design each XOR operation using logic gates.

Q72. Given a 4-variable Boolean function, demonstrate step-by-step sim-

plification using Karnaugh Map and implement it using NAND gates only.
Asked in: Qualcomm, AMD
Answer: Let the function be:
X
F (A, B, C, D) = m(0, 1, 2, 5, 6, 7, 8, 9, 10, 14)

• Construct 4-variable K-map and group minterms.

• Simplify into SOP form using K-map.
• Convert the simplified SOP into NAND logic using double negation method.

Q73. Design a combinational logic system that outputs ’1’ if a 4-bit input
represents a prime number, else outputs ’0’. Include logic expression and
minimization strategy.
Asked in: Nvidia, STMicroelectronics
Answer:
• Valid 4-bit primes: 2, 3, 5, 7, 11, 13
• Inputs: A3 A2 A1 A0 , minterms = 2,3,5,7,11,13
• Use SOP form and K-map simplification to derive final expression

Q74. What are the limitations of a multiplexer when used for implement-
ing combinational functions? Propose a method to overcome them using
additional logic blocks.
Asked in: Texas Instruments, Google Hardware
Answer:
Digital Electronics Interview Guide 16

• Limitations:

– Limited number of select lines.

– Complex functions may require large MUX or hierarchical design.

• Solution:

– Use ROM-based lookup table for logic.

– Combine MUX with decoders or programmable devices.

Q75. A vending machine accepts only 1 and 2 rupee coins and issues a
product when the total reaches 5 rupees. Design a combinational logic circuit
that signals when to dispense the product.
Asked in: ARM, Samsung
Answer:

• Track all valid combinations to reach 5:

(1 + 1 + 1 + 1 + 1), (1 + 2 + 2), (2 + 1 + 2), etc.

• Implement combinational adders and comparators to track total.

• Output ’1’ when total = 5.

Q76. How can a full adder be implemented using only two half-adders and
one OR gate? Derive equations and explain its circuit design.
Asked in: Analog Devices, NXP Semiconductors
Answer:

• Half-Adder 1: Inputs: A, B → S1 = A ⊕ B, C1 = A · B

• Half-Adder 2: Inputs: S1 , Cin → Sum = S1 ⊕ Cin, C2 = S1 · Cin

• OR Gate: Cout = C1 + C2

Q77. Explain in detail how propagation delay impacts the performance of

combinational logic circuits. Support your answer with timing diagrams.
Asked in: Intel, MediaTek
Answer:

• Delay between input change and stable output.

• Can cause glitches in asynchronous systems.

• Addressed using:

– Hazard analysis
– Gate balancing
– Using faster gates
Digital Electronics Interview Guide 17

• Include sample timing diagram illustrating glitch

Q78. Compare and contrast PLA and PAL in terms of structure, flexibility,
and implementation complexity.
Asked in: ON Semiconductor, TI
Parameter PLA PAL
Structure Programmable AND and OR Fixed AND, Programmable OR
Answer: Flexibility More flexible Less flexible
Complexity More complex, customizable Faster, simpler
Speed Slightly slower Faster due to fixed logic

Q79. Describe the design and logic behind a seven-segment display de-
coder. Show truth table for BCD to 7-segment.
Asked in: Honeywell, Marvell Technology
Answer:

• Input: 4-bit BCD

• Output: 7-segment lines (a to g)

• Design combinational circuit for each segment based on BCD combinations.

• Create truth table and derive expressions using K-map.

Q80. You are given a combinational logic block with unknown function.
Explain how to reverse engineer the logic function using truth table generation
and Boolean simplification.
Asked in: Synopsys, Cadence Design Systems
Answer:

• Observe inputs and output combinations.

• Generate full truth table.

• Map output = 1 combinations → derive SOP.

• Simplify Boolean using K-map or algebraic identities.

• Test derived logic with real inputs to verify.

Digital Electronics Interview Guide 18

Combinational Circuits (Q81–Q100)

Q81. How do you implement a 5-input majority function using only 2-input
logic gates? Provide truth table and derive optimized Boolean equation.
Asked in: Intel, GlobalFoundries
Answer:

• Majority output is ‘1’ when at least 3 inputs are ‘1’.

• Total inputs = A, B, C, D, E

• Generate combinations where 3 or more inputs are ‘1’.

• Derive SOP, simplify using K-map, and implement with AND, OR, and NOT gates.

Q82. Design a digital comparator to compare two 4-bit binary numbers.

Explain how cascading can help in comparing larger bit numbers.
Asked in: Xilinx, Cadence
Answer:

• Comparator outputs: A = B, A ¿ B, A ¡ B

• Use bitwise comparison from MSB to LSB.

• Cascade multiple 4-bit comparators to handle 8-bit or 16-bit inputs.

Q83. Explain how an arithmetic circuit can be designed to perform both

addition and subtraction using control logic. Implement using full adders.
Asked in: Analog Devices, Infineon
Answer:

• Control signal (M): 0 for addition, 1 for subtraction

• Use 2’s complement logic for subtraction: Invert B and add 1

• Add M to Cin and B XOR M to the adder inputs

Q84. Construct a logic circuit that detects a parity error in a 5-bit input
using even and odd parity logic.
Asked in: Cisco, Altera
Answer:

• Even parity: XOR of all bits should be 0

• Odd parity: XOR of all bits should be 1

• Implement using XOR chain: P = A ⊕ B ⊕ C ⊕ D ⊕ E

Digital Electronics Interview Guide 19

Q85. You are asked to design a 3-bit binary to Excess-3 code converter.
Provide circuit diagram and logic expressions.
Asked in: Texas Instruments, Wipro VLSI
Answer:
• Excess-3 = Binary + 3

• Add ‘011’ to input using a 3-bit adder

• Implement using half and full adders or look-up K-map

Q86. Differentiate between a priority encoder and a regular encoder. De-

sign a 4-to-2 priority encoder with truth table and logic implementation.
Asked in: STMicroelectronics, Intel
Answer:
• Regular encoder: Only one input should be active

• Priority encoder: Resolves multiple active inputs based on priority

• Implement using logic:

Y1 = I3 + I2 , Y0 = I3 + I2 I1

Q87. What is a look-ahead carry adder? Explain its advantage over ripple
carry adder with logic and delay comparison.
Asked in: AMD, Microchip Technology
Answer:
• Ripple carry has linear delay; Look-ahead carry uses generate and propagate logic

• Carry generation: Gi = Ai · Bi , Pi = Ai ⊕ Bi

• Carries precomputed in parallel: faster

Q88. Design a circuit that detects whether the 4-bit binary input is divis-
ible by 3. Derive expression using Boolean algebra or state table.
Asked in: Qualcomm, Nvidia
Answer:
• Map all 4-bit inputs (0 to 15)

• Select inputs divisible by 3: 0, 3, 6, 9, 12, 15

• Create truth table and minimize with K-map

Q89. Explain the significance of hazards in combinational logic. Illustrate

static and dynamic hazards with an example and circuit diagram.
Asked in: Cadence, Synopsys
Answer:
Digital Electronics Interview Guide 20

• Static hazard: Output should remain constant but glitches

• Dynamic hazard: Multiple glitches due to transition

• Add redundant terms to remove hazard

• Show waveform illustrating glitch

Q90. A combinational circuit has 6 inputs and 1 output, and it acts as a

voting machine where output is ‘1’ if more than half inputs are ‘1’. Design
the logic circuit.
Asked in: IBM, Cypress Semiconductor
Answer:

• Output = ‘1’ if number of 1’s 4

• Derive function by summing all 6-bit combinations with 4 ones

• Minimize using SOP/K-map

Q91–Q100: Extended Design and Logical Reasoning Based

Q91. Construct a logic system that determines whether a 4-digit BCD input is palin-
dromic. (i.e., same forwards and backwards)
Q92. Implement a 3-input comparator with outputs indicating equality, greater than, or
less than using minimum number of gates.
Q93. Design a combinational circuit to detect a 4-bit Gray code input and convert it
back to binary. Show conversion logic.
Q94. Explain the principle behind the implementation of arithmetic logic unit (ALU)
using multiplexers and full adders.
Q95. Derive the logic to detect an overflow condition in a 4-bit adder-subtractor unit
using sign bits.
Q96. Design a binary-to-thermometer code converter for 3-bit input using combinational
logic.
Q97. Show how a priority encoder and a decoder can be combined to implement a 2-level
priority arbiter.
Q98. Create a logic circuit to detect if any two or more inputs are active high simulta-
neously in an 8-input system.
Q99. Implement a real-time digital safe-lock system logic that grants access only on a
specific sequence of inputs.
Q100. Discuss the concept of gate minimization and Boolean reduction in designing
power-efficient combinational circuits.
Digital Electronics Interview Guide 21

Sequential Circuits (Q101–Q130)

Q101. What is the fundamental difference between a latch and a flip-flop?

Explain using logic diagrams and timing behavior.
Asked in: Intel, Qualcomm
Answer: A latch is level-triggered while a flip-flop is edge-triggered. Latches change
output based on the level of the clock (high or low), whereas flip-flops only change output
on clock edges (rising or falling). Flip-flops are more predictable in synchronous systems,
reducing timing errors.

Q102. Design a D flip-flop using NAND gates only. Show truth table,
circuit diagram and explain working.
Asked in: AMD, Cadence
Answer: A D flip-flop can be built by modifying an SR latch. A D flip-flop eliminates
the invalid state by ensuring only one input. The D input is connected to one NAND
gate, and its complement to another. On clock edge, the gated SR latch stores the D
value.

Q103. Derive the characteristic equation of a JK flip-flop and explain how

it differs from D and T flip-flops.
Asked in: Broadcom, Texas Instruments
Answer: Characteristic equation: Qnext = J Q̄ + K̄Q. JK flip-flops can toggle, hold, set,
or reset depending on inputs. D flip-flop has a single data input (Q = D), while T toggles
on every clock if T = 1.

Q104. Explain race-around condition in JK flip-flops and how master-slave

configuration avoids it.
Asked in: Synopsys, Microchip
Answer: Race-around occurs when J=K=1 and clock is high long enough to toggle
repeatedly. Master-slave uses two flip-flops; master captures on clock high, slave updates
on clock low, thus avoiding continuous toggling.

Q105. Design a 4-bit synchronous binary counter using T flip-flops. Draw

timing diagram and logic diagram.
Asked in: Intel, STMicroelectronics
Answer: All flip-flops share the same clock. Each T flip-flop toggles when all previous
outputs are 1. Connect Q outputs of previous flip-flops to T input of next.

Q106. What are metastability issues in flip-flops? How do you handle

them in real-time digital systems?
Asked in: Cisco, Google Hardware
Answer: Metastability happens when input changes close to clock edge, causing uncer-
tain output. It is handled using synchronizer chains (2-3 flip-flops in series) and proper
timing constraints.

Q107. Compare asynchronous and synchronous counters. Discuss advan-

tages, disadvantages and timing diagrams.
Digital Electronics Interview Guide 22

Asked in: Xilinx, Altera

Answer: Asynchronous: Ripple effect, slower due to propagation delays. Synchronous:
All flip-flops triggered simultaneously, faster and more reliable.

Q108. Design a sequence detector for the pattern “1011” using Mealy and
Moore machines. Provide state diagrams.
Asked in: Qualcomm, Marvell
Answer: Moore: Output depends on state; Mealy: depends on input and state. Define
states for partial matches, transition accordingly, and output when sequence is detected.

Q109. What is the difference between hold time and setup time? Explain
using waveform.
Asked in: Analog Devices, AMD
Answer: Setup time: Data must be stable before clock edge. Hold time: Must remain
stable after clock. Violations lead to metastability.

Q110. Explain the design of a modulo-6 counter using JK flip-flops. How

will you reset at the right count?
Asked in: Lattice Semiconductor, Infineon
Answer: Count 0 to 5. On 6 (110), use AND gates to detect and reset flip-flops to 000.
Connect this reset logic to asynchronous clear input.

Q111. Design a shift register that performs left, right and parallel load
operations. Include control logic.
Asked in: Microsemi, Texas Instruments
Answer: Use multiplexers at input of each flip-flop. Control signals determine mode.
Left shift: feed from next; Right shift: feed from previous; Load: take external input.

Q112. What is the role of clock skew in sequential circuits? How does it
affect performance and correctness?
Asked in: Synopsys, Intel
Answer: Clock skew: Difference in arrival time of clock at flip-flops. Positive skew may
help hold violations but hurt setup. Managed using clock trees and buffers.

Q113. Design a 3-bit Johnson counter. Provide waveform and explain

working.
Asked in: Broadcom, Nvidia
Answer: Feedback from inverted MSB to LSB. Sequence: 000 → 100 → 110 → 111 →
011 → 001 → 000. Uses D flip-flops and NOT gate.

Q114. How do ring counters differ from Johnson counters? Compare with
state diagrams.
Asked in: Marvell, Infineon
Answer: Ring: Feedback from last to first, only one ‘1’ circulates. Johnson: Comple-
mented MSB to LSB, double the states. Ring has n states, Johnson has 2n.

Q115. Create a state table and diagram for a traffic light controller with
three states: Red, Yellow, Green.
Digital Electronics Interview Guide 23

Asked in: Philips Semiconductors, Bosch

Answer: States: R → G → Y → R. Use two FFs to encode states (00, 01, 10). Transition
on clock pulse.

Q116. Explain the function of enable signal in flip-flops and how it affects
data storage.
Asked in: Cypress, Qualcomm
Answer: Enable controls when input data is sampled. Acts like a gate. When disabled,
no change in output regardless of input.

Q117. Design a frequency divider that divides input clock by 8. Show

timing and FF arrangement.
Asked in: Texas Instruments, STMicro
Answer: Use 3 T flip-flops connected in series. Each divides clock by 2. Output of last
gives ÷8 signal.

Q118. Compare Mealy and Moore machines in terms of latency, complexity

and resource usage.
Asked in: Nvidia, Google
Answer: Mealy: Less states, faster response (output depends on input). Moore: Stable
output, more states. Moore easier to design.

Q119. What are synchronous and asynchronous inputs in flip-flops? Give

examples.
Asked in: Intel, AMD
Answer: Synchronous: Respond on clock (enable, load). Asynchronous: Act immedi-
ately (reset, preset). Used in power-up or emergency stop.

Q120. Explain the concept of finite state machine (FSM). How does it
apply to sequential circuit design?
Asked in: Marvell, Synopsys
Answer: FSM models system behavior with states, transitions, inputs and outputs.
Helps break down complex logic into manageable steps.

Q121–Q130: Higher-Order Questions

Q121. Design a synchronous up-down counter and explain the mode control logic.
Q122. Implement a binary to Gray code converter using sequential logic.
Q123. Discuss the role of flip-flops in pipelined processor design.
Q124. Explain how you can store multiple bits using a single flip-flop with control logic.
Q125. Design a pulse generator using monostable multivibrator logic.
Q126. Explain clock gating and its role in power optimization.
Q127. Show the difference in timing diagram when using SR vs D flip-flop.
Q128. Explain programmable counter implementation in FPGA using HDL.
Q129. How would you test a sequential circuit for stuck-at faults?
Q130. Derive the transition table from a given state diagram of a Moore machine.
Digital Electronics Interview Guide 24

Sequential Circuits (Q131–Q140)

Q131. Design a 4-bit universal shift register and explain its working modes
(hold, shift left, shift right, parallel load) using logic diagram and control ta-
ble.
Asked in: Intel, Texas Instruments
Answer: A 4-bit universal shift register is a combination of four D flip-flops with ad-
ditional multiplexers at the input of each flip-flop. The multiplexer selects among four
operations:
- Hold (00): Current value is fed back to the D input.
- Shift Left (01): Each flip-flop receives the output from the right neighbor.
- Shift Right (10): Each flip-flop receives the output from the left neighbor.
-Parallel Load (11): Input data is directly loaded into flip-flops.
Each mode is selected using control inputs S1 and S0. The outputs are updated on the
clock edge.

Q132. What is a Moore finite state machine? Design a Moore FSM to

detect the sequence “1101” with overlapping allowed. Show state diagram,
table, and logic expression.
Asked in: Qualcomm, Xilinx
Answer: In a Moore machine, the output depends only on the current state, not the
input. To detect “1101”: - States: S0 (start), S1 (‘1’), S2 (‘11’), S3 (‘110’), S4 (‘1101’
detected).
- Transitions: - S0 → S1 on 1
- S1 → S2 on 1
- S2 → S3 on 0
- S3 → S4 on 1 - The FSM allows overlap, so from S4 we go back to S2 if next input is
1. - Output is ‘1’ only in S4. A table maps each state and input to the next state, and
outputs. Boolean logic is derived from the encoded states and transitions.

Q133. Explain the role of metastability in asynchronous data transfer

between clock domains. How is it mitigated in ASIC design?
Asked in: AMD, Broadcom
Answer: Metastability occurs when a flip-flop’s input changes too close to the clock edge,
resulting in undefined output levels. This is common during asynchronous data transfer.
To mitigate: - Use a two-stage synchronizer (two flip-flops in series), which increases the
probability of resolving metastability before data is used. - Implement handshaking or
FIFO buffers for multi-bit or burst transfers. - Set conservative timing constraints and
use Gray coding for multi-bit counters to avoid simultaneous bit changes.

Q134. What are the advantages and disadvantages of using a Mealy ma-
chine over a Moore machine in sequential logic?
Asked in: Synopsys, Marvell
Answer: Advantages of Mealy - Requires fewer states, making state machine simpler.
- Faster response to input changes as outputs can change without waiting for a state
transition.
Disadvantages: - Output glitches possible due to direct input dependency. - Harder to
Digital Electronics Interview Guide 25

test and debug due to tighter input-output coupling. In contrast, Moore outputs are
more stable but may require more states.

Q135. Design a modulo-12 counter using synchronous logic. What is the

minimum number of flip-flops required and how do you reset the counter
correctly?
Asked in: Microchip, NXP
Answer: A modulo-12 counter counts from 0 to 11 (decimal), which is 0000 to 1011
(binary). - Needs at least 4 flip-flops (as 24 = 16). - Reset on count 1100 (12), which
is done by detecting 1100 using AND gates and resetting all FFs asynchronously or
synchronously. Design can be implemented using T or JK FFs with logic for toggling
and reset circuitry.

Q136. Explain clock gating technique in sequential circuits. How does it

help in reducing power consumption in ASICs?
Asked in: ARM, Texas Instruments
Answer: Clock gating involves disabling the clock to portions of a circuit when they
are not in use. This prevents unnecessary switching activity, reducing dynamic power
consumption. In ASIC design: - Gating logic is placed before the clock input of flip-flops.
- Controlled via enable signals. - Special care is taken to avoid glitches using integrated
gating cells. It’s one of the most effective RTL-level power-saving techniques in modern
SoC design.

Q137. Design a circuit that divides a 100 MHz clock to 1 MHz using flip-
flops. How many flip-flops are needed and why?
Asked in: Intel, Nvidia
Answer:
To divide 100 MHz to 1 MHz: 100 MHz
1 MHz
= 100, so a divide-by-100 circuit is needed.

- Use a 7-bit counter (since 27 = 128 > 100). - Count from 0 to 99 (mod-100). On
count 99, reset the counter and toggle the output flip-flop. This design provides a precise
1 MHz clock from 100 MHz input using digital logic.

Q138. What is the importance of setup and hold time violations in se-
quential circuits? How are these analyzed in timing verification?
Asked in: Cadence, Synopsys
Answer: Setup time: Data must be stable before the clock edge. Hold time: Data must
remain stable after the clock edge. Violations: - Setup violation can cause incorrect data
to be latched.
- Hold violation causes metastability. Analyzed using Static Timing Analysis (STA).
Tools like PrimeTime report paths where timing constraints are violated. Designers re-
solve them by adjusting logic delays or clock skew.

Q139. Explain the difference between level-sensitive and edge-triggered

flip-flops with practical applications.
Asked in: STMicroelectronics, Analog Devices
Answer: **Level-sensitive** latches respond to input as long as clock is active (high or
low level). Used in asynchronous or latch-based designs. Edge-triggered flip-flops respond
Digital Electronics Interview Guide 26

only at clock edges (rising/falling). Applications: - Edge-triggered FFs are common in

synchronous FSMs and counters. - Level-sensitive latches are used in pipelines for timing
optimization or high-speed ASIC paths.

Q140. What is the difference between an asynchronous FIFO and a syn-

chronous FIFO? Where would you use each?
Asked in: Qualcomm, Broadcom
Answer: Synchronous FIFO: Both write and read use same clock. Easier to design and
verify.
Asynchronous FIFO: Write and read have independent clocks.
Used in: - Synchronous FIFO for single-clock domain systems. - Asynchronous FIFO
in clock domain crossing (CDC) applications, e.g., SoC block communication, UART
buffers. Special techniques like Gray code pointers and synchronizers are used to ensure
reliability in asynchronous FIFOs.

Sequential Circuits: Q151–Q160

Q151. Explain the concept of metastability in flip-flops. How do designers
mitigate it in clock domain crossing?
Asked in: Xilinx, Nvidia
Answer: Metastability is a condition where a flip-flop enters an undefined state due
to setup/hold violations, especially in asynchronous data sampling. It results in unpre-
dictable output and can propagate errors in the system.

• Occurs when input changes near the clock edge.

• Output hovers between logic 0 and 1 for an undefined duration.

Mitigation Techniques:

• Using synchronizer chains: Typically two or more flip-flops in series in the

receiving clock domain.

• Asynchronous FIFO with Gray code: Used in data transfer across clock do-
mains.

• Handshaking protocols: Used for reliable communication.

Q152. Draw and explain the Mealy and Moore state machines. Which one
is preferred and why?
Asked in: AMD, Synopsys
Answer:
Moore Machine: Mealy Machine:

• Output depends only on current • Output depends on current state

state. and input.

• More stable output. • Faster response to inputs.

Digital Electronics Interview Guide 27

Feature Moore Mealy

Output depends on State State + Input
Output timing Synchronized with clock Immediate
Hardware complexity More states Fewer states

Q153. Design a mod-6 synchronous counter using T flip-flops.

Asked in: Qualcomm, Broadcom
Answer: A mod-6 counter counts from 0 to 5 (6 states).

• Minimum flip-flops = ⌈log2 6⌉ = 3

• Use T flip-flops with excitation table.

• Design logic equations using Karnaugh maps.

Q154. Explain the function and importance of setup and hold times in
sequential circuits.
Asked in: Intel, ARM
Answer:

• Setup Time: Minimum time input should be stable before the clock edge.

• Hold Time: Minimum time input should remain stable after the clock edge.

Violation leads to: Metastability, incorrect data sampling.

Q155. Design a finite state machine (FSM) that detects a sequence ‘1011’.
Use Mealy model.
Asked in: STMicro, Texas Instruments
Answer: 5 states are required. Output = 1 when pattern is detected.
States:

• S0: Start

• S1: Detected ‘1’

• S2: Detected ‘10’

• S3: Detected ‘101’

• S4: Detected ‘1011’

Q156. What are hazards in sequential logic? Explain static and dynamic
hazards.
Asked in: Lattice Semiconductor
Answer:

• Hazards: Unwanted switching due to propagation delay mismatches.

• Static Hazard: Output temporarily toggles when it should remain constant.

• Dynamic Hazard: Multiple toggles before settling to final output.

Digital Electronics Interview Guide 28

Q157. Why are Gray codes preferred in asynchronous counters and data
transfer?
Asked in: Western Digital, Seagate
Answer:
• Only one bit changes between consecutive values — prevents glitches.
• Ideal for clock domain crossing and rotary encoders.

Q158. Compare Johnson counter and Ring counter.

Asked in: AMD, CDAC

Feature Johnson Counter Ring Counter

States 2n n
Feedback Inverted output fed to input Last output to first input
Applications Timing generation Sequence detection

Q159. Design a universal shift register and explain its operation modes.
Asked in: Google Hardware, Marvell
Answer:
• Modes: Shift left, Shift right, Parallel load, No change
• 4x1 MUX used for each flip-flop input to select mode
Diagram: Use 4 D flip-flops connected through MUX logic
Q160. Explain Clock Gating and how it helps in low-power VLSI design.
Asked in: MediaTek, Apple
Answer:
• Disables clock to inactive modules to reduce switching power
• Saves dynamic power
• Implemented using AND gates with enable signals
Diagram:
Clock
AND Gated Clock
Enable

Sequential Logic Questions (161–170)

161. What is a sequential circuit?
Answer: A sequential circuit is a type of digital circuit where the output depends not
only on the present input but also on the history of inputs. This is due to the presence
of memory elements (like flip-flops) that store the previous state of the circuit. Examples
include flip-flops, registers, counters, etc.
—
Digital Electronics Interview Guide 29

162. What is the difference between combinational and sequen-

tial circuits?
Answer:
Feature Combinational Circuit
Dependence on Inputs Output depends only on current inputs. Output d
Memory No memory elements. Cont
State No states, always outputs the result of the input combination. Outpu
Example Adders, multiplexers, decoders.
—

163. What is the operation of a D flip-flop?

Answer: A D flip-flop (Data flip-flop) stores the value of the input D on the rising edge
of the clock. When the clock signal is triggered, the output Q takes the value of D. It has
the property that the output Q follows the input D only during the clock edge transition.
—

164. What is a JK flip-flop?

Answer: A JK flip-flop is a type of flip-flop that has two inputs: J and K. Its operation
is similar to a T flip-flop but with more flexibility:
• When J = 0 and K = 0, the output does not change.

• When J = 0 and K = 1, the output is reset (Q = 0).

• When J = 1 and K = 0, the output is set (Q = 1).

• When J = 1 and K = 1, the output toggles.

—

165. Explain the operation of a T flip-flop.

Answer: A T flip-flop (Toggle flip-flop) has a single input, T. The output Q toggles its
state (changes from 0 to 1 or 1 to 0) whenever the input T = 1 on the triggering edge of
the clock. If T = 0, the output does not change.
—

166. What is a shift register?

Answer: A shift register is a sequential circuit that stores multiple bits and shifts them
through its flip-flops in response to clock pulses. There are different types of shift registers:
• Serial-in, Serial-out (SISO): Bits are input and output one by one.

• Serial-in, Parallel-out (SIPO): Bits are input serially, but all outputs are avail-
able simultaneously.

• Parallel-in, Serial-out (PISO): Multiple bits are input simultaneously, but the
output is serial.
Digital Electronics Interview Guide 30

• Parallel-in, Parallel-out (PIPO): Multiple bits are input and output simulta-
neously.

167. What is the function of a counter?

Answer: A counter is a sequential circuit that increments or decrements its output in
response to clock pulses. Counters can be up counters (increment), down counters
(decrement), or up/down counters (both increment and decrement). Counters are
commonly used in applications like frequency division, timing, and sequencing.
—

168. What is the difference between a synchronous and an asyn-

chronous counter?
Answer:

• Synchronous Counter: All flip-flops in the counter are triggered by the same
clock signal, which ensures that all flip-flops change state simultaneously.

• Asynchronous Counter: The flip-flops are triggered by different clock signals.

The clock of one flip-flop triggers the clock of the next flip-flop, causing a ripple
effect where the output of each flip-flop changes at different times.

169. Explain the operation of a 4-bit binary counter.

Answer: A 4-bit binary counter can count from 0 to 15. It has 4 flip-flops, each storing
1 bit of information. When a clock pulse is applied, the counter increments by 1 on each
pulse, transitioning through binary values. For example, starting from 0000, it will count
up to 1111.
—

170. What is a Johnson counter?

Answer: A Johnson counter is a type of shift counter in which the output of the last
flip-flop is fed back to the input of the first flip-flop, causing the counter to generate a
”walking” or ”rotating” pattern. In a 4-bit Johnson counter, the pattern repeats every 8
clock pulses. The counter generates a sequence like:

0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001

This counter is also known as a ”twisted ring counter.”

Digital Electronics Interview Guide 31

Sequential Logic Questions (171–180)

171. What is a race condition in sequential circuits?
Answer: A race condition occurs when the output of a sequential circuit depends on
the relative timing of two or more input signals. If the inputs change at almost the same
time, the final output may be unpredictable because the circuit might ”race” between
different states. This can lead to malfunction in the system.
—

172. Explain the concept of metastability in sequential circuits.

Answer: Metastability occurs when a flip-flop or latch enters a state where it is unable
to resolve to a stable high or low value within the required time frame. This typically
happens when the input to a flip-flop changes asynchronously, and the flip-flop does not
have enough time to settle to a valid state. Metastability can result in glitches or incorrect
outputs in the system.
—

173. What is a frequency divider?

Answer: A frequency divider is a sequential circuit that divides the input frequency by
a fixed factor. It typically uses a flip-flop to divide the frequency of a clock signal. For
example, a divide-by-2 frequency divider takes an input clock of frequency f and outputs
a clock signal with frequency f2 . More complex dividers can divide the input frequency
by higher factors.
—

174. What is a Moore state machine?

Answer: A Moore state machine is a type of finite state machine where the outputs
depend only on the current state, not on the inputs. The outputs change when the state
transitions. In a Moore machine, every state is associated with a fixed output value, and
the transition from one state to another is determined by the inputs.
—

175. What is a Mealy state machine?

Answer: A Mealy state machine is a type of finite state machine where the outputs
depend on both the current state and the inputs. In a Mealy machine, the output can
change immediately when the input changes, allowing for faster responses compared to a
Moore machine, where the output only changes on a state transition.
—

176. What is a state diagram?

Answer: A state diagram is a graphical representation of a state machine. It shows
the states, the transitions between states, and the conditions under which the transitions
Digital Electronics Interview Guide 32

occur. The diagram helps visualize the operation of a sequential circuit and is essential
in designing both Moore and Mealy state machines.
—

177. What is a state table?

Answer: A state table is a tabular representation of a finite state machine that lists
all possible states, inputs, and the corresponding next state and output for each input
combination. It is used to describe the behavior of sequential circuits and to derive the
necessary logic equations for the circuit.
—

178. How do you convert a state diagram to a state table?

Answer: To convert a state diagram to a state table:

• List all the states of the system.

• Identify the inputs that trigger transitions.

• For each combination of state and input, determine the next state and the corre-
sponding output.

• Fill the state table with this information, including current state, input, next state,
and output.

179. What is the difference between synchronous and asyn-

chronous reset in sequential circuits?
Feature Synchronous Reset
Timing Reset is synchronized with the clock.
Answer: Usage Requires clock to be active for the reset to take effect.
Reliability More reliable as the reset state is guaranteed to occur on the clock edge.
Implementation Requires an additional logic for synchronization.
—

180. What is the function of a clock in sequential circuits?

Answer: The clock in sequential circuits provides the timing signal that controls the
synchronization of state transitions in flip-flops, latches, and other memory elements.
The clock ensures that all parts of the circuit change their state in a coordinated manner.
It typically provides periodic pulses, with the state of the sequential circuit changing on
the rising or falling edge of the clock.
Digital Electronics Interview Guide 33

Sequential Logic Questions (181–200)

181. What is the function of a flip-flop in a sequential circuit?
Answer: A flip-flop is a basic memory element in sequential circuits that stores one
bit of information. It has two stable states and can change state based on clock inputs
and other control signals. Flip-flops are used in storing data, state transitions, and clock
division in digital systems.
—

182. Explain the difference between a flip-flop and a latch.

Feature Flip-Flop
Clocking Edge-triggered (changes state on clock edges). Level-sensitive (changes sta
Answer: Usage Suitable for synchronous circuits. Suitable for a
Stability More stable in terms of timing. Less stable
Design Complex and typically used in high-speed designs. Simpler, often use
—

183. What is the role of a D flip-flop in sequential circuits?

Answer: A D flip-flop is a type of flip-flop that has a single data input (D) and stores
the value of the D input on the rising (or falling) edge of the clock. It is widely used in
registers, memory elements, and data storage applications. The value of the D input is
transferred to the output Q on each clock edge, ensuring reliable data storage.
—

184. How does an SR latch work?

Answer: An SR latch is a basic storage element made using NOR or NAND gates. It
has two inputs: Set (S) and Reset (R). The latch maintains its state until the Set or Reset
inputs are activated. The latch is asynchronous and does not require a clock. When S is
high, the latch sets the output to 1, and when R is high, it resets the output to 0.
—

185. What is the significance of a clocked SR flip-flop?

Answer: A clocked SR flip-flop is a type of flip-flop that behaves similarly to the SR
latch but has an additional clock input. The flip-flop changes state only when the clock
signal is active, making it synchronous. This ensures that the state changes occur in a
coordinated manner with the system clock.
—

186. What is a JK flip-flop, and how is it different from a D

flip-flop?
Answer: A JK flip-flop is a more versatile flip-flop than the D flip-flop. It has two
inputs: J and K. The JK flip-flop can toggle between states, set, or reset, depending on
Digital Electronics Interview Guide 34

the input conditions. It avoids the invalid state problem present in the SR flip-flop. The
primary difference is that a D flip-flop stores the value of the data input, while a JK
flip-flop has a more complex behavior based on the J and K inputs.
—

187. Explain the working of a T flip-flop.

Answer: A T flip-flop is a type of flip-flop that toggles its state with every clock pulse
when the T input is high. If the T input is low, the flip-flop maintains its current state.
It is commonly used in frequency division and counting circuits because it changes state
on every clock edge when enabled.
—

188. What is a 4-bit shift register?

Answer: A 4-bit shift register is a sequential circuit that stores 4 bits of data and shifts
them either to the left or right with each clock pulse. It can be used to convert parallel
data to serial data or vice versa. The shift register can also be configured as a serial-
in, serial-out (SISO), parallel-in, parallel-out (PIPO), serial-in, parallel-out (SIPO), or
parallel-in, serial-out (PISO) register.
—

189. What is the difference between a synchronous counter and

an asynchronous counter?
Feature Synchronous Counter Asynchron
Clocking All flip-flops receive the clock signal simultaneously. Flip-flops receive clock
Answer:
Speed Faster because all flip-flops are synchronized. Slower due
Complexity Requires additional logic for synchronization. Simpler bu
—

190. What is a Johnson counter?

Answer: A Johnson counter is a type of shift register that cycles through a sequence of
states by shifting a bit pattern in a way that every new state is the complement of the
previous state. It is also called a ”twisted ring counter” and is used in applications where
a known, fixed sequence of states is required.
—

191. What is a ring counter?

Answer: A ring counter is a type of counter in which the output of the last flip-flop is
fed back to the input of the first flip-flop. The counter rotates through a set of states,
with only one flip-flop being active (high) at any time. Ring counters are commonly used
in control systems and sequence generation.
—
Digital Electronics Interview Guide 35

192. How does a binary counter work?

Answer: A binary counter is a sequential circuit that counts in binary, incrementing
its value by one with each clock pulse. It typically uses a series of flip-flops where each
flip-flop represents a bit in the binary number. The counter increments its value from
0000 to 1111 (for a 4-bit counter), resetting to 0000 after reaching the maximum value.
—

193. Explain the working of a 3-bit binary counter.

Answer: A 3-bit binary counter has 3 flip-flops and can count from 000 to 111 in binary.
Each flip-flop represents one bit, and each clock pulse increments the counter. The counter
is designed to roll over to 000 after reaching 111. The counter’s output changes state
with every clock pulse, producing a binary sequence from 000 to 111 and repeating.
—

194. What is a BCD counter?

Answer: A BCD (Binary-Coded Decimal) counter is a sequential circuit that counts
in decimal (0-9) and stores each decimal digit in binary format. It uses a 4-bit binary
counter to represent each decimal digit. The counter can represent decimal numbers from
0 to 9 in binary form, and once it exceeds 9, it resets to 0.
—

195. What is a ripple counter?

Answer: A ripple counter, also known as an asynchronous counter, is a type of counter
where each flip-flop is clocked by the previous flip-flop in the chain. The counter ”ripples”
from one flip-flop to the next, which causes the propagation delay and reduces the speed
of the counter. It is simpler to design but slower than synchronous counters.
—

196. How does a frequency divider work?

Answer: A frequency divider is a sequential circuit that reduces the frequency of the
input clock by a certain factor. It typically uses a flip-flop to divide the frequency by
2. For example, a divide-by-2 frequency divider takes an input clock with frequency f
and produces an output clock with frequency f2 . More complex dividers can divide the
frequency by higher factors.
—

197. What is a shift-and-add multiplier?

Answer: A shift-and-add multiplier is a binary multiplication algorithm that repeatedly
shifts the multiplicand and adds it to an accumulator based on the bits of the multiplier.
It is a sequential process where, for each bit in the multiplier, the multiplicand is shifted
and added to the result. This method is commonly used in hardware multipliers.
—
Digital Electronics Interview Guide 36

198. What is an up/down counter?

Answer: An up/down counter is a type of counter that can count in both directions,
either incrementing (up) or decrementing (down) its value based on a control input. It
uses the same flip-flops as a binary counter, but the direction of counting is controlled by
an additional control signal.
—

199. What is a synchronous load counter?

Answer: A synchronous load counter is a type of counter where the counter value can
be loaded synchronously based on an external control signal. The load operation allows
the counter to be preset to a specific value, which is useful in applications where a known
starting value is required.
—

200. What is a counter with a carry-out feature?

Answer: A counter with a carry-out feature is a type of counter that generates a carry-
out signal when the counter overflows (i.e., reaches its maximum count and resets to
zero). This carry-out signal can be used to trigger other circuits or to indicate that the
counter has reached its limit. It is commonly used in applications requiring chaining of
multiple counters.

Number System and Boolean Algebra Questions (201–250)

201. What is the binary equivalent of the decimal number 45?
Answer: To convert decimal 45 to binary, we divide the number by 2 and record the
remainders:

45÷2 = 22 remainder 122÷2 = 11 remainder 011÷2 = 5 remainder 15÷2 = 2 remainder 12÷2 = 1 rem

Now, reading the remainders from bottom to top, we get the binary equivalent:

4510 = 1011012

202. Convert the binary number 1101 to its decimal equivalent.

Answer: To convert binary 1101 to decimal, we multiply each digit by 2n , where n is
the position of the digit from right to left starting from 0:

1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 8 + 4 + 0 + 1 = 13

Thus, the decimal equivalent of 11012 is 1310 .

—
Digital Electronics Interview Guide 37

203. What is the hexadecimal representation of the decimal num-

ber 254?
Answer: To convert decimal 254 to hexadecimal, divide the number by 16 and record
the remainders:
254 ÷ 16 = 15 remainder 14
The remainder 14 corresponds to the hexadecimal digit ’E’. The quotient 15 corresponds
to the hexadecimal digit ’F’. Therefore:
25410 = F E16
—

204. Convert the binary number 1010101 to octal.

Answer: Group the binary number in groups of three bits starting from the right:
10101012 = 001 010 101
Now, convert each group to its octal equivalent:
0012 = 18 , 0102 = 28 , 1012 = 58
Thus, the octal equivalent of 10101012 is 1258 .
—

205. What is the binary addition of 1011 and 1101?

Answer: Performing binary addition:
1011
+1101
11000
Thus, the sum of 10112 and 11012 is 110002 .
—

206. What is the Boolean expression for the AND operation?

Answer: The Boolean AND operation is represented by the symbol ·. The operation
results in true (1) only when both inputs are true:
A · B = 1 if and only if A = 1 and B = 1
Thus, the Boolean expression for AND is simply A · B.
—

207. How does the OR operation in Boolean algebra work?

Answer: The Boolean OR operation is represented by the symbol +. The operation
results in true (1) when at least one of the inputs is true:
A + B = 1 if A = 1 or B = 1
Thus, the Boolean expression for OR is A + B.
—
Digital Electronics Interview Guide 38

208. What is the complement of the Boolean expression A · B?

Answer: By De Morgan’s law, the complement of a product (AND operation) is the
sum (OR operation) of the complements of the individual terms:
A·B =A+B
Thus, the complement of A · B is A + B.
—

209. What is the Boolean expression for the XOR operation?

Answer: The Boolean XOR (exclusive OR) operation results in true (1) when exactly
one of the inputs is true:
A ⊕ B = (A · B) + (A · B)
Thus, the Boolean expression for XOR is A ⊕ B.
—

210. What is the truth table for the OR operation?

Answer: The truth table for the OR operation is as follows:
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
Thus, the OR operation returns 1 when at least one input is 1.
—

211. What is the truth table for the AND operation?

Answer: The truth table for the AND operation is as follows:
A B A·B
0 0 0
0 1 0
1 0 0
1 1 1
Thus, the AND operation returns 1 only when both inputs are 1.
—

212. What is the Boolean simplification of A + A · B?

Answer: Using the absorption law in Boolean algebra:
A+A·B =A
Thus, the simplified Boolean expression is A.
—
Digital Electronics Interview Guide 39

213. What is the simplified Boolean expression for A + B?

Answer: Using De Morgan’s law:

A+B =A·B

Thus, the simplified Boolean expression is A · B.

—

214. What is the result of A · A?

Answer: The result of A · A is always 0, as A and its complement A cannot both be 1
at the same time:
A·A=0
—

215. What is the simplification of the expression A + A?

Answer: The simplification of A + A is always 1, as one of them must be true:

A+A=1

216. What is the Boolean expression for the NAND operation?

Answer: The Boolean NAND operation is the complement of the AND operation:

A NAND B = A · B

217. What is the Boolean expression for the NOR operation?

Answer: The Boolean NOR operation is the complement of the OR operation:

A NOR B = A + B

218. What is the simplification of A · 1?

Answer: The simplification of A · 1 is A, as any variable ANDed with 1 remains the
same:
A·1=A
—
Digital Electronics Interview Guide 40

219. What is the simplification of A + 0?

Answer: The simplification of A + 0 is A, as any variable ORed with 0 remains the
same:
A+0=A
—

220. What is the Boolean expression for the XNOR operation?

Answer: The Boolean XNOR operation is the complement of XOR. It can be expressed
as:
A ⊙ B = A ⊕ B = (A · B) + (A · B)
—

221. What is the complement of the Boolean expression A·B +C?

Answer: By De Morgan’s law:

A · B + C = A · B · C = (A + B) · C

222. What is the Boolean expression for A · (B + C)?

Answer: The Boolean expression for A · (B + C) is already in simplified form and does
not require further simplification.
—

223. What is the simplification of A + A · B?

Answer: Using the absorption law:

A+A·B =A

224. What is the truth table for the NAND operation?

Answer: The truth table for the NAND operation is as follows:

A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0
—
Digital Electronics Interview Guide 41

225. What is the Boolean simplification of A + A · B + A · C?

Answer: The simplification of this expression uses the consensus theorem:

A+A·B+A·C =A

226. What is the simplified Boolean expression for A · B + C?

Answer: By applying De Morgan’s law:

A · B + C = A · B · C = (A + B) · C

227. What is the truth table for the XOR operation?

Answer: The truth table for the XOR operation is as follows:
A B A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
—

228. How is the Boolean function A ⊕ B ⊕ C simplified?

Answer: The XOR operation is associative, so the function A ⊕ B ⊕ C is equivalent to:

(A ⊕ B) ⊕ C

This can be simplified further if specific values of A, B, and C are known.

—

229. What is the truth table for the NOR operation?

Answer: The truth table for the NOR operation is as follows:
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0
—

230. How would you simplify the Boolean expression A · (B + C)?

Answer: The expression A · (B + C) is already in its simplest form.
—
Digital Electronics Interview Guide 42

231. What is the simplification of A + A · B + B?

Answer: Using the absorption law:

A+A·B+B =A+B

232. What is the Boolean complement of A + B?

Answer: Using De Morgan’s law:

A+B =A·B

233. What is the Boolean expression for A + B + C?

Answer: Using De Morgan’s law:

A+B+C =A·B·C

234. How can you simplify the expression A + A · B?

Answer: Using the absorption law:

A+A·B =A

235. What is the simplification of A · B + A · B?

Answer: Using the distributive property:

A·B+A·B =A

236. What is the Boolean expression for the AND of three vari-
ables A, B, and C?
Answer: The Boolean expression for the AND of three variables is:

A·B·C

—
Digital Electronics Interview Guide 43

237. What is the Boolean expression for the OR of three vari-

ables A, B, and C?
Answer: The Boolean expression for the OR of three variables is:

A+B+C

238. What is the truth table for the AND operation with three
variables?
Answer: The truth table for the AND operation with three variables is as follows:

A B C A·B·C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
—

239. What is the Boolean simplification of A + A · B + C?

Answer: Using the absorption law:

A+A·B+C =A+C

240. What is the Boolean expression for the OR operation with

three variables A, B, and C?
Answer: The Boolean expression for the OR operation with three variables is:

A+B+C

—
Digital Electronics Interview Guide 44

241. What is the truth table for the AND operation with four
variables?
Answer: The truth table for the AND operation with four variables is as follows:

A B C D A·B·C ·D
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
—

242. What is the Boolean expression for the NAND operation

with three variables A, B, and C?
Answer: The Boolean expression for the NAND operation with three variables is:

A·B·C

and then complemented:

A·B·C
—
Digital Electronics Interview Guide 45

243. What is the truth table for the NOR operation with four
variables?
Answer: The truth table for the NOR operation with four variables is as follows:

A B C D A NOR B NOR C NOR D

0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
—

244. What is the Boolean simplification of A · B + A · C?

Answer: This expression cannot be simplified further as it is already in its simplest
form.
—

245. What is the Boolean expression for the XOR operation with
three variables A, B, and C?
Answer: The Boolean expression for the XOR operation with three variables is:

A ⊕ B ⊕ C = (A ⊕ B) ⊕ C

—
Digital Electronics Interview Guide 46

246. What is the truth table for the XNOR operation with three
variables?
Answer: The truth table for the XNOR operation with three variables is as follows:

A B C A⊙B⊙C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 1 1
1 1 0 0
—

247. What is the simplification of A · A + B?

Answer: Using the complement law:

A·A+B =0+B =B

—
’s a concise and polished continuation of your documentation in LaTeX format:
“‘latex

247. What is the simplification of A · A + B?

Answer: Using the complement law:

A·A+B =0+B =B

248. What is the simplification of A + A · B?

Answer: Using the absorption law:

A+A·B =A

249. What is the simplification of A · A + B?

Answer: Applying De Morgan’s law:

A · A + B = A · (A · B) = 0 · B = 0

—
Digital Electronics Interview Guide 47

250. How would you simplify A · B + A · B?

Answer: By factoring out A, we get:

A · B + A · B = A · (B + B) = A · 1 = A

251. What is the simplification of A · B + A · B?

Answer: This expression is the XOR operation:

A·B+A·B =A⊕B

252. What is the simplification of (A + B) · (A + C)?

Answer: Using the distributive property:

(A + B) · (A + C) = A · A + A · C + B · A + B · C

Since A · A = A and A · B = B · A, the simplification is:

A+A·C +B·C

253. What is the simplification of A + A · (B + C)?

Answer: Using the absorption law:

A + A · (B + C) = A

254. How can we simplify the expression A + B · A + C?

Answer: Using De Morgan’s law:

A+B·A+C =A·B·A·C =A·B·C

255. What is the simplification of A · B + A · C + B · C?

Answer: The expression simplifies as:

A · B + A · C + B · C = (A + B) · (A + C) (using the distributive law)

—
Digital Electronics Interview Guide 48

256. What is the simplification of A + A · B?

Answer: Using the absorption law:
A+A·B =A+B
—

257. What is the simplification of A + A · B?

Answer: Using the absorption law:
A+A·B =A+B
—

258. What is the simplification of A + A · B?

Answer: By the absorption law:
A+A·B =A+B
—

259. How would you simplify the expression A · B + A · B?

Answer: By factoring out A, we get:
A · B + A · B = A · (B + B) = A · 1 = A
—

260. What is the simplification of A + A · B?

Answer: Using the absorption law:
A+A·B =A
—

261. What is the simplification of A · A + B?

Answer: Using De Morgan’s law:
A · A + B = A · (A · B) = 0
—

262. What is the simplification of A + B · A + C?

Answer: Using De Morgan’s law:
A+B·A+C =A·B·A·C =A·B·C
—
Digital Electronics Interview Guide 49

263. What is the simplification of A + A · B?

Answer: Using the absorption law:
A+A·B =A
—

264. What is the simplification of A · B + A · C + B · C?

Answer: Using the distributive property:
A · B + A · C + B · C = (A + B) · (A + C)

265. What is the Hamming code for the word 1101?

Answer: Hamming code is used for error detection and correction. To generate the
Hamming code, we follow these steps: 1. First, determine the number of parity bits
required using the formula:
2r ≥ m + r + 1
Where r is the number of parity bits and m is the number of data bits. In this case, for
the 4 data bits (1101), we need 3 parity bits. 2. The data is arranged as:
P1 P2 D1 P3 D2 D3 D4
Where P1 , P2 , P3 are the parity bits, and D1 , D2 , D3 , D4 are the data bits.
3. Now, we calculate the parity bits:
P1 = D1 ⊕ D2 ⊕ D4 = 1 ⊕ 1 ⊕ 1 = 1
P2 = D1 ⊕ D3 ⊕ D4 = 1 ⊕ 1 ⊕ 1 = 1
P3 = D2 ⊕ D3 ⊕ D4 = 1 ⊕ 1 ⊕ 1 = 1
Thus, the Hamming code for 1101 is 1111011.
—

266. How do you convert the decimal number 42 to binary?

Answer: To convert 42 into binary, divide the number by 2, keeping track of the re-
mainders:
42 ÷ 2 = 21 remainder = 0
21 ÷ 2 = 10 remainder = 1
10 ÷ 2 = 5 remainder = 0
5 ÷ 2 = 2 remainder = 1
2 ÷ 2 = 1 remainder = 0
1 ÷ 2 = 0 remainder = 1
Reading the remainders from bottom to top gives the binary equivalent:
4210 = 1010102
—
Digital Electronics Interview Guide 50

267. How do you convert a binary number 101101 to decimal?

Answer: To convert a binary number to decimal, multiply each bit by 2 raised to the
power of its position and sum the results:
1011012 = 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20
= 32 + 0 + 8 + 4 + 0 + 1 = 4510
—

268. How is the 1’s complement of a number obtained?

Answer: To obtain the 1’s complement of a binary number, flip each bit. For example:
1’s complement of 10101 = 01010
—

269. How is the 2’s complement of a number obtained?

Answer: To obtain the 2’s complement of a binary number, first find the 1’s complement
and then add 1 to the result:
1’s complement of 10101 = 01010
Now add 1:
01010 + 1 = 01011
Thus, the 2’s complement of 10101 is 01011.
—

270. How do you convert the hexadecimal number 3F to binary?

Answer: Each hexadecimal digit is equivalent to a 4-bit binary number. The hexadeci-
mal number 3F is converted to binary as follows:
3 = 0011, F = 1111
Thus, 3F16 = 001111112 .
—

271. How do you convert the binary number 1011 to hexadeci-

mal?
Answer: Group the binary number into 4-bit sections from right to left:
1011 (add leading 0s to make 4 bits) 1011 → 1011
Then, convert each group to hexadecimal:
10112 = B16
Thus, 10112 = B16 .
—
Digital Electronics Interview Guide 51

272. What is the Gray code equivalent of the binary number

1101?
Answer: To convert binary to Gray code, follow these steps: 1. The most significant bit
(MSB) of the Gray code is the same as the MSB of the binary number. 2. To find the
next Gray code bits, XOR each consecutive pair of bits from the binary number.
For binary 1101:
MSB of Gray code = 1
1⊕1=0
1⊕0=1
0⊕1=1
Thus, the Gray code of 11012 is 10112 .
—

273. What is the purpose of Gray code?

Answer: Gray code is a binary numeral system where two successive values differ in only
one bit. It is used in various applications such as: - Rotary encoders - Error correction -
Analog to digital conversion (ADC) - Digital communication
—

274. What is the Hamming distance between the binary numbers

1101 and 1001?
Answer: Hamming distance is the number of positions at which two strings of equal
length are different. For 1101 and 1001:

1101

1001
The Hamming distance is 1, as only the second bit differs.
—

275. How do you convert the octal number 37 to decimal?

Answer: To convert an octal number to decimal, multiply each digit by 8 raised to the
power of its position, starting from 0:

378 = 3 × 81 + 7 × 80 = 24 + 7 = 3110

—
Digital Electronics Interview Guide 52

276. How do you convert the decimal number 75 to octal?

Answer: To convert decimal to octal, divide the number by 8 and record the remainders:

75 ÷ 8 = 9 remainder = 3

9 ÷ 8 = 1 remainder = 1
1 ÷ 8 = 0 remainder = 1
Reading the remainders from bottom to top, we get:

7510 = 1138

277. What is the Gray code equivalent of the decimal number

5?
Answer: First, convert the decimal number 5 to binary:

510 = 1012

Then, convert the binary number to Gray code:

MSB of Gray code = 1

1⊕0=1
0⊕1=1
Thus, the Gray code of 510 is 1112 .
—

278. What is the 1’s complement of the decimal number -5?

Answer: To find the 1’s complement of a negative number, first find the binary repre-
sentation of the positive number and then flip all the bits:

510 = 01012

1’s complement of 01012 is 10102 .

—

279. What is the 2’s complement of the decimal number -5?

Answer: To find the 2’s complement of a negative number, first find the 1’s complement
and then add 1:
510 = 01012
1’s complement of 01012 is 10102 . Adding 1:

10102 + 1 = 10112

Thus, the 2’s complement of −5 is 10112 .

—
Digital Electronics Interview Guide 53

280. How do you convert the binary number 101011 to octal?

Answer: To convert binary to octal, group the binary number into groups of 3 bits from
right to left:
101011 (grouped as) 101 011
Now, convert each group to octal:

1012 = 58 , 0112 = 38

Thus, 1010112 = 538 .

—

281. How do you convert the binary number 101010 to hexadec-

imal?
Answer: To convert binary to hexadecimal, group the binary number into 4-bit sections
from right to left:
101010 (grouped as) 1010 1010
Now, convert each group to hexadecimal:

10102 = A16 , 10102 = A16

Thus, 1010102 = AA16 .

—

282. What is the Hamming code for the word 101?

Answer: The Hamming code for the word 101 requires 3 parity bits. The steps to
calculate the Hamming code are as follows: 1. Place the data bits in the positions of the
Hamming code:
P1 P2 D1 P3 D2 D3
Where P1 , P2 , P3 are the parity bits, and D1 , D2 , D3 are the data bits. 2. Calculate the
parity bits:
P1 = D1 ⊕ D2 = 1 ⊕ 0 = 1
P2 = D1 ⊕ D3 = 1 ⊕ 1 = 0
P3 = D2 ⊕ D3 = 0 ⊕ 1 = 1
Thus, the Hamming code for 101 is 101101.
—

283. How do you convert the hexadecimal number 9F to binary?

Answer: Each hexadecimal digit corresponds to a 4-bit binary number:

9 = 1001, F = 1111

Thus, 9F16 = 100111112 .

—
Digital Electronics Interview Guide 54

284. What is the base-10 equivalent of the binary number 1101?

Answer: To convert the binary number to decimal, calculate the sum of each bit multi-
plied by 2n , where n is the bit position:
11012 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20
= 8 + 4 + 0 + 1 = 1310
—

285. How do you convert a number from base-10 to any other

base?
Answer: To convert a number from base-10 to any other base, repeatedly divide the
number by the new base, keeping track of the remainders. The remainders, read from
bottom to top, form the number in the new base.

286. What is the conversion process for a binary number to

octal?
Answer: To convert a binary number to octal, group the binary digits into groups of
three (starting from the right). If necessary, add leading zeros to complete the groups.
Then, replace each group with the corresponding octal digit.
Example: Convert 110101 2 110101 2 to octal. Group the binary number in groups
of 3: 110101 2 110101 2 → 110 101 110101 Now, convert each group:
110 2 = 6 8 , 101 2 = 5 8 110 2 =6 8 ,101 2 =5 8
Thus, 110101 2 = 65 8 110101 2 =65 8 .

287. What is the significance of the carry-out in binary addition?

Answer: In binary addition, the carry-out represents a value that exceeds the range of
the current bit. It is propagated to the next higher bit. For example, when adding 1 + 1
= 10 2 1+1=10 2 , the sum is 0 0 with a carry-out of 1 1 that will be added to the next
column.

288. How do you perform binary subtraction using the two’s

complement method?
Answer: To perform binary subtraction using the two’s complement method, follow
these steps:
Convert the number to be subtracted into its two’s complement form (invert the bits
and add 1).
Add the two’s complement of the subtracted number to the original number.
If there is a carry-out, discard it; the result will be the binary difference.
Example: Subtract 101 2 101 2 from 1100 2 1100 2 :
The two’s complement of 101 2 101 2 is 0101 2 0101 2 .
Add 1100 2 1100 2 and 0101 2 0101 2 :
1100 2 + 0101 2 = 10001 2 1100 2 +0101 2 =10001 2
Discard the carry-out: 0001 2 0001 2 (which is 1 in decimal).
Digital Electronics Interview Guide 55

289. How do you multiply two binary numbers?

Answer: Binary multiplication is similar to decimal multiplication. The multiplication
of binary digits follows these steps:
Multiply each bit of the first number by each bit of the second number.
Add the partial products.
If there is a carry-over, add it to the next column.
Example: Multiply 101 2 101 2 by 11 2 11 2 :
101 × 11 101 ( Partial product for 1st bit ) + 1010 ( Partial product for 2nd bit )
1111 ( Final result ) +101 ×+11 101(Partial product for 1st bit) +1010(Partial prod-
uct for 2nd bit) 1111(Final result)
Thus, 101 2 × 11 2 = 1111 2 101 2 ×11 2 =1111 2 .

290. How do you divide two binary numbers?

Answer: Binary division follows the same basic principles as decimal division, but it
uses binary numbers.
Divide the dividend by the divisor.
Subtract the result from the dividend and bring down the next bit.
Repeat the process for each bit of the dividend.
Example: Divide 1101 2 1101 2 by 10 2 10 2 :
Divide the first part of 1101 2 1101 2 (i.e., 11 2 11 2 ) by 10 2 10 2 :
11 2 ÷ 10 2 = 1 2 (quotient) remainder = 1 2 11 2 ÷10 2 =1 2 (quotient)remainder=1
2
Bring down the next bit (1), and divide the remainder by 10 2 10 2 :
11 2 ÷ 10 2 = 1 2 (quotient) remainder = 1 2 11 2 ÷10 2 =1 2 (quotient)remainder=1
2
Thus, the result is 11 2 11 2 with a remainder of 1 2 1 2 .

291. What is the difference between a full adder and a half

adder?
Answer: A half adder is a simple circuit that adds two single-bit numbers. It has two
inputs (A and B) and two outputs (sum and carry). The sum is calculated as AB and
the carry is AB.
A full adder, on the other hand, adds three bits: two inputs (A and B) and a carry-in
from a previous addition. It has three inputs (A, B, and carry-in) and two outputs (sum
and carry-out). The sum is Carry-in ABCarry-in, and the carry-out is ( ) + (
Carry-in ) + ( Carry-in ) (AB)+(BCarry-in)+(ACarry-in).

292. What is a multiplexer (MUX), and how does it work?

Answer: A multiplexer (MUX) is a combinational circuit that selects one of many
inputs and forwards the selected input to a single output line. It works by using selec-
tion lines that determine which input to pass through. The number of selection lines
determines how many inputs the MUX can handle.
For example, a 4-to-1 MUX has 4 input lines, 2 selection lines (since 2 2 = 4 2 2 =4),
and 1 output line.
Digital Electronics Interview Guide 56

293. What is a demultiplexer (DEMUX), and how does it work?

Answer: A demultiplexer (DEMUX) is the reverse of a multiplexer. It takes a single
input and channels it to one of many outputs based on selection lines. The number of
selection lines determines how many outputs the DEMUX can direct the input to.
For example, a 1-to-4 DEMUX takes a single input and can route it to one of four
outputs based on the selection lines.

294. What is a shift register, and what are its types?

Answer: A shift register is a type of sequential logic circuit used for storing and
shifting data. It consists of flip-flops, and data can be shifted in or out in a serial or
parallel manner.
There are several types of shift registers:
Serial-in, Serial-out (SISO): Data is shifted in and out one bit at a time.
Serial-in, Parallel-out (SIPO): Data is shifted in serially, but output is taken in par-
allel.
Parallel-in, Serial-out (PISO): Data is entered in parallel, but shifted out serially.
Parallel-in, Parallel-out (PIPO): Data is entered and output in parallel.

295. What is a flip-flop, and how does it work?

Answer: A flip-flop is a basic digital memory circuit that stores one bit of information.
It has two stable states and can be used to store binary data. Flip-flops are edge-triggered
devices, meaning they change their state based on a clock signal.
There are various types of flip-flops:
SR Flip-Flop: Uses Set and Reset inputs.
D Flip-Flop: Uses Data and Clock inputs.
JK Flip-Flop: A more versatile flip-flop with J and K inputs.
T Flip-Flop: Toggles its output on each clock pulse.

1’s and 2’s Complement Problems and Solutions

296. What is the 1’s complement of the binary number 1101012 ?
Answer: To calculate the 1’s complement, invert each bit of the number.
Given number: 1101012
1’s complement: 0010102
—

297. What is the 2’s complement of the binary number 1101012 ?

Answer: To calculate the 2’s complement: 1. Find the 1’s complement (invert each bit).
2. Add 1 to the result.
Given number: 1101012
1’s complement: 0010102
Add 1:
0010102 + 1 = 0010112
Digital Electronics Interview Guide 57

Thus, the 2’s complement is 0010112 .

—

298. Find the 1’s complement of 1011102 .

Answer: To find the 1’s complement, simply invert the bits:
Given number: 1011102
1’s complement: 0100012
—

299. Find the 2’s complement of 1011102 .

Answer: To calculate the 2’s complement: 1. Find the 1’s complement. 2. Add 1 to the
result.
Given number: 1011102
1’s complement: 0100012
Add 1:
0100012 + 1 = 0100102
Thus, the 2’s complement is 0100102 .
—

300. Convert 1101012 to its 2’s complement and add it to 1011012 .

Answer: To add two numbers using 2’s complement: 1. First, find the 2’s complement
of 1101012 .
Given number: 1101012
1’s complement: 0010102
Add 1:
0010102 + 1 = 0010112
Thus, the 2’s complement of 1101012 is 0010112 .
2. Now, add 1011012 and 0010112 .

1011012
+0010112
10000002
The sum is 10000002 , which is a 7-bit result with the leftmost 1 being the carry-out.
—

301. Find the 1’s complement of 111100002 .

Answer: To find the 1’s complement, invert each bit:
Given number: 111100002
1’s complement: 000011112
—
Digital Electronics Interview Guide 58

302. Find the 2’s complement of 111100002 .

Answer: To calculate the 2’s complement: 1. Find the 1’s complement. 2. Add 1 to the
result.
Given number: 111100002
1’s complement: 000011112
Add 1:
000011112 + 1 = 000100002
Thus, the 2’s complement is 000100002 .
—

303. Subtract 101012 from 110112 using 1’s and 2’s complement.
Answer: To subtract 101012 from 110112 using 2’s complement: 1. Find the 2’s com-
plement of 101012 .
Given number: 101012
1’s complement: 010102
Add 1:
010102 + 1 = 010112
Thus, the 2’s complement of 101012 is 010112 .
2. Now, add this to 110112 .
Thus, the result is 1011102 , which is 46 in decimal.
—

304. What is the 1’s complement of 10010012 ?

Answer: To find the 1’s complement, simply invert each bit:
Given number: 10010012
1’s complement: 01101102
—

305. What is the 2’s complement of 10010012 ?

Answer: To calculate the 2’s complement: 1. Find the 1’s complement. 2. Add 1 to the
result.
Given number: 10010012
1’s complement: 01101102
Add 1:
01101102 + 1 = 01101112
Thus, the 2’s complement is 01101112 .
—

306. Convert the decimal number −38 to its binary form using
2’s complement.
Answer: To convert a negative decimal number to binary using 2’s complement: 1.
Convert the positive value to binary. 2. Find the 1’s complement. 3. Add 1.
Digital Electronics Interview Guide 59

1. 3810 = 1001102 2. 1’s complement: 0110012 3. Add 1:

0110012 + 1 = 0110102

Thus, the 2’s complement of −38 is 1101102 (for an 8-bit representation).

—

307. What is the 1’s complement of 01010102 ?

Answer: To find the 1’s complement, invert each bit:
Given number: 01010102
1’s complement: 10101012
—

308. What is the 2’s complement of 01010102 ?

Answer: To calculate the 2’s complement: 1. Find the 1’s complement. 2. Add 1 to the
result.
Given number: 01010102
1’s complement: 10101012
Add 1:
10101012 + 1 = 10101102
Thus, the 2’s complement is 10101102 .
—

309. Find the 1’s complement of the binary number 1110002 .

Answer: To find the 1’s complement, invert each bit:
Given number: 1110002
1’s complement: 0001112
—

310. Find the 2’s complement of the binary number 1110002 .

Answer: To calculate the 2’s complement: 1. Find the 1’s complement. 2. Add 1 to the
result.
Given number: 1110002
1’s complement: 0001112
Add 1:
0001112 + 1 = 0010002
Thus, the 2’s complement is 0010002 .
—
Digital Electronics Interview Guide 60

311. How do you represent the number −37 in 8-bit 2’s comple-
ment?
Answer: To represent −37 in 8-bit 2’s complement: 1. Convert the positive value 3710
to binary:
3710 = 001001012
2. Find the 1’s complement:
110110102
3. Add 1:
110110102 + 1 = 110110112
Thus, −37 in 8-bit 2’s complement is 110110112 .
—

312. Convert the decimal number −19 to binary using 2’s com-
plement.
Answer: To convert −19 to binary using 2’s complement: 1. Convert the positive value
1910 to binary:
1910 = 100112
2. Find the 1’s complement:
011002
3. Add 1:
011002 + 1 = 011012
Thus, −19 in 2’s complement is 111011012 (for 8-bit representation).
—

Combinational Circuit Problems and Solutions

321. Design a 4-input AND gate using only 2-input AND gates.
Answer: To design a 4-input AND gate using only 2-input AND gates, we need to chain
multiple 2-input AND gates. 1. First, take the inputs A, B, C, and D. 2. Combine A
and B through a 2-input AND gate to form AB. 3. Combine C and D through another
2-input AND gate to form CD. 4. Finally, combine AB and CD through another 2-input
AND gate to produce the output.
The schematic is as follows:

Output = (A · B) · (C · D)
—
Digital Electronics Interview Guide 61

322. Design a 4-input OR gate using only 2-input OR gates.

Answer: To design a 4-input OR gate using only 2-input OR gates: 1. Combine A and
B using a 2-input OR gate to form A + B. 2. Combine C and D using another 2-input
OR gate to form C + D. 3. Finally, combine A + B and C + D using another 2-input
OR gate to get the output.
The schematic is as follows:

Output = (A + B) + (C + D)
—

323. Design a full adder circuit using NAND gates only.

Answer: A full adder adds two bits, A and B, along with a carry input Cin , and produces
a sum and carry output.
1. The Sum output (S) of a full adder can be expressed as:

S = A ⊕ B ⊕ Cin

This can be implemented using XOR gates, which can be realized using NAND gates.
2. The Carry output (Cout ) can be expressed as:

Cout = (A · B) + (Cin · (A ⊕ B))

This can also be realized using NAND gates.

—

324. Simplify the Boolean expression A + AB + A′ B.

Answer: The given Boolean expression is A + AB + A′ B.
1. Apply the Distributive Law:

A + AB + A′ B = A(1 + B) + A′ B

2. Since 1 + B = 1, we have:
A + A′ B
3. The simplified Boolean expression is:

A + A′ B

325. Design a half adder using NAND gates only.

Answer: A half adder adds two bits, A and B, and produces a sum S and carry output
C.
1. The Sum output can be expressed as:

S =A⊕B
Digital Electronics Interview Guide 62

This XOR operation can be implemented using NAND gates.

2. The Carry output can be expressed as:

C =A·B

This AND operation can be implemented using a NAND gate.

—

326. Realize a 3-input AND gate using only NOR gates.

Answer: To realize a 3-input AND gate using NOR gates: 1. First, combine A and B
using a NOR gate to form A ↓ B. 2. Then, combine the result from step 1 with C using
another NOR gate. 3. Finally, invert the output to get the AND result.
The schematic is as follows:

Output = (A ↓ B) ↓ C
—

327. Design a 2-input NAND gate using NOR gates only.

Answer: To design a 2-input NAND gate using NOR gates: 1. First, combine A and B
using a NOR gate. 2. Then, invert the output of the NOR gate using another NOR gate.
The schematic is as follows:

Output = (A ↓ B) ↓ (A ↓ B)
—

328. Convert the Boolean expression (A+B)(C +D) into a NAND

gate implementation.
Answer: To convert the Boolean expression (A + B)(C + D) into a NAND gate imple-
mentation: 1. First, implement the OR gates for A + B and C + D using NAND gates.
2. Then, implement the AND gate using a NAND gate for (A + B)(C + D).
The schematic is as follows: 1. A + B = (A ↓ A) ↓ (B ↓ B) 2. C + D = (C ↓ C) ↓
(D ↓ D) 3. (A + B)(C + D) = [(A ↓ A) ↓ (B ↓ B)] ↓ [(C ↓ C) ↓ (D ↓ D)]
—

329. Implement a 3-input XOR gate using NAND gates only.

Answer: To implement a 3-input XOR gate using NAND gates: 1. First, implement
two 2-input XOR gates using NAND gates. 2. Then, combine the results of the two XOR
gates to create the final 3-input XOR.
The Boolean expression for a 3-input XOR gate is:

X =A⊕B⊕C

This can be implemented using NAND gates, following the steps for the 2-input XOR
gate.
—
Digital Electronics Interview Guide 63

330. Simplify the Boolean expression A · (B + C) · D.

Answer: The given Boolean expression is A · (B + C) · D.
1. Apply the Distributive Law:
A · (B + C) · D = (A · B · D) + (A · C · D)
Thus, the simplified Boolean expression is:
A·B·D+A·C ·D
—

331. Realize a 2-input OR gate using NOR gates only.

Answer: To realize a 2-input OR gate using NOR gates: 1. First, implement the NOR
operation on A and B, which will give A ↓ B. 2. Then, invert the output using another
NOR gate.
The schematic is as follows:

Output = (A ↓ B) ↓ (A ↓ B)
—

332. Design a 2-input NAND gate using only AND gates.

Answer: To design a 2-input NAND gate using only AND gates: 1. First, implement
the AND gate for A · B. 2. Then, invert the output using a NOT gate.
The schematic is as follows:
Output = ¬(A · B)
—

333. Design a 4-bit binary adder using basic gates.

Answer: A 4-bit binary adder can be designed by cascading 1-bit full adders. Each full
adder will take two bits and a carry input, and produce a sum and carry output.
The Boolean expressions for the full adder are: - Sum: S = A ⊕ B ⊕ Cin - Carry:
Cout = (A · B) + (Cin · (A ⊕ B))
By cascading four 1-bit full adders, we can create a 4-bit binary adder.
—

334. Implement a 2-input XNOR gate using only NAND gates.

Answer: To implement a 2-input XNOR gate using NAND gates: 1. Use the formula
for XNOR:
X = ¬(A ⊕ B)
2. First, implement an XOR gate using NAND gates. 3. Then, invert the output of the
XOR gate using another NAND gate.
The schematic is as follows:
X = (A · B) ↓ (A ↓ B)
—
Digital Electronics Interview Guide 64

335. Design a half subtractor using logic gates.

Answer: A half subtractor subtracts two bits, A and B, and produces a difference D
and borrow Bout .
1. The Difference output is:
D =A⊕B
2. The Borrow output is:
Bout = ¬A · B
Thus, a half subtractor can be implemented using XOR and AND gates.
—

336. Implement a 4-bit binary subtractor using basic gates.

Answer: A 4-bit binary subtractor can be designed by cascading 1-bit half subtractors
and a borrow-in input.
Each half subtractor takes two bits A and B and produces a difference and a borrow
output.
The Boolean expressions for the half subtractor are: - Difference: D = A ⊕ B -
Borrow: Bout = ¬A · B
By cascading four 1-bit half subtractors, we can create a 4-bit binary subtractor.