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Lab1 Digital ModelAnswer

The document outlines a course on Digital Circuits (CMPS244) for Spring 2024-2025 at Beirut Arab University, detailing various problems related to number system conversions and Verilog programming. It includes exercises for converting binary, octal, decimal, and hexadecimal numbers, as well as instructions for creating and simulating a Verilog design for basic logic gates. The document emphasizes the importance of showing all calculation steps and provides a structured approach to learning Verilog syntax and circuit simulation.

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3 views4 pages

Lab1 Digital ModelAnswer

The document outlines a course on Digital Circuits (CMPS244) for Spring 2024-2025 at Beirut Arab University, detailing various problems related to number system conversions and Verilog programming. It includes exercises for converting binary, octal, decimal, and hexadecimal numbers, as well as instructions for creating and simulating a Verilog design for basic logic gates. The document emphasizes the importance of showing all calculation steps and provides a structured approach to learning Verilog syntax and circuit simulation.

Uploaded by

mehrezhiba80
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Course: CMPS244 – Digital Circuits Semester: Spring 2024 - 2025

Mathematics and Computer Science Department Time: 11:00 A.M–02:00 P.M


Faculty of Science Date: Monday, 27- 01- 2025
Beirut Arab University

Part One
Note: Show all steps in your calculations (i.e., final answers alone are not acceptable).

Problem 1: Convert the following numbers to decimal:


1 (100110110)2
.
2 (1001100.0101)
. 2
3 (BF2.D)16
.
4. (571.75)8

1. (1*2^8) + (0*2^7) + (0*2^6) + (1*2^5) + (1*2^4) + (0*2^3) + (1*2^2) +


(1*2^1) + (0*2^0) = (310)10
2. (76.3125)10
3. (11*16^2) + (15*16^1) + (2*16^0) + (13*16^-1) = (3058.8125)10
4. (377.953125)10

Problem 2: Convert (37)10 and (59)10 to binary, octal, and hexadecimal.

 (37)10=(100101)2
(37)10=(45)8
(37)10 =(25)16
 (59)10 =(111011)2
(59)10 =(73)8
(59)10 =(3B)16

Problem 3: Convert the following decimal numbers to the stated number system:

1. (1983.925)10=(?)8
2. (571.825)10=(?)16
3. (605.203)10=(?)2

1. 3677.731
2. 23B.D3
3. 1001011101.001

Problem 4: Convert the following numbers to the stated number system:


1. (BF2.D)16 = (?)8

2. (571.75)8=(?)16

1. 5762.64

2. 179.F4
Part Two -Learn Verilog

Purpose:

⮚ Learn the basics of structural Verilog Syntax.

⮚ Learn to create a new project using Verilog.

⮚ Learn to simulate the behavior of the basic gates using DigitalJS Online tool.

Procedure:

A. Design:
a) Create a new Verilog HDL design file and Save it.
b) Create a module having the same name as the project name (Top-level
Design Entity)
c) The module has two 1-bit inputs a and b.
d) The module has three 1-bit outputs: outAND, outOR, outNOTA where:
i. outAND is the result of the logical AND of the inputs: a & b
ii. outOR is the result of the logical OR of the inputs: a | b
iii. outNOTA is the result of the logical NOT of the input a.
e) Write your code using structural Verilog.
f) Check the code for syntax errors using the Analyze tool.

module circuit (a, b, outAnd, outOr, outNotA);

input a, b;

output outAnd, outOr, outNotA;

and (outAnd,a,b);

or (outOr,a,b);
not (outNotA,a);

endmodule

B. Simulation:
a) Open the https://digitaljs.tilk.eu/ website.
b) Load the Verilog file previously created by selecting “Load from File” tab
and select the “*.v” file.
c) Press the “Synthesize and simulate” button, a diagram of the circuit will be
shown on the left panel.
d) Check the wave alternations for all the possible combinations of inputs, and
their output.
e) sketch the wave form with the different input combinations and output
result, then draw the truth table of each gate.

a b outAnd outOr outNotA


0 0 0 0 1
0 1 0 1 1
1 0 0 1 0
1 1 1 1 0

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