EXPERIMENT NO: 6 PULSE AMPLITUDE MODULATION (PAM) & DEMODULATION To study Pulse Amplitude modulation and demodulation process with Relevant waveforms. APPARATUS. 1, Pulse amplitude modulation & demodulation Trainer Kit. 2, Dual trace CRO. 3. Patch chords. 4, PC with windows(95/98/XP/NT/2000) 5. MATLAB Software with communication toolbox BLO DIAGRA! PULSE AMPLITUDE MODULATION AND DEMODULATION ee THEORY: Pulse modulation is used to transmit analog information. In this system continuous wave forms are sampled at regular intervals. Information regarding the signal is transmitted only at the sampling times together with syncing signals. At the receiving end, the original waveforms may be reconstituted from the information regarding the samples.The pulse amplitude modulation is the simplest form of the pulse modulation. PAM is a pulse modulation system is which the signal is sampled at regular intervals, and each sample is made proportional to the amplitude of the signal at the instant of sampling. The pulses are then sent by either wire or cables are used to modulated carrier. The two types of PAM are i) Double polarity PAM, and ii) the single polarity PAM, in which a fixed de level is added to the signal to ensure that the pulses are always positive. Instantaneous PAM sampling occurs if the pulses used in the modulator are infinitely short, ‘Natural PAM sampling occurs when finite-width pulses are used in the modulator, but the tops of the pulses are forced to follow the modulating waveform. Flat-topped sampling is a system quite often used because of the ease of generating the modulated wave. PAM signals are very rarely used for transmission purposes directly. The reason for this lies in the fact that the modulating information is contained in the amplitude factor of the pulses, which can be easily distorted during transmission by noise, crosstalk, other forms of distortion. They are used frequently as an intermediate step in other pulsemodulating methods, especially where time- division multiplexing is used. PROCEDURE: 1, The 4016 integrated circuit is a CMOS bilateral switch which is used as a sampling switch. A positive voltage on pin 13 closes the CMOS transistor switch between pins 182. When pin13 is as zero volts, the switch is open. 2, Switch ON the trainer kit Connect a 10 KHz sine wave of SV p-p from an audio generator at the point marked AF i/p. 4. Connect the oscilloscope to pin 2 of 4016 IC, adjust the 1K potentiometer (Ri) to vary the amplitude of the modulating signal. Also adjust the frequency of the modulating signal to obtain stable display on the oscilloscope, The waveform obtained is a dual polarity PAM. 5. Vary the amplitude and frequency of the sine wave signal and observe the change in the output waveform, 6. Connect the modulated output to the input of the demodulator 7. Connect channel | of the dual trace oscilloscope to the demodulator output and channel 2 to the input sine wave. Compare the two waveforms you will find that they are 180 out of phase.EXPECTED WAVE FORMS: (© MODULATING SIGNAL t TIMEMT) = , ; ! Mn innar t ps YL ees SNL RESULT: Pulse amplitude modulation and demodulation is observed and their respective wave forms are plotted. CONCLUSION: Tn Pulse Amplitude Modulation we observed that the characteristic parameter (amplitude) of carrier is varied according to the amplitude of the message signal, the samples are taken at regular intervals of time, Each sample is a pulse whose amplitude is determined by the amplitude of the variable at the instant of time at which the samples are taken, a reasonable approximatingof the signal being sampled can be constructed at the receiving end VIVA Q 1 DM is possible for sampled signals. What kind of multiplexing can be used in continuous modulation systems? 2. What is the minimum rate at which a speech signal can be sampled for the purpose of PAM? 3. What is cross talk in the context of time division multiplexing? 4, Which is better, natural sampling or flat topped sampling and why? 5. Why a de offset has been added to the modulating signal in this board? Was it essential for the working of the modulator? Explain. 7. Study about the frequency spectrum of PAM signal and derive mathematical expression for it? 8. Explain the modulation circuit operation? 9. Explain the demodulation circuit operation? MATLAB COD! PROGRAM: cle; close all; clear all; t=0:1/6000:((10/1000)-(1/6000)); xa=sin(2*pi* 100*abs(t)); Ts=32; x=sin(2*pi*600*(Ts*t)); X=fft(xa,abs(x)); subplot(3,1,1); plot(x,a); atid subplot(3,1,2); stem(X); atid Y-ifh(xa,X); subplot(3,1,3); plot(Y); gridModulating Signal Modulated SignalEXPERIMENT NO: 9 PULSE WIDTH MODULATION AND DEMODULATION AIM: To generate the pulse width modulated and demodulated waves. APPARATUS: 1, PWM trainer kit 2. CR.OG0MHz) 3. Patch Chords 4, PC with windows(95/98/XP/NT/2000) 5. MATLAB Software with communication toolbox BLOCK DIAGRAM: PWM MODULATOR & DEMODULATOR AF GENERATOR PWM OUTPUT pw [—> RF GENERATOR DEMODULATOR vooman gq frowrassmmnm |) sum |__a_openarepovnrer PROCEDURE: 1, Switch “ON” the experimental kit, 2. Observe the clock generator output & modulation signal outputs. 3. Connect clock generator output to the clock input point of PWM modulator And observe the same clock on channel of a dual trace CRO. 4, Trigger the CRO with respect to CH 15. Apply a variable DC voltage of 8 to 12 volts from any external regulated Power supply. 6. Observe the PWM output on CH 2. 7. If we observe the PWM output, it’s width varies according to the Modulating voltage. 8. A variable amplitude modulating signal is given to observe how the PWM. are varying for AC modulating voltages. 9. In this case we have to trigger the CRO with respect to modulating voltage. EXPECTED WAVE FORMS: "4 i 7 ap nt vl I I i I 4 7 bet kL oy Tine th Fig(2) PULSE WIDTH MODULATION (a) Signal (8) iota pses (Ce) PWM RESULT: Pulse width modulation and demodulation is observed and their respective wave forms are plotted. CONCLUSTO! In Pulse Width Modulation we observed that carrier signal width is varied according to the amplitude of the message signal, amplitude of the carrier signal is fixed vr UA! 1 S: 1. An audio signal consists of frequencies in the range of 100Hz to 5.5KHz.What is the minimum frequency at which it should be sampled in order to transmit it through pulse modulation? 2. Draw )M signal which is handling three different signals using PWM?3. What do you infer from the frequency spectrum of a PWM signal? 4, Clock frequency in a PWM system is 2.5 kHz and modulating signal frequency is S00Hzhowmany pulses per cycle of signal occur in PWM output? Draw the PWM signal? Why should the curve for pulse width Vs modulating voltage be linear? What is the other name for PWM? What is the disadvantage of PWM? Will PWM work if the synchronization between Tx and Rx fails? 9. Why integrator is required in demodulation of PWM? 10. What kind of conversion is done in PWM generation? MATLAB CODE: Cle; Clear all; fe=1000; fs=1000 1=200; t=0:1/f8:((2/f1)(1/f5)); x1=0.4*cos(2*pi*fl *)+0.5; %modulation yl=modulate(x,fe,fs,'pwm'); subplot(421); plot(x1); title(original signal tokne mesage,f1=500,fs=10000') ; subplot(422); plot(y1); axis({0 500-0.2 1.2); title(PWM)) demodulation x1_recov-demod(y1,fe,6,'pwm’); subplot(423); plot(x1_recov); title(time domain reoverd recoverd,sigle tone,f1=200');vigil signal tone mesage I= DLA ooo oD oO 0 0 0 10 05 a ee ee ee) time domain oer covet sil tone f1-200 os +o oD ooo mo 0EXPERIMENT NO: 8 PULSE POSITION MODULATION AND DEMODULATION AIM: To study the generation Pulse Position Modulation (PPM) and Demodulation. APPARATUS: 1. Pulse Position Modulation (PPM) and demodulation Trainer Ki 2. C.R.O(30MHz) 3. Patch chords. 4, PC with windows(95/98/XP/NT/2000) 5. MATLAB Software with communication toolbox BLOCK DIAGRAM: PPM MODULATION AND DEMODULATION AF GENERATOR PPMOUTPUT pwm b>} pwe-ppm }—> RF GENERATOR PPMOUTPUT aroureut PPM-PWM DeMODULATOR: > THEORY: Pulse modulation is used to transmit analog information, such as continuous speech or data. The data is sent at sampling times, with synchronizing pulses. The pulse position modulation is an analog modulation method, where in we have fixed amplitude of each pulse, but the position of each pulse is made proportional to the amplitude of the modulating signal at that instantPPM is derived from the pulse width modulated signal. To demodulate the PPM signal, it is fed to an integrating RC circuit (LPF) to obtain the modulating signal. PROCEDURE: MODULATOR: 1 Switch On the experimental kit, 2. Observe the clock generator output and modulating signal outputs. 3. Connect the clock generator output to the clock input point of PPM modulator and ‘observe the same clock on CHI of dual trace CRO. 4, Trigger the CRO w.r:t CHI 5. Apply a variable D.C voltage of 8-12V from any external regulated power supply. 6. Observe the PPM output on CH2. 7. By varying the modulating voltage, PPM output changes position, but the width is ‘maintained constant. DEMODULATOR: 1, Apply PPM signal to the PPM demodulator and observe the output. 2. The output almost coincides with modulating signal, (a) SIGNAL (bh) CLOCK INPUT (ce) EWM OUTPUT Vee (a) TRIGGERS (0) FEM. | ourevr — CI Lo = i Coy [Ty C4 [TyUL’ Pulse position modulation and demodulation is observed and their respective wave forms are plotted, VIVA Q 1 1. Define and describe PPM? 2. Explain with waveforms how PPM is derived from PWM. 3. What is the fundamental difference between pulse modulation, on the one hand, and frequency and amplitude modulation on the other? MATLAB CODE: ALGORITHM ‘© Choose the sampling frequency f; and modulating frequency fi such that Nyquist criteria sfied. © Generate the message signal using fi and f& are sal ‘© Modulate the message signal using the carrier frequency. ‘+ FFT is applied to the modulated signal to get frequency spectrum. * Demodulate the modulated signal using the same carrier frequency. ‘* Plot the graphs for the original message signal, modulated, frequency spectrum and demodulated signal. PROGRAM, cle; clear all; close all; 0; £2 t=0:1/fs:((2/F1)-(1/fs)); x1=0.4%cos(2*pi*f1"t)+0.5; %x2=0.2*(cos(2*pi*f1*t)+cos(2*pi"f2*t)) +0.5 ; subplot(4,2,1); plot(x1); title(‘original msg signal’); yi=modulate(x1,fc,fs,'ppm');subplot(4,2,2); plot(y1) axis([0 50 -0.2 1.2]); title('ppm one of f1,fe=1000,f1=80 "); fat =abs(Fft(y1,1024)) ; fet=[fx1(512:1024) x1(1:513)]; f=[(511*f5/1024):(fs/1024):(512*fs/1024)]; subplot(4,2,3); plot(fx1); title('freq des ppm signal tone,fe= 1000"); x1_recov = demod(y1,fe,fs,'ppm'); subplot(4,2,4); plot(x1_recov); title(‘time domain recovered signal’); WAVE FORMS: = & 3s original msg signal pam one of f,-=1000 FBO 1 a5 oO oO 5 0 6 7 ri a n 2a mn 4 ao freq des ppm Signal tone £c=1000 time domamn covered samal q or . SS oO a 100 1500 %y 5 10 6 2 2AIM: To analyze a PCM system and interpret the modulated and demodulated waveforms for a sampling frequency of 4 KHz, APPARATUS 1. PCM modulator trainer 2. PCM Demodulator trainer 3. C.R.0(30MHz) 4, Patch chords. 5. PC with windows(95/98/XP/NT/2000) 6, MATLAB Software with communication toolbox INTRODUCTION In Pulse code modulation (PCM) only certain discrete values are allowed for the ‘modulating signals. The modulating signal is sampled, as in other forms of pulse modulation. But any sample falling within a specified range of values is assigned a discrete value. Each value is assigned a patter of pulses and the signal transmitted by means of this code. The electronic circuit that produces the coded pulse train, from the modulating waveform is termed a coder or encoder, A suitable decoder must be used at the receiver in order to extract the original information from the transmitted pulse train, This PCM system consists of PCM Modulator 1, Regulated power supply 2, Audio Frequeney signal generator 3. Sample & Hold circuit 4,8 Bit A/D Converter 5. 8 Bit Parallel-Serial Shift register 6. Clock generator/Timing circuit 7. DC source 2.3.2. PCM Demodulator 1, Regulated power supply 2. 8 Bit Serial-Parallel to shift register 3. 8 Bit D/A converter 4, Clock generator 5. Timing circuit 6. Passive low pass filter 7. Audio amplifiersBLOCK DIAGRAM: PCM MODULATOR & DEMODULATOR Ings AP + sample || av shit Generator Hold Convert Reiter rem oupe Sen « vote |] towpas le pa shit Amplifier Files Convete Register |, Regulated power supply (68M & 68D): This consists of a bridge rectifier followed by capacitor filters and three terminal regulators 7805 and 7905 to provide regulated DC voltages of +SV and +12V @ 300Ma each to the on board circuits. These supplies have been internally connected to the circuits, so no external connections are required for operation. Audio Frequency (AF) Signal generator (68M): Sine wave signal of 200Hz is generated to use as a modulating (message or information) signal to be transmitted. This is an Op-Amp based Wein bridge Oscillators using IC TLO84. IC TLO84 is @ FET input general purpose Operational Amplifier. Amplitude control is provided in the circuit to vary the output amplitude of AF signal Clock generator/Timing circuit (68M & 68D): A TTL compatible clock signal of 64 KHz and 4KHz frequency are provided on board to use as a clock to the various circuits in the system. This circuit is a astable multivibrator using 555 timer followed by a buffer and frequency dividers. DC source (68M): A 0 to +5V variable DC voltage is provided on board to use as a modulating signal instead of AF signal. This is useful to study step by operation of PCM modulation and demodulation. This is a simple circuit consisting of potentiometer and fixed power supply. Low pass filters (68D): This is a series of simple RC networks provided on board to smoothen the output of the D/A converter output (stair case signal). RC values are chosen such that the cutoff frequency would be at 200HzAmplifiers (68D): This is an Op-amp (IC TLO84) based non-inverting variable gain amplifiers provided on board to amplify the recovered message singles i.e. output of the Low pass filter to desired level. Amplitude control is provided in circuit to vary the gain of the amplifier between 0 and 3. AC/DC Switch facilitates to couple the input signal through capacitor or directly to the amplifier input. Sample & Hold circuit (AET-68M): This block (circuit) is a combination of buffer, level shifting network and sample & hold network. Op- amp IC TLO84 is connected as buffer followed by non-inverting summer circuit. One of the inputs of summer is connected a voltage divider network and other being drawn as input. A dedicated sample& hold integrated circuit LF 398 is used as an active component followed by buffer. The LF198/LF298/LF398 is monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high de accuracy with fast acquisition of signal and low droop rate, Operating as a unity gain follower, de gain accuracy is 0.002% typical and acquisition time is as low as 6ys to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of | MHz op amps without having stability problems. Input impedance of 1010(Ohm) allows high source impedance to be used without degrading accuracy. P-channel junction FET’s are combined with bipolar devices in the output amplifier to give droop rates as low as SmV/min with a lyf hold capacitor. The JFET’s have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages. Logic inputs on the LF198 are fully differential with low current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from +5V to +18V supplies. 8 Bit A/D Converter (AET-68M): This has been constructed with a popular 8 bit successive approximation A/D Converter IC ADCO0808. The ADCO0808, data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channe! multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. ‘The 8-channel multiplexer can directly access any of 8-single-ended analog signals. A dedicated 1MHz clock generator is provided in side this block. For complete specifications and operating conditions please refer the data sheet of ADC0808.8 Bit Parallel-Serial Shift register (AET-68M): A dedicated parallel in serial out shift register integrated circuit is used followed by a latch The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode, When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled, Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function, Clocking is inhibited when cither of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. For complete specifications and operating conditions please refer the data sheet of SN74LS166, 8 Bit Serial-Parallel Shift register (AET-68D): A dedicated serial in parallel out shift register integrated circuit is used followed by a latch. The SN74LS 1 64 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features as asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all TTL products. For complete specifications and operating conditions please refer the data sheet of SN74LS164, 8 Bit D/A Converter (AET-68D): This has been constructed with a popular 8 bit D/A converter IC DAC 0808. The DAC0808 is an 8-bit monolithic digital-to-analog converter (DAC) featuring a full scale output current settling time of 150ns while dissipating only 33mW with +5V supplies No reference current (IREF) trimming is required for most applications since the full scale output current is typically +1 LSB of 255 IREF/256. Relative accuracies of better than +0.19% assure 8-bit monotonicity and linearity while zero level output current of less than 4A provides 8-bit zero accuracy for IREF >= 2mA. The power supply currents of the DAC0808 is independent of bit codes, and exhibits essentially constant device characteristics over the entire supply voltage range. For complete specifications and operating conditions please refer the data sheet of DACO808.PCM Operation: the block diagram of the PCM system. The modulating signal is applied to sample & hold circuit. This applied signal will be super imposed by +2.5V DC so that the negative portion the modulating signal will clamped to positive, this process is needed, because input of the A/D Converter should be between 0 and +5V. After level shifting is done the signal will be passed to sample & hold circuit, Sample & hold circuit will sample the input signal during on period of the clock signal and will hold the sampled output till next pulse comes. Sampling rate is 4KHz. in this system. So input of the A/D Converter is a stable voltage of certain level in between 0 and +5V. AUD converter (encoder) will give a predetermined & bit code for the sampled input. This entire conversion process will be made at a fast rate as ADCO8O8 is operating at high frequency clock ie, IMHz. Coded output of the A/D converter is applied to input of the parallel in serial out register through a latch (7418373). This shift register is operating at 64KHz (sampling frequency is 4KHz, so to shift 8 bits from parallel to serial we need 64KHz). This output (PCM) is transmitted through a co-axial cable which represents a communication channel PCM signal from modulator (encoder) is applied to serial to parallel register. This shift register is also operating at 64KHz clock at which parallel to serial shift register is operating at PCM modulator (these both the clock signals should be in synchronized with each other in order to get proper decoded output). So the output of the serial to parallel register is a 8 bit code. This 8 bit code is applied to 8 bit D/A converter. Output of the D/A converter will be a staircase signaling between 0 and +5V. This stair case signal is applied a low pass filter. This low pass will smoothen the staircase signal so that we will get a recovered AF signal. We can use a voltage amplifier at the output of the low pass filter to amplify the recovered AF signal to desired voltage level PROCEDI 1. Connect the modulator trainer to the mains and switch on the power supply. 2. Observe the output of the AF generator using CRO, it should be a sine wave of 200Hz frequency with 3Vpp amplitude. 3. Verify the output of the DC source with multimeter/scope, output should vary from 0 to +SV. 4, Observe the output of the clock generator using CRO, they should be 64KHz and 4KHz frequency of square wave with 5Vpp amplitude. 5. The clock signals are intemally connected the circuit so no external connections are required 6. Connect the demodulator trainer to the mains and switch on the power supply 7. Observe the output of the clock generator using CRO, it should be 64KHz square wave with SVpp amplitude. PCM Operation (with DC input): Modulatio 8. Set DC source to some value say 4.4V with the help of multimeter and connect it to the A/D converter input and observe the output LED's9. Note down the digital code i.e. output of the A/D converter and compare with the theoretical value. Theoretical value can be obtained by: PAE =X 50 V2) Where LSB Value = Vres'2” Since Vrer = SV and n=8 ILSB Value = 0.01953 Example: A/D Input Voltage = 44V 225.2801 11100001 So digital output is 11100001 10. Keep CRO in dual mode, Connect one channel to 4KHz signal (one which is connected to the Shift register) and another channel to the PCM output. 11. Observe the PCM output with respect to 4 Khz signal and sketch the waveforms. Compare them with the given waveforms Note: From this waveform you can observe the LSB bit enters the output first. Demodulation 12. Connect PCM signal to the demodulators(S-P shift register) from the PCM modulator (AET-68M) with the help of coaxial cable. 13. Connect clock signal (64KHz) from the transmitter (AET-68M) to the receiver (AET- 68D) using co axial cable. 14. Connect transmitter clock to the timing circuit 15. Observe and note down the S-P shift register output data and compare it with transmitted data(i.e. output A/D converter at transmitter).You will notice that the output of the S-P shift register is following the A/D converter output in the modulator. 16. Observe D/A converter output (Demodulated output) using multimeter /scope and compare it with the original signal and you can observe that there is no loss in information in process of conversion and transmission. Sample work sheet: 1, Modulating signal 4av 2. A/D Output (theoretical) 1110 0001(2) 3. AID Output (practical): 1110 0001(2) 4, S-P Output 1110 0001(2) 5. D/A Converter output 4aVv (Demodulated output)PCM Operation (with AC input): Modulation: 17. Connect AC signal of 2Vpp amplitude to Sample & Hold circuit. 18. Keep the CRO in dual mode. Connect one channel to the AF signal and another channel to the Sample & Hold output. Observe and sketch the sample & hold output. 19. Connect the Sample and Hold output to the A/D converter and observe the PCM output using Storage oscilloscope. 20. Observe PCM output by varying AF signal voltage. Demodulation: 21. Connect PC! modulator (Al 22. Connect clock signal (64 KHz) from the transmitter (AET- using coaxial cable. 23, Connect transmitter clock to the timing circuit, 24, Keep CRO in dual mode. Connect CH! input to the sample and hold output (AET-68M) and CH2 input to the D/A converter output (AET-68D) 25. Observe and sketch the D/A output. 26. Connect D/A output to the LPF input. 27. Observe the output of the LPF/Amplifier and compare it with the original modulating signal (AET-68M). 28. From above observation you can verify that there is no loss in information (modulating signal) in conversion and transmission process. 29. Disconnect clock from transmitter (AET-68M) and connect to local oscillator (i.e.,Clock generator output from AET-68D) with remaining setup as itis. Observe D/A output and compare it with the previous result. This signal is little bit distorted in shape. This is because lack of synchronization between clock at transmitter and clock at receiver. Note: You can take modulating signals from external sources. Maximum amplitude should not exceed 4V incase of DC and 3 Vpp incase AC (AF) signals. signal to the demodulator input (AET-68D) (S-P shift register) from the PCM, 68M) with the help of coaxial cable (supplied with the trainer). 8M) to the receiver (Al 8D)- mocd-rvEp o4tro< ) 4 (ins) | HOLL + > a 2 = = 4 Fig2.2 PCM Waveform with AC Input 7)WITH DC INPUT: cook 14108) SROOnOn NON noon =| = oo __["s em ee seRegireaps 118004 LED nfiaton NSS) PCM Modulation with AC input OBSERVATIONS: ‘Amplitude Time period ‘AC input ‘Sample and hold circuit Clock signal(4KHz) Clock signal(64KH2) PCM Output D/A converter output signal LPF output signal Demodulated outputPCM Modulation with DC input ‘Amplitude Time period DC input, Clock signal(4KHz) Clock signal(64KHz) PCM Output PCM Demodulated (with DC input) ‘Amplitude Time period D/A converter output signal LPF output signal Demodulated output RESUL! Thus the Pulse Code modulation and demodulation were performed and graphs were plotted. VIVA QUESTIONS: 1, What do you mean by quantizing process 2. What will happen when sampling rate is greater than Nyquist rate ? 3, What will happen when sampling rate is less than Nyquist rate ? 4, Find the A/D Converter output for input DC voltage of 3.6V. 5, Fig shown below shows a PCM wave in which the amplitude levels of + volt and -1 volt are used to represent binary symbols | and 0 respectively. The code word used consists of three bits. Find the sampled version of an analog signal from which this PCM wave is derived. 6. Mention some applications of PCM. 7. What is the function of Sample and Hold circuit? MATLAB CODE: % Pulse Code Modulati (Pc P=5; “percentage of errors in transmission % sampling t= [0:0.1:1*pi]; % Times at which to sample the sine function sig = 4*sin(0); % Original signal, a sine w: Yesig-exp(-1/3*0) % quantization Vh=max(sig); Vi-min(sig); N=3;M=2°N; Vh-VIVM; %design N-bit uniform quantizer with stepsize=$partition = [VI+S:S:Vh-S]; % Length M-l, to represent M intervals codebook = [VI+S/2:8:Vh-S/2]; % Length M, one entry for each interval % partition = [-1:.2:1]; % Length 11, to represent 12 intervals codebook = [-1.2:.2:1]; % Length 12, one entry for each interval [index,quantized_sig,distor] = quantiz(sig,partition,codebook); % Quantize. % binary encoding codedsig—de2biCi codedsig=codedsig’; txbits-codedsig(:); Yoserial transmit errvec=randsre(length(txbits),1,[0 1;(1-P/100) P/100)); %error vector lex, left-msb’); Yrxbits-xor( Ixbits,errver) rxbits-remi(txbits Ferrvec,2); %bits received rxbits-reshape(rbits,Nlength(sig)); rxbits=rxbits' index 1=bi2de(rxbits, lefi-msb’); Yodecode reconstructedsig=codebook(index +1); Yore-quantize %plotit.sig,'’t,quantized sig Yplotit.sig,'x-t,quantized_sig, Yofigure,stem(t.sig,’x-);hold;stem(t,quantized si figure, subplot(2,2,1); stem(tsig); xlabel( time’); title( original signal’); subplot(2,2,2); stem(t,quantized_sig); xlabel( time’); title quantized signal’; ‘t=[0:N*length(t)-1]; subplot(2,2,3); stairs(t,txbits); xlabel(time’); title(PCM waveform’); subplot(2,2,4); stem(t,reconstructedsig); xlabel( time’); title(received signal); “t,reconstructedsig,'d~’) !.-:stem(t,reconstru edsig,/d-)OUTPUT WAVE FORM