Unit 1

Questions and answers

Q1. Draw & explain architecture of 8086?
• 8086 is a 16-bit microprocessor and was designed in 1978 by Intel. Unlike, 8085, an
8086 microprocessor has 20-bit address bus. Thus, is able to access 220 i.e., 1 MB
address in the memory.
• As we know that a microprocessor performs arithmetic and logic operations. And an
8086 microprocessor is able to perform these operations with 16-bit data in one cycle.
Hence is a 16-bit microprocessor. Thus the size of the data bus is 16-bit as it can carry
16-bit data at a time.
• The architecture of 8086 microprocessor is composed of 2 major units, the BIU i.e.,
Bus Interface Unit and EU i.e., Execution Unit.

Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) manages the data, address and control buses.
The BIU functions in such a way that it:
• Fetches the sequenced instruction from the memory,
 • Finds the physical address of that location in the memory where the instruction is
stored and
Manages the 6-byte pre-fetch queue where the pipelined instructions are stored
BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction connection
with System Buses so this is possible with the BIU. EU and BIU are connected with the
Internal Bus.
It has the following functional parts −
• Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions
and is ready for its next instruction, then it simply reads the instruction from this
instruction queue resulting in increased execution speed.
Fetching the next instruction while the current instruction executes is called pipelining.
Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory
locations. It also contains 1 pointer register IP, which holds the address of the next instruction
to executed by the EU.
CS − It stands for Code Segment. It is used for addressing a memory location in
the code segment of the memory, where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used by
the string to hold the extra destination data.
Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to
be executed.

EU (Execution Unit)

Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the
instruction decoder & ALU. EU has no direct connection with system buses as shown in the
above figure, it performs operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the
result stored in the accumulator. It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.
Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the
list of conditional flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e.
carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary
to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For
odd number of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation
is negative, then the sign flag is set to 1 else set to 0.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The
valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the
AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address
of the memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
• DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack
Q.2 Draw and explain software model of 8086?
The software architecture of the 8088 microprocessor includes
13 16-bit internal registers:
• the instruction pointer (IP),
• four data registers (AX, BX, CX, and DX)
• two pointer registers (BP and SP)
• two index registers (SI and DI)
• four segment registers (CS, DS, SS, and ES)
There is another register called status register (SR), with nine
of its implemented for status and control flags.
8088 software architecture implements independent memory and input/output address
spaces. Memory address space is 1,048,576 (1 Mbyte) in length and the I/O address space is
65,536 bytes (64Kbytes) in length.
Q.3 What is register? Explain segment registers in detail?

• Processor operations mostly involve processing data. This data can be stored in
memory and accessed from thereon. However, reading data from and storing data
into memory slows down the processor, as it involves complicated processes of
sending the data request across the control bus and into the memory storage unit and
getting the data through the same channel.
• To speed up the processor operations, the processor includes some internal memory
storage locations, called registers.
• The registers store data elements for processing without having to access the
memory. A limited number of registers are built into the processor chip.
1MB memory is partitioned into 64KB byte segments.
Each segment is assigned a base address that identifies its starting point, that is its
lowest addressed byte storage location.
Only four of these segments are active at a time. They are called the Code, Data, Stack
and Extra segments. The base address of each of these 4 active segments are stored
in four internal registers.
Those 4 segment registers are:
• Code Segment Register(CS)
• Data segment Register(DS)
• Stack Segment Register(SS)
• Extra Segment Register(ES)

• CS (Code Segment)

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.

• Stack segment (SS)

Stack segment is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer
(SP) and base pointer (BP) registers is located in the stack segment. SS register can be
changed directly using POP instruction.

• Data segment (DS)

Data segment is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers
 (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register
can be changed directly using POP and LDS instructions.

• Extra segment (ES)

Extra segment is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the
ES segment in string manipulation instructions. ES register can be changed directly
using POP and LES instructions.It is possible to change default segments used by
general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.

• Restriction on Segment

There is one restriction on the value that can be assigned as a base address that is it
must reside on a 16- byte address boundary i.e. its last four bits should be zero.Other
that this segment can be contiguous, adjacent, disjoint, or overlapping.

Q.4 Explain Flag registers in detail?

8086 has a 16 bit flag register which is also called as program status word(PSW).

S Z X AC X P X CY

Condition flags
The conditional flags are set or reset after any arithmetic or logical operation is performed on
an 8 bit or 16-bit number. This category consists of the following 6 flags:
1. Carry Flag (CF): The carry flag will be set only if a carry is generated from the MSB of the
result after doing any operation in 8086 Microprocessor.
2. Parity Flag (PF): Parity is related to the number of 1’s contained in the binary data. There
exist two types of parity:
i. Even Parity: When the number of 1’s in the binary data are even.
ii. Odd Parity: When the number of 1’s in the binary data are odd.
For the flag, the PF is set if there exists an even parity in data after the execution of the
instruction. Else the flag is reset.
3. Auxiliary-Carry Flag (AF): This flag is set if there is a generation of carrying from a nibble,
i.e. 4 bits of data.
4.Zero Flag (ZF): If the result after performing the required operation (Arithmetic or Logical)
on the instructions is zero, in that case, the zero flags are set to 1. Else, it remains reset.
5. Sign Flag (SF): If the result after performing any arithmetic or logic operation in the given
instruction is negative, then the sign flag is set to 1. Else, for a positive result, the sign flag
remains reset.

Q.5 What are the data types supported by 8086 ?

Unsigned integer numbers: each type of integer can be either byte-wide or word-wide.
 Unsigned byte integer can be used to represent decimal
numbers in the range 0 through 255.
 The unsigned word integer can be used to represent decimal numbers in the range 0
through 65,535.

2. Signed integer numbers: each type of integer can be either byte-wide or word-wide.
The most significant bit in signed integer data type is a sign bit. A zero in this position
identifies a positive number.
The Signed byte integer can be used to represent decimal numbers in the range +127 to –
128.
The signed word integer can be used to represent decimal numbers in the range +32,767 to
–32,768.
3. Binary-coded decimal (BCD) numbers: BCD data can be stored on either unpacked or
packed form. In unpacked BCD, a single BCD digit is stored in four least significant bits, and
the four bits are set to 0. In packed BCD, two BCD numbers are stored in a byte.

4. ASCII (American Standard Code for Information Interchange) : ASCII codes can be
processed by 8088 microprocessor. For example, 65H is ASCII code for A. This will be stored
as 01100101 in the memory.

0 1 1 0 0 1 0 1
Q.6 The value of Code Segment (CS) Register is 4042H and the value of
different offsets is as follows:
BX: 2025H , IP: 0580H , DI: 4247H. Calculate the effective address of the
memory location pointed by the CS register.

Ans:

The offset of the CS Register is the IP register.

Therefore, the effective address of the memory location pointed by the CS register is
calculated as follows:

Effective address= Base address of CS register X 10H + Address of IP

= 4042H X 10H + 0580H

= (40420 + 0580)H
= 41000H

Q.7) Calculate the effective address for the following register:

SS: 3860H, SP: 1735H, BP: 4826H

Ans:

Both SP and BP are the offsets for Stack Register (SS). The address calculated when BP is
taken as the offset gives the starting address of the stack. The address when SP is taken as
the offset denotes the memory location where the top of the stack lies.

Therefore, the effective address for both these cases is:

(SS X 10H) + SP = 3640H X 10H + 1735H

= 36400H + 1735H
= 38135H
(SS X 10H) + BP = 3640H X 10H + 4826H
= 36400H + 4826H
= 41226H
Q.8 How the Double word is stored in memory ?Explain aligned and
misaligned word?
The double word is another data from that can be processed by 8086/8088.A double word
correspond to 4 consecutive byte of data stored in memory. It Is used to access data in memory.
The word of data stored at higher address is called segment base address and word at lower
address is called the offset Just like word ,double word can be aligned or misaligned

The double words of data can be stored at what are called even or odd address boundaries. The
least significant bit of address determine the type of word boundary. If bit is 0 ,4, the word is
at even address boundary. If LSB bit is 1, 3 or 5…means double word stored at odd address
boundary. It occupy 4 byte of memory.
The double word data stored at even address boundary is called aligned word and word stored
at odd address boundary is called misaligned double word.
Double word 0, 4 and 2 are stored at even address boundary are called aligned double word.
Double word 1,3 and 5 are stored at odd address boundary are called misaligned double word
Q.9. Draw 8086 pin diagram and Explain following pins (1) ALE (2) IO/M’ (3)
READY (4) HLDA (5) INTA?
8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let
us now discuss in detail the pin configuration of a 8086 Microprocessor

Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges
the HOLD signal.

Q.10 What is Assembly Language?/What is low level language?

Each personal computer has a microprocessor that manages the computer's arithmetical,
logical, and control activities.
Each family of processors has its own set of instructions for handling various operations such
as getting input from keyboard, displaying information on screen and performing various
other jobs. These set of instructions are called 'machine language instructions'.
A processor understands only machine language instructions, which are strings of 1's and
0's. However, machine language is too obscure and complex for using in software
development. So, the low-level assembly language is designed for a specific family of
processors that represents various instructions in symbolic code and a more understandable
form.
An assembly language is a type of low-level programming language that is intended to
communicate directly with a computer’s hardware.
Low-level programming languages such as assembly language are a necessary bridge
between the underlying hardware of a computer

Properties of Lower Level Language/ Programming

 Low-level languages are far from human languages.
 Programs in low-level languages are fast in execution.
 Programs in low-level languages are difficult to modify.
 Deep knowledge of hardware is required programs.
 Low-level languages are difficult to learn.
Q.11 What does Simple Computer Model comprise of?

central processing unit (CPU), principal part of any digital computer system, generally
composed of the main memory, control unit, and arithmetic-logic unit. It constitutes the
physical heart of the entire computer system; to it is linked various peripheral equipment,
including input/output devices and auxiliary storage units. In modern computers, the CPU is
contained on an integrated circuit chip called a microprocessor.The CPU is the heart of the
computer, most of computations occur inside the CPU.
RAM stands for random-access memory, but what does that mean? Your computer RAM is
essentially short term memory where data is stored as the processor needs it. This isn’t to be
confused with long-term data that’s stored on your hard drive, which stays there even when
your computer is turned off. Anytime you play a game from your computer’s hard drive or
stream a movie from the Internet, all of the data that your computer’s processor needs to
play the game or watch the movie is stored in RAM. This is so that your processor can get to
it quickly. Once you’re done playing your game or watching your movie and you close it down,
the processor doesn’t need that data anymore, so it replaces it with the next task you give it.
RAM can slow down your computer if there isn’t enough of it for the processor to perform
the tasks you ask it to. If your processor wants to load more data than your computer RAM
can handle, it has to keep going back to the hard drive or the Internet to obtain the
information again. This is just like someone trying to pick up more tennis balls than they can
carry; in the end, they spend more time picking up tennis balls than playing the game!
What Does System Bus Mean?

The system bus is a pathway composed of cables and connectors used to carry data between
a computer microprocessor and the main memory. The bus provides a communication path
for the data and control signals moving between the major components of the computer
system. The system bus works by combining the functions of the three main buses: namely,
the data, address and control buses. Each of the three buses has its separate characteristics
and responsibilities.

Q.12 What is inside CPU?/How many parts CPU is divided into? Which are
those?

central processing unit (CPU), principal part of any digital computer system, generally
composed of the main memory, control unit, and arithmetic-logic unit. It constitutes the
physical heart of the entire computer system; to it is linked various peripheral equipment,
including input/output devices and auxiliary storage units. In modern computers, the CPU is
contained on an integrated circuit chip called a microprocessor.The CPU is the heart of the
computer, most of computations occur inside the CPU.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The
valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the
AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address
of the memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
• DX register − This register is used to hold I/O port address for I/O instruction.
Segment Registers
• CS − It stands for Code Segment. It is used for addressing a memory location in the
code segment of the memory, where the executable program is stored.
• DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
• SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
• ES − It stands for Extra Segment. ES is additional data segment, which is used by the
string to hold the extra destination data.
Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to
be executed.
SP (Stack pointer register)
It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack

BP – This is the base pointer. It is of 16 bits. It is primary used in accessing parameters passed
by the stack. It’s offset address relative to stack segment.

SI – This is the source index register. It is of 16 bits.It is used in the pointer addressing of data
and as a source in some string related operations. It’s offset is relative to data segment.

DI – This is the destination index register. It is of 16 bits.It is used in the pointer addressing of
data and as a destination in some string related operations.It’s offset is relative to extra
segment.

Arithmetic-logic unit (ALU)? An arithmetic-logic unit is the part of a central processing unit
that carries out arithmetic and logic operations on the operands in computer instruction
words.

Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the
list of conditional flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e.
carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary
to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For
odd number of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation
is negative, then the sign flag is set to 1 else set to 0.
 UNIT 02

1] Explain Addressing Modes of 8086 in detail. (7 M)

OR
What do you mean by addressing modes? Explain with
example various memory operand addressing modes.
(7 M)
OR
Explain the following addressing modes of8086.
i) Direct addressing mode.
ii) Based Index addressing mode.
iii) Index addressing mode. (6 M)

Ans : When the instructions are executed in 8086 ,it performs on the
specified data i.e. Operand . the operand may me resides in the one of the
internal register of the microprocessor, may be stored at an address in
memory, to access this different types of operand, the 8086 is provided with
various Addressing Modes. Addressing modes indicates a way of locating data
or operands. The addressing modes are classified into basic three types :
1) Register operand addressing
2) Immediate operand addressing
3) Memory operand addressing

1} Register Operand Addressing : The operand to be accessed is

specified as residing in an internal registers of 8086.( The instruction
performed on the operands are stored in the registers.) Operand may be byte
or word.
e.g. MOV AX , BX
In the above instruction the operand is stored in the register BX (source) which
has to be move to the register AX (destination).
2} Immediate Operand Addressing : If an operand is a part of the
instruction instead of the contents of the register or memory location, that
operand is said to immediate operand (operand is directly given in instruction.)
And the addressing mode use for these operands are immediate addressing
mode. The operand may be byte or word.
e.g. MOV AL , 15H
In the above instruction the operand 1516 (source) is immediate operand which
has to be move to the lower byte of AH register i.e. AL(destination)
3} Memory Operand Addressing : To an operand in the store in the
memory and to fetch that address we need to calculate the effective
address(EA). This addressing mode consist of the different representation of
the EA. The memory operand addressing is further divided into following parts:
*1] Direct Addressing Mode : In this addressing mode the 16-bit EA is taken
directly from the displacement field of the instruction. The displacement
(unsigned 16-bit or signed-extended 8-bit number ) is stored in the location
following the instruction.
E.g. Mov AL , [3000H] : here 3000H is the offset address and by default the
content of Data Segment will be segment address . The combination of these
two addresses having the address of particular memory location that content
some data which is moved to AL register.
2] Register Indirect Addressing Mode : In this mode, the EA is specified in
either a pointer register or an index register. The pointer register can be either
base register (BX) or base pointer(BP) and the index register can be either
source index (SI) or destination index (DI). The physical address is computed by
using DS and EA .
e.g. MOV [DI] , BX : The instruction copied the 16-bit content of BX into the
memory location offset by the value of EA specified in the DI from the current
contents in DS. Now , if we consider [DS]=7205H , [DI]= 0030H and BX = 8765H,
the after execution of instruction , the content of BX is copied to the memory
locations 72080H and 72081H
Physical Address: [DS]x [10H]+EA = [DS]x [10H] + [DI]
3] Base Addressing Mode : In this addressing mode , the effective address of
the operand is obtained by adding a direct or indirect displacement to the
contents of either base register(BX) or base pointer (BP). To find the actual
physical address this displacement is also added to the segment address and
offset address.
e.g. MOV AX , [BP + 6] : If the content of BP =2300H and SS=1000H then the
content of memory locations 12306H and 12307H will move to the 16-bit
destination register AX
*4] Index Addressing Mode : This addressing mode uses only one of the two
index registers (SI or DI) and the 8-bit or 16-bit displacement is included in the
operand field. To find the actual physical address this displacement is also
added with segment address and offset address.
e.g. MOV AX , [SI + 16] : If the content of SI=1400H and DS =4000H then the
contents of memory locations 41416H and 41417H are move to the 16-bit
destination Register AX.
*5] Base Index Addressing Mode : This addressing Mode combines the
features of the Base Addressing Mode and Index Addressing Mode but does
not allow the use of a displacement . Two registers must be used as source and
destination operand , one for BX/BP or another for SI/DI. This combination of
two register can be written as [BX][DI] or [BX+DI] both have the same meaning
and gives the total offset value with addition of these registers.
e.g. MOV [BP][SI] , AL : If the content of SS=0400H , BP= 4320H and SI= 4000H
and AL = 34H is given the physical address will be calculated as SS*10H+BP+SI so
04000H+4320H+4000H = 0C320H, the content of AL register will be load at
0C320H memory location .
2] Explain following instruction :
1) DAS 2) SBB 3) XALT 4) DAA
5)ADC 6) SUB 7) IMUL 8) LDA / LES
10) XCHG 11) IN (each for 3M/4M)
Ans :
1) DAS :
This instruction is decimal adjust after subtraction is similar to
DAA instruction except that this adjusts decimal result after subtraction
.This instruction internally performs following steps :
Step 1: Check lower nibble of AL;
If it is greater than 9,
Subtract 6 to this nibble.
Else
No change.
Step 2: Check upper nibble of AL:
If it is greater than 9,
Subtract 6 to this nibble
Else
No change.
Example :
MOV AL ,10 ; AL = 10H
SUB AL , 3 ; AL = 10H – 3H will give result 0DH in AL.
DAS ; because lower nibble is greater than 9,
; subtracted by 6 , will give result 7.
; upper nibble is zero , so on change.
Finally
; AL = 07 . This is our result.
2)SBB :
The operation of SBB is similar to SUB. However in subtraction to
the source operand the processor also subtract the content of carry flag.
It is primarily used for multiword subtract operation.
 Destination = Destination – Source – Carry
Syntax : SBB Destination , Source
Example : SBB BX , CX
If the contents of BX=1234H and contents of CX=0123H then
after execution the result i.e. content of BX=1111H carry flag will remain
unset as no borrow is taken.

3)XALT :
This instruction converts the content of the AL registers into a
number stored in a memory table. This instruction performs the direct table
lookup techniques, which is often used to convert one code to another .An
XLAT instruction first adds the content of AL to BX to form a memory
address within the data segment . It copies the content of this address into
AL. This is the only instruction that adds the 8-bit number to a 16-bit
number.
Syntax : XLAT
Example : Suppose a translation table resides at address 2000H (contents
of BX registers ) and AL=05H and DS=4000H then the working of XLAT
instruction will check the memory location of the address DS * 10H + BX +
AL i.e. 42005H which contains 8AH then the AL=8AH.
4)DAA :
Sometimes we need to add decimal numbers together and assumes
results as decimal , but processor solves numbers treating as a hexadecimal
numbers so it is not always possible to get correct decimal result after addition
. For example we want to add 23 and 18, processor will treat these numbers as
hexadecimal numbers and gives answer 3BH , which is not correct answer form
our respect , so DAA instruction is able to correct this instruction adjust only
lower byte of AX. This instruction internally performs following steps :
Steps1: Check lower nibble of AL ;
If it is greater than 9,
Add 6 to this nibble . Auxiliary carry will be set.
Else
No change . Auxiliary carry will be clear.
Step 2 : Check upper nibble of AL :
If it is greater than 9,
Add 6 to upper nibble with Auxiliary carry
Else
Add upper nibble with Auxiliary carry.

Syntax : DAA
Example : ADD AL , BL
DAA
5) ADC :
The operation of ADC is similar to ADD .However , in addition to
the source operand the processor also add contents of the carry flag . The ADC
is commonly used to add multi-bytes together , basically more than storage
capacity. Destination = Destination + Source + Carry
Syntax : ADC Destination, Source
Example : Suppose we want to perform 32-bit operation , but we have 16-bit
register in 8086,so we can store only 16-bit in any register. Consider AX store
lower 16-bit number AC59H . Now add the contents of AX register with 9678H ,
which will give result 42D1H and carry flag will be set
Now , our aim is to add upper 16-bit numbers (7654H + 24447H)
and we have to add carry too these numbers to get correct result. This
operation can not be performed by simple ADD instruction , so we need a new
instruction which will add the operands as well as carry , hence this instruction.
6) SUB :
This instruction is used to subtract 8-bit(byte) or 16-bit (word)
operands together. If source operand is larger than the destination operand ,
the resulting borrow is indicating by setting carry flag.
Syntax : SUB Destination , Source
Example : SUB AX , BX
 If AX=1234H and BX= 4321H the after the execution of instruction
the AX will be CF13H and carry flag will be set to indicate borrow was taken.
7) IMUL :
This instruction is similar to MUL expert that operands are
assumed to be a signed numbers. The source operand specified in the
instruction is multiplied by accumulator , if source is 8-bit it multiplies with AL
and result is placed into AX register. If source is 16-bit then it multiplies with Ax
register and result is placed into DX : Ax registers
Syntax : IMUL Source
Example : IMUL BL If AL =80H and BL=20H, The content of AL will be treated as
signed number which is 2’s complement of (128)10 which is -128 * 32 then
multiplication of these numbers is -4096 , the 2’s complement of this number
is F000H . So finally AX will be F000H.
8) LDS / LES :
These instruction are used to load two 16-bit registers
from a 4-byte block of memory . The first two bytes are copied into destination
registers and the next two bytes are copied into corresponding segment
registers DS / ES . These instruction are useful when we want to load segment
and offset value by using single instruction. Usually in string instruction we use
the instruction to load source string address (DS:SI) and destination string
address (ES:DI) using single instruction
Syntax : LDS / LES Destination , Source
Example : LEA SI , EA When executed it loads the SI register with the offset
address value. The value of this address is represented by the effective address
EA. The value of effective address can be specified by any valid addressing
mode. For instance , if the value in DI equals 1000H and that in BX is 20H , then
executing the instruction
LEA SI , [DI + BX + 5H]
Will load SI with the value (SI)= 1025H
9) XCHG :
This instruction is used to swap the data . After executing this
instruction destination and source will swap .
Syntax : XCHG Destination , Source
Example : XCHG AL , BL If AL = 34H and BL= 76H then after execution AL will be
76H and BL=34H.
10) IN :
Processor has a separate I/O space from its memory space . among
them 65536 I/O ports available for the programmer to use.
These ports can be access directly , using the ports address , for 65536
ports address in 0000H to FFFFH , the input port is actually a hardware device
connected to the processor’s port . The 8086 allows two different forms of the
IN instruction. A fyll 16-bit ports address must be loaded into DX register and
instruction like IN Al , DX or IN AX , DX may be used to read the input port . If
the port number is in between 00H to FFH then another form of IN instruction
may be used as In AL , 86H or IN AX , 80H.
Syntax : IN accumulator , port
Example : If we want to read input 80 H then we may give instruction like
IN AL , 08 H or MOV DX , 80H
IN AL , DX
3] Explain Instruction format of 8086.
Ans :
•A machine language instruction format has one or more number of fields
associated
with it.
•The first field is called as operation code field or op-code field, which
indicates the
type of operation to be performed by the CPU
•The instruction format also contains other fields known as operand fields
•The CPU executes the instruction using the information which reside in these
fields
•There are six general formats of instructions in 8086 instruction set.
•The length of an instruction may vary from 1 byte to 6 bytes. The instruction
formats
are described as follows
1] One Byte Instruction:
•This format is only one byte long and may have the implied data or register
operands.
•The least significant 3-bits of the opcode are used for specifying the register
operand, if any
•Otherwise, all the 8 bits form an opcode and the operands are implied
2] Register to Register:
•This format is 2 bytes long
•The first byte of the code specifies the operation code and width of the
operand specified by ‘w’ bit.
•The second byte of the code shows the register operands and R/M field, as
shown below:
•The register represented by the REG field is one of the operands.
•The R/M field specifies another register or memory location i.e. the other
operand.

3] Register to/from memory with no displacement:

•This format is also 2 bytes long and similar to the Register to Register format
except for the MOD field as shown.

•The MOD field shows the mode of addressing. The MOD, R/M, REG and the
‘W’ fields are decided in Table 2.2.
4] Register to/from Memory with Displacement:
•This type of instruction format contains 1 or 2 additional bytes for
displacement along with 2 byte format of the register to/from memory
without displacement. The format is as shown below.

5] Immediate Operand to Register:

•In this format, the first byte as well as the 3-bits from the second byte which
are used for REG field in case of register to register format are used for
opcode.
•It also contains one or two bytes of immediate data. The complete instruction
format is as shown below.

6] Immediate Operand to Memory with 16-bit displacement:

•This type of instruction format requires 5 or 6 bytes for coding.
•The first 2 bytes contain the information regarding OPCODE, MOD and R/M
fields.
The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data as
shown.
4] State and Explain Arithmetic group of Instruction.
Ans :
The operation such as Addition , Subtraction , Multiplication and
Division are the arithmetic . To perform these operation the 8086 is provided
with the arithmetic group of instruction which consist of following instruction :
Addition :
1] ADD : This instruction is use to perform addition of two 8-bit or 16-bit
registers or immediate operand
e.g. ADD AX , BX
2] ADC : This instruction is use to perform addition of two 8-bit or 16-bit
registers or immediate operand and the content of carry flag are added to the
result if it is set.
e.g. ADC AX , BX
3] INC : The instruction increases the operand by one
e.g. INC AX
4] AAA: After performing the addition of the ascii values the result is adjust by
ascii to get the required output. This instruction is used after ADD instruction
e.g. ADD AX , BX
AAA
5] DAA : The instruction is performed on the packed BCD numbers after
performing operation the result is adjust with the decimal. It is used after ADD
instruction.
e.g. ADD AL , BL
DAA

Subtraction :
1] SUB : This instruction is used to subtract two operand representing in an
form of addressing modes .
e.g. SUB AX , BX
2] SBB : After performing the subtraction of the if the borrow is taken then the
carry flag is set . So, the content of carry flag are also subtracted from the
result.
e.g. SBB AL , BL
3] DEC : The decrease the operand by 1 .
e.g. DEC AL
4] AAS : After performing the subtraction of the ascii values the result is adjust
by ascii to get the required output. This instruction is used after SUB
instruction.
e.g. SUB AL , BL
AAS
5] DAS : The instruction is performed on the packed BCD numbers after
performing operation the result is adjust with the decimal. It is used after SUB
instruction.
e.g. SUB AL , BL
DAS
6] NEG : The operand is convert to its 2’s complement
e.g. NEG AL

Multiplication / Division :
1] MUL : It multiplies the two unsigned integer values, one of the operand
always resides in the AX register.
e.g. MUL BL
2] IMUL : It multiplies the two signed integer values, one of the operand always
resides in the AX register.
e.g. IMUL BL
3] AAM : It adjust the AX register for multiplication
4] DIV : 1] MUL : It divide the two unsigned integer values, one of the operand
always resides in the AX register.
e.g. DIV BL
5] IDIV : It divides the two signed integer values, one of the operand always
resides in the AX register.
e.g. IDIV BL
6] AAD : It adjust the AX register for division.
7] CBW : It convert the Byte value to the Word value i.e. 8-bit to 16-bit
8] CWD : It convert the word to the double word i.e. 16-bit to 32-bit
e.g. MOV AL , 0A1H
CBW
CWD
5] Assume that (AX)=001016 , (BX)=010016 and (DS)=100016,
What happens if XLAT instruction is executed?
Ans : Given,
(AX) = 001016
(BX) = 010016
(DS) = 100016
Hence lookup table resides at DS x 10 i.e. 10000H
+ BX 0100H
10100H
So the lookup table is at the address 10100H . The value of the AL=10H.The
data from the memory location will transfer to the AL register.
6] Assume that (AX)=110016 , (BX)=0ABC16. What is the
result of executing instruction ADD AX,BX?
Ans :
Given,
(AX)= 110016
(BX)= 0ABC16
Instruction : ADD AX, BX
The content of register AX and BX are added and the result is stored in the AX
register
(AX) = 110016 = 0001000100000002
ADD
(BX) = 0ABC16 =0000101010111100 2
(AX) =1BBC 16= 00011011101111002
Hence after executing the instruction the result stored in the AX is 1BBC16.
7] Write a program to add 8-bit data at offset 0400H in
3000H segments to another 8-bit data available at 0500H
offset in the same segment and store the result at 0700H
in the same segment.
Ans :
MOV AX , 3000H ; Move the data 3000H into AX register
MOV DS , AX ; The content of AX i.e. 3000H is move to DS

The above two instruction establish the Data Segment and set segment
address to 3000H.

MOV AL , [0400H] ; The 8-bit content of memory location having

Address 3000H : 0400H are move to 8-bit AL
Register
ADD AL , [0500H] ; The content of memory location having address
3000H : 0500H are added with the content of AL
register and result is store in AL register
MOV [0700H] , AL ; the 8-bit content of AL register are moved to the
memory location having address 3000H : 0700H
8] Assume that (AX) : ABCD16 and (BX) : 432116. What is
the result of executing ADD AX ,BX ?
Ans :
Given,
(AX)= ABCD16
(BX)= 432116
Instruction : ADD AX, BX
The content of register AX and BX are added and the result is stored in the AX
register
(AX) = ABCD16 = 10101011110011012
ADD
(BX) = 432116 = 01000011001000012
(AX) = DDDD16= 11101110111011102
Hence after executing the instruction the result stored in the AX is DDDD16.
9] Two byte sized register are stored at the symbolic
offset address NUM1 and NUM2 respectively. Write an
instruction sequence to generate their sum and store it at
NUM3. The SUM is to be formed by adding the values at
NUM1 and that at NUM2. Assume that all storage location
are in the current data segment. (6 M/7 M)
Ans :
Let us assume that the memory locations NUM1 ,NUM2 and NUM3 are
in the same data segment
MOV AX, @data ; Establish data segment
MOV DS , AX
MOV AL, [NUM1] ; Get the second BCD number
MOV AL, [NUM2] ; Adding the values
DAA ; Apply BCD adjustment
MOV [NUM3] , AL ; Save the result
10] Memory location 00490H through 00493H contain
respectively 0A,9C, 82 and 78. What does AX contain
after each instruction? (Assume that SI contains 0490H
and BP contain 0002H)
i) MOV Ax, [SI]
ii) MOV Ax, [SI +1]
iii) MOV Ax, [SI] [BP]. (6 M)
Ans :

0A 00490H

9C 00491H

B2 00492H

78 00493H

Given , (SI) = 0490H

= 0490H x 10H
= 04900H
(BP)= 0002H
i] MOV AX , [SI]
In this instruction the content of memory location whose address is contain by
SI is moved to the AX register. The content of memory location 00490H is 0AH
and 00491H is 9CH .Hence, the content of 00490H and 00491H is moved to the
register AX as AX is a 16-bit. After performing instruction the content of AX will
be:
(AX)=(9C0A)16
ii] MOV AX , [SI + 1]
In this instruction the content of memory location whose address is contain by
(SI + 1) is moved to the AX register. The memory address contain by (SI + 1) is
00491H .The content of memory location 00491H is 9CH and 00492H is B2H.
Hence, the content of 00491H and 00492H is moved to the register AX. After
performing instruction the content of AX will be:
(AX)=(B29C)16

iii] MOV AX , [SI] [BP]

In this instruction the content of memory location whose address is contain by
(SI + BP) is moved to the AX register. The memory address contain by (SI + BP)
is 00492H .The content of memory location 00492H is B2H and 00493H is 78H.
Hence, the content of 00492H and 00493H is moved to the register AX. After
performing instruction the content of AX will be:
(AX)=(78B2)16
 Unit 3 - Instruction Sets
1. What are logical Instructions?
Logical instructions of a microprocessor are simply the
instructions that carry out basic logical operations such as
OR,AND,XOR and NOT.
In the 8085 microprocessor,the destination operand is
always the accumulator. Logical operations works on a
bitwise level.
AND,OR,XOR and NOT instructions.
1.AND

A B F=AB
0 0 0
0 1 0
1 0 0
1 1 1

2.OR

A B F=AB
0 0 0
0 1 1
1 0 1
1 1 1
 3.NOT
A F=A
0 1
1 0
4.XOR

A B F=AB
0 0 0
0 1 1
1 0 1
1 1 0

Mnemonic Meaning Format Operation Flags Affected

AND Logical AND D,S S.D → (D) OF,SF,ZF,PF,CF
AND AF undefined
OR Logical OR D,S S+D → (D) OF,SF,ZF,PF,CF
OR AF undefined
XOR Logical XOR D,S S + D → (D) OF,SF,ZF,PF,CF
XOR AF undefined
NOT Logical NOT D D → (D) None
NOT

Allowed Operands for AND,OR and XOR instructions

DESTINATION SOURCE

Register Register Allowed Operands for

Register Memory NOT instructions.
Memory Register
Register Immediate
Memory Immediate DESTINATION
Accumulator Immediate Register
Memory

2. What are Shift Instructions?

The four shift instructions of the 8088 can perform two basic
types of shift operations : the logical shift and the arithmetic
shift. Moreover,each of these operations can be performed to
the right or to the left.The shift instructions are shift logical
left(SHL),shift arithmetic left(SAL),shift logical right(SHR) and
shift arithmetic right(SAR).
These instruction are used to align data,to isolate bits of a
byte or word so that it can be tested,and to perform simple
multiply and divide computations.
Mnemonic Meaning Format Operation Flags Affected
SAL/SHL Shift SAL/SHL D, Shift the D CF,PF,SF,ZF
arithmetic Count left by the AF undefined
left/Shift number of OF undefined if
logical left bit count #1
positions
equal to
Count and
fill the
vacated bit
positions
on the
right with
Zeros.
SHR Shift SHR D, Shift the D CF,PF,SF,ZF
Logical Count right by the AF undefined
Right number of OF undefined if
bit count #1
positions
equal to
Count and
fill the
vacated bit
positions
on the left
with Zeros.
SAR Shift SAR Shift the D SF,ZF,PF,CF
arithmetic D,Count right by the AF undefined
Right number of OF undefined if
bit count #1
positions
equal to
Count and
fill the
vacated bit
positions
on the left
with the
original
most
significant
bit.
Allowed Operands

DESTINATION COUNT

Register 1
Register CL
Memory 1
Memory CL

3.What are rotate instructions?

Those groups of instructions are used to rotate left or right(bit
wise) the contents of the processor resistor or memory location
.In all these instruction one’s ‘count’ operands is used count
may be immediate value if only one bit to rotate and can be
specified in the CL register if multiples rotate is required
.Maximum possible value of count is 31.

1.ROL(Rotate left bytes or word):

Syntax:
ROL Destination,count
Purpose:
The left rotate instruction shifts all bits in the register or
memory operand specified. The most significant bit is rotated
to the carry flag, the carry flag is rotated to the least significant
bit position, all other bits are shifted to the left. The result does
not include the original value of the carry flag.

Carry flags Destination

Example:

2.ROR(Rotate Right Bytes or word):

Syntax:
ROR Destinaion,count
 Purpose:
This instruction has opposite effect of ROL,with bits moving to
right withine the destination operands . the bit that rotate out
of LSB goes into carry flag and also into the MSB.

Destination carry flags

Example:

4.What are Flag Instructions?

The 8088 microprocessor has a set of flags that either
monitors the state of executing instructions or controls options
available in its operation.

Mnemonic Meaning Operation Flags Affected

LAHF Load AH from flags (AH)(Flags) None
SAHF Store AH into flags (Flags)(AH) SF,ZF,AF,PF,CF
Clear Carry Flag
CLC (CF)0 CF
Set Carry Flag
STC Complement carry (CF)1 CF
CMC flag (CF)(CF) CF
CLI Clear Interupt Flag (IF)0 IF
STI Set Interupt FLag (IF)1 IF

LAHF and SAHF can be used either to read the flags or to

change them. Data Transfer takes place is always between the
AH register and the Flag Register.
5.What are Compare Instructions?

CMP(compare Byte or Word):

COMPARE is an important instruction widely used in 8085

microprocessor. The 8085 instruction set has two types of
Compare operations: Compare with accumulator (CMP) and
Compare immediate with accumulator (CPI).
Syntax:
CMP Destination ,source
Purpose:
The various characteristics of the Compare (CMP) instruction
are as follows: - The CMP instruction can be used to compare
two 8-bit or two 16-bit numbers.
Carry:if Destination <Source ,this bit will be set; otherwise it
will be clear.
That allowed the operand shown in fig.
Destination Source

Register Register
Register Memory
Memory Register
Register Immediate
Memory Immediate
Accumlater Immediate
Example:

6.What are control flow and the Jump Instructions?

Jump Instructions are used for changing the flow of execution

of instructions in the processor. If we want jump to any
instruction in between the code, then this can be achieved by
these instructions. There are two types of Jump instructions:
 1. Unconditional Jump Instructions
2. Conditional Jump Instructions

1) Unconditional Jump Instructions

These instructions are used to jump on a particular location
unconditionally, i.e. there is no need to satisfy any condition for
the jump to take place. There are three types of procedures
used for unconditional jump. They are:

i. NEAR – This procedure targets within the same code

segment. (Intra-segment)
ii. SHORT - This procedure also targets within the same code
segment, but the offset is 1 byte long. (Intra-segment)
iii. FAR - In this procedure, the target is outside the segment
and the size of the pointer is double word. (Inter-segment)

Syntax: JMP
procedure_namememory_location
Example: JMP short target

2) Conditional Jumps
In these types of instructions, the processor must check for the
particular condition. If it is true, then only the jump takes place
else the normal flow in the execution of the statements is
maintained.

The ALU operations set flags in the status word (Flag register).
The conditional jump statements tests the flag and jump is the
flag is set.
There are following types of conditional jump instructions:

i) JC : Stands for 'Jump if Carry'

It checks whether the carry flag is set or not. If yes, then jump
takes place, that is: If CF = 1, then jump.

ii) JNC : Stands for 'Jump if Not Carry'

It checks whether the carry flag is reset or not. If yes, then jump
takes place, that is: If CF = 0, then jump.

iii) JE / JZ : Stands for 'Jump if Equal' or 'Jump if Zero'

It checks whether the zero flag is set or not. If yes, then jump
takes place, that is: If ZF = 1, then jump.

iv) JNE / JNZ : Stands for 'Jump if Not Equal' or 'Jump if Not
Zero'

It checks whether the zero flag is reset or not. If yes, then jump
takes place, that is: If ZF = 0, then jump.
v) JP / JPE : Stands for 'Jump if Parity' or 'Jump if Even Parity'
It checks whether the Parity flag is set or not. If yes, then jump
takes place, that is: If PF = 1, then jump.

vi) JNP / JPO : Stands for 'Jump if Not Parity' or 'Jump if Odd
Parity'

It checks whether the Parity flag is reset or not. If yes,

then jump takes place, that is: If PF = 0, then jump.
7. Whar are Subroutine and Sub Hanlings ?
A subroutine is a collection of instruction that CALL from
one or many other different location within a program.The
lastindtruction of the subrountine tells the processor how
to RETURN(go back) and where to return.
The instruction provided to transfer control from main
program toa subrountine and return control to back
memory to the main program are called subrountine-
handling instruction.
It includeCALL and RET instruction.
8.What are the loops and loop Handling Instructions?
The 8088 microprocessor has three instructions specifcally
designed for implementing loop operations. These
instructions can be used in place of certain conditional jump
instructions and give the programmer a simpler way of
writing loop sequences.
The first instruction,loop(LOOP) works with respect to the contents of
the CX register.CX must be preloaded with a count that represents the
number of times the loop is to repeat. Whenever LOOP is executed,the
content of CX are first decremented by one and then checked to
determine if they are equal to zero. If equal to zero,the loop is
complete and the instruction following LOOP is executed
otherwise,control is returned to the instruction at the label specified in
the loop instruction.
 Macros:

Macro is a set of instructions grouped under a single unit.

It is another method for implementing modular
programming.
The process of assigning a MACRO name to the string is
called defining MACRO.
Syntax of simple micro:
<MACRO NAME>MACRO

<BODY OF MACRO>

ENDM

Calling statement of this micro:

STR1 DB ‘FIRST STRING’

STR2 DB ‘SECOND STRING’

LEA DX, STR1

PPP
LEA DX, STR2
PPP
EXAMPLE:

PPP MACRO
MOV AH,9 (display string fuction )
INT 21H (DOS CELL)
 Recursion :
A recursive procedure is one that calls itself. There are two
kind of recursion: direct and indirect. In direct recursion,
the procedure calls itself and in indirect recursion, the first
procedure calls a second procedure, which in turn calls the
first procedure.
Care has to be taken to assure that each successive call
does not destroy the
parameters and results generated by the previous call .
This means that each call must store its set of
parameters, registers and allthe temporary results.
The data stored by an application of a procedure is called a
frame.

Example:

1. Factorial
2. Non-recursive way
3. Factorial (N) = N x (N-1) x (N-2)x...x3x2x1
4. Recursive Way:
5. Factorial (N) = N x Factorial (N-1)
 UNIT-4
Subroutines & Macros
Q.1] What is stack? How stack is implemented in memory?
Explain stack related instruction.
Ans:
The Stack: Sometimes it is necessary to save the contents of a
register during execution so that it can be used for the
purposes.For this purpose microprocessor has a area of
memory where the contents of specified registers or memory
location can be saved temporary and this area of memory is
called the stack.
Implementation of stack in memory : The stack is a block of
memory that may be used for storing the contents of the CPU
registers temporarily. The stack is a block of memory locations,
which is accessed using the SP and SS registers.In other words,
it is a top-town data structure whose elements are accessed
using a pointer that is implemented using the SP and SS
registers.
As we go on storing the data words into the stack,the
pointer goes on decrementing and on the other hand,the
pointer goes on incrementing as we go on retrieving the word
data.
The process of storing the data in the stack is called “Pushing
into” the stack and the reverse process is known as “Popping
off” the stack for each such process,the stack pointer (SP) is
decremented or incremented by two.
The stack is essentially last-in-first-out (LIFO) data segment.This
means that the data,which is pushed into the stack last,will be
on top of stack and will be popped off stack first.
Stack Related Instructions:
1) PUSH(Push Word Onto Stack)
Syntax: PUSH Source
Purpose: It is often necessary to save the contents of a register
so that it can be used for other purposes.This instruction
pushes the contents of the specified register/memory location
onto the special area of memory called stack.
This special area is pointed by SS (Stack segment) register as
segment address and SP (Stack Ponter) register as offset
value,whenever data is pushed into the stack SP is
decremented by two automatically.The higher byte is pushed
first and then the lower byte,allowed operands.

Operands
Register
Seg-Reg
Memory
2]POP(Pop Data off Stack)
Syntax: POP Destination
Purpose: The POP instruction is used to perform the reserve
working of PUSH instruction. Again Sp(Stack Pointer) plays main
role. The 16-bit data from stack where SP is currently pointing
copy to the destination and SP is automatically incremented by
2.
3]PUSHF(Push 16-bit flag onto stack)
Syntax: PUSHF
Purpose: Some time it is necessary to save the contents of the
flag register during execution.Usually this is done whenever the
processor is interrupted.PUSHF instruction pushes the lower
16-bit of the flag register onto the stack and SP is decremented
by two.
4]POPF(Pop 16-bit flags off stack)
Syntax: POPF
Purpose: This instruction is reserve of PUSHF
instruction,popping 16-bits off the stack and storing them in
the flag register.The SP will incremented by 2 (POPF) after the
execution.
Q.2] Explain subroutine.What is the difference between
Subroutine and Macro?
Ans:
Subroutine: A subroutine is a special segment of program
that can be called for execution from any point in a program.
1)In computers, a subroutine is a sequence of program
instructions that perform a specific task, packaged as a unit.
This unit can then be used in programs wherever that particular
task have to be performed.
2)A subroutine is often coded so that it can be started (called)
several times and from several places during one execution of
the program, including from other subroutines, and then
branch back (return) to the next instruction after the call, once
the subroutine’s task is done. It is implemented by using Call
and Return instructions.
3)The subroutine is written to provide a function that must be
performed at various points in the main program.Instead of
including this piece of code in the main program each time the
function needed, it is put into the program just once as a
subroutine. An assembly language subroutine is also reffered to
as a procedure.
4)The instructions provided to transfer control from the main
program to a subroutine and return control back to the main
program are called subroutine-handling instructions.
The different types of subroutine instructions are:
• CALL and RET Instructions: There are two basic instructions
in the instruction set of 8086 for subroutine handling: the
call(CALL) and return (RET) instructions together they
provide the mechanism for calling a subroutine into
operation and returning control back to the main program
at its completion .
1) Just like the JMP instruction,CALL allows implementation
of two types of operations: the intrasegment call and the
intersegment call.
2)Every subroutine must end by executing an instruction that
returns control to the main program.This is the return (RET)
instruction.
Difference Between Subroutine and Macro:
Subroutine Macro
Subroutine are called by CALL In case of macro the
instruction and control is complete code of instruction
transfer to subroutine where is inserted at each place
it is called. where the macro.
Subroutine is called the Macro does not utilize the
return address i.e. CS:IP is surface of the stack.
pushed into the stack.
The executable code in the The executable cod ein the
case of subroutine is not case of macro becomes
lengthy as compared to lengthy as compare to
macro. subroutine.
Subroutine requires more Macro requires less time for
time for execution as execution as compared to
compared to macro. subroutine.
The program using The program using macro
subroutine requires less requires more memory space
memory space for execution for execution.
as compare to macro.
Q.3] What is macro? Explain nested macro with example.
Ans:
Macro: A macro is a group of instructions that perform one
task,just as a procedure performs a task.The difference is that a
procedure is accessed via a CALL instruction,while a macro is
inserted in the program at the point of usage as a new
sequence of instructions.Creating a macro is very similar to
creating a new opcode that can be used in the program.Macro
sequencences execute faster than procedures because there is
no CALL and RET instructions to execute.The macro instructions
are placed in your program by the assembler at the point where
they are invoked.
The code that is to be repeated is called the prototype
code,and the prototype code along with the statements for
referencing and terminating it is called the macro definition.
Included in the first statement of a macro definition is the
macro’s name.The propcedure for using a macro is to give
macro definition and then cause the macro to be inserted at
various points within a program by placing a statement that
includes the macro’s name at these points.These statements
are known as macro calls.When a macro call is encountered by
the assembler,the assembler replaces the call with the macro’s
code.This replacement action is reffered to as macro expansion.
Nested Macro: It is possible for a macro call to appear within a
macro definition.This is referred to as macro nesting and has
the limitation that all macros included in the definition of a
given macro must be defined before the given macro is called.
Example:
Write a program to compute (diff1-diff2)2.
Solution: DIF MACROVAR1,VAR2
MOV AX,VAR1
SUBAX,VAR2
ENDM
The first macro finds the difference.
:The second macro calls the first and computes the difference
square.

DIFSQRMACRO OPR1, OPR2,RESULT

PUSH DX
PUSH AX
DIF OPR1,OPR2
IMUL AX
MOV RESULT,AX
 POP AX
POP DX
ENDM
; The main program starts which calls the nested macro.
:
DIFSQR VAR1, VAR2,RES
:
Q.4]Write a procedure named SQUARE that squares the
content of BL and places the result in BX.Assume that this
procedure is called from the main program ,which is located in
the same code segment.(7m)
Solution:
SQUARE PROC NEAR
PUSH AX
;save the register to be used
Mov AL, BL
;Place the number in AL
IMUL BL ;Multiply with itself
MOV BX, AX ;Save the result
POP AX ;Restore the register used
RET ;Restore from procedure
SQUARE ENDP
Q.5] Write a procedure named CUBE that cubes the contents
of BL and place the result in BX. Asssume that this procedure
is called from the main program which is located in the same
code segment.
Solution:
CUBE PROC NEAR
PUSH AX
MOV AL,BL
IMUL BL
IMUL BL
MOV BX,AX
POP AX
RET
CUBE ENDP
Q.6] Describe the concept of recursion at assembly language
programming level.
OR Explain recursion with example (7or 8m).
ANS: Sometimes an algorithm is defined in terms of itself .That
is, the algorithm is nested within itself in such a way that its
computational procedure calls upon itself. Such algorithms are
said to be recursive.Recursive algorithms may be implemented
by having a procedure call itself,but care must be taken to
assure that each successive call does not destroy the
parameters and results generated by the previous call and to
make sure that the procedure does not modify itself.This
means that each call must store its set of
parameters,registers,and all temporary results in a different
place in memory.To guarantee that separate areas of memory
are used a stack is normally employed.By pushing the data onto
the stack as shown in fig.

Frame for Temporary result

Second call Save area for registers
Parameter Addresses
Frame for Temporary result
first call Save area for registers
parameter Addresses
 It can be conveniently retrieved in reverse order as
the process emerges from its nesting .The data stored by an
application of the procedure is called a frame,and the 8086’s BP
register can be used to permit ready access to the individual
terms within a frame.Normally, a frame contains the saved
register contents ,the parameter addresses,and a temporary
storage area. Properly storing the information on the stack
provides for an orderly exit. To prevent indefinite nesting of a
recursive algorithm,clearly the algorithm must include a
conditional branch that will eventually allow the nest to be
exited.
A trivial example of a recursive procedure is one for evaluating
factorials.Computing a factorial can be done using a recursive
procedure FACT as follows:
BEGIN FACT(N, RESULT)
SAVE registers on stack
IF N = 0 THEN
RESULT = 1
ELSE
PUSH address of RESULT onto stack
PUSH N-1 onto stack
CALL FACT (N-1, RESULT)
RESULT = N * RESULT
 ENDIF
RESTORE registers from stack
DELETE parameters from stack
RETURN

The parameters N and RESULT represent the factorial to be

found and the result,respectively.
Q.7] Write a program to exchange the ccontents of AX register
with BX register without using MOV and XCHG instruction.
Solution:
SUB CX, CX ;To clear the CX register
OR CX, AX ;Copy contents of AX into CX
SUB AX, AX ;To clear AX register
OR AX, BX ; Copy contents of BX into AX
SUB BX, BX ;To clear BX register
OR BX, CX ; Copy contents of CX into BX
Q.8]Explain the operation of input/output instructions of
8086.
OR
Explain in detail the input-output instructions of 8086.
Ans: Input/output operations are performed by the 8086
microprocessor that employ isolated I/O using special input and
output instructions together with the I/O port addressing
modes.
These instructions,in(IN) and out(OUT),are listed in the table:
Mnemonics Meaning Format Operation
Input direct IN Acc,Port *Acc←Port
IN
Input indirect IN Acc, DX Acc←[DX]

Output direct OUT Port, Port←Acc

OUT Acc

Output OUT DX, [DX] ←Acc

indirect Acc
*Acc=AL OR AX
(Input/Output instructions)
Their mnemonics and formats are provided together with a
brief description of their operations. Note that there are two
different forms of IN and OUT instructions: the direct I/O
instructions and variable I/O instructions.Either of these two
types of in structions can be used to transfer a byte or word of
data.All data transfers take place between an I/O devices and
the MPU’s accumulator register. For this reason ,this method of
performing I/O is known as accumulator I/O. Byte transfers
involve the AL register, and word transfers the AX register in
fact, specifying AL as the source or destination register in an I/O
instruction indicatses that it corresponds to a byte transfer.That
is byte-wide or word-word input/output is selected by
specifying the accumulator (Acc) in the instruction as AL or AX,
respectively.
In a direct I/O instruction, the address of the I/O port is
specified as part of the instruction.Eight bits are provided for
this direct address. For this reason, its value is limited to the
address range from 00H to FFH(first 256+ ports). This range is
referred to as page 0 in the I/O address space.
1. IN (Input Byte or Word from Port)
Syntax: IN Accumulator,Port
Purpose: Processor has a separate I/O space from its memory
space, among them 65536 (0 to 65535) I/O ports are available
for the programmer to use.These ports can be access directly
,using the port address,for 65536 port address range is 0000H
to FFFFH. The input port is actually a hardware device
connected to the processor’s data bus.Using IN instruction we
can access port.The 8086 allows two different forms of the IN
instruction.
A full 16-bit port address must be loaded into DX register and
instructions like IN AL,DX or IN AX,DX may be used to read the
input port.If the port number is in between 00H to FFH then
another form of IN instruction may be used as IN AL,86H or IN
AX,80H.
Example: If we want to read input port 80H then we may give
instruction like
IN AL, 80H or MOV DX,80H
IN AL,DX
2.OUT(Output Byte or Word to Port)
Syntax: OUT PAort,Accumulator
Purpose: This instruction is reserve instruction of IN instruction.
With OUT we can send 8-bit or 126-bit data to an output port.
The port address may be loaded into DX (ifv more than 8-bit
address) for us ewith OUT DX,AL or OUT DX,AX or specified
within the instruction, as OUT 80H,AL or OUT, 80H,AX.
Example: OUT DX,AL if DX= 2000H and AL=3EH then port
address stored in DX register is output on the address
bus,along w2ith 3E from AL on the data bus,and 8-bit data -----
-from AL on the data bus,and 8-bit data from AL will store to
2000H port address.
 Q.9] Write a sequence of instructions that inputs the byte
of data from input ports at I/O addresses A00016 and
B00016 adds these values together,and saves the sum in
memory location IO_SUM.
Solution:

MOV DX, A000H ; Set port address

IN AL, Dx ;receive data from port
MOV BL, AL ;Copy in BL
MOV DX, B000H ;Set port address
IN AL, DX ;receive data from port
ADD AL, BL ; add data
MOV [IO_SUM], AL ; store result
Q.10] Explain the I/O address space of 8086.
Ans: The 8086 has separate memory and input/output
address space .The I/O address space is the place where I/O
interfaces, such as pointer and monitor port,are
implemented.The I/O address range is from 0000H to
FFFFH.This is 65536 bytes or 64KB
addresses;therefore,unlike memory,I/O addresses are only
16 bits long.Each of these addresses corresponds to one
byte or port.The part of the map from address 0000H
through 00fh is referred to as page 0.Certain of the 8086’s
I/O instructions can perform only input or output data-
transfer operation to I/O devices located in this part of the
I/O address space .Other I/O instructions can input or
output data for devices located anywhere in the I/O address
space.I/O data transfers can be byte wide or word
wide.Notice that the eight locations from address 00f8h
through 00ffh are specified as reserved by microprocessor
and should not be used.
 Unit 5. 8086 Interrupt
1) Explain how enter a processing mechanism of 8086 works.explain interrupt
types?

Interrupt mechanism:-

-The dictionary meaning of the word interrupt is to break the sequence of operation.
While the CPU is executing the program, an interrupt breaks the normal sequence
of execution of instructions diverts its execution to some other program called
interrupt service routine(ISR). After executive ISR, the control is transferred back
to main program which was being executed at the time of interruption.

-Interrupt is the method of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor. The microprocessor
responds to that interrupt with an ISR (Interrupt Service Routine), which is a short
program to instruct the microprocessor on how to handle the interrupt.

The following image shows the types of interrupts we have in a 8086

microprocessor −

Hardware Interrupts

-Hardware interrupt is caused by any peripheral device by sending a signal through

a specified pin to the microprocessor.

-The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-
maskable interrupt and INTR is a maskable interrupt having lower priority. One
more interrupt pin associated is INTA called interrupt acknowledge.

NMI
-It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt.The NMI is open
used for parity errors and other major system for such as power failure.

INTR

-The INTR is a maskable interrupt because the microprocessor will be interrupted

only if interrupts are enabled using set interrupt flag instruction. It should not be
enabled using clear interrupt Flag instruction i.e INTR can be masked.

Software Interrupts

-Software interrupts are generated by some instruction used in program. Basically

software interrupt is generated by INT instruction. Software interrupts are basically
used for to allow the user to read the keyboard, write text to screen, control disk
drive, control printer, control speaker and so forth. Some other software interrupts
are INTO etc.

INT

- Interrupt instruction with type number.It is 2-byte instruction. First byte provides
the op-code and the second byte provides the interrupt type number. There are 256
interrupt are available.

2)Explain priority of interrupt with example?

Interrupts priority

-hardware, software, and internal interrupts are serviced on a priority basis. Priority
is achieved into ways. First, the interrupt processing sequence implemented in the
8086 tests for the occurrence of the various groups based on the hierarchy shown
in table.Thus, we see that internal interrupts are the highest-priority group, and
external hardware interrupts are the lowest- priority group. Second, each of the
interrupts is given a different priority level by assigning it a type number. Type 0
identify the highest priority interrupt, and type 225 identifies the lowest- priority
interrupt.
 Interrupt Priority

Reset Highest

Internal interrupts

Software interrupts

NMI

External hardware interrupts Lowest

-Actually,a few of the type numbers are not available for use with software or
hardware interrupts. This is because they are reserved for special interrupt function
of the 8086, such as internal interrupts. For instance, within the internal interrupt
group, the interrupt known as divide error is a sign to type number 0. therefore it
has the highest priority of the internal interrupts. Another internal interrupt called
overflow is a signed the type number 4. Overflow is the lowest priority internal
interrupt.

-The importance of interrupt lies in the fact that, even interrupt-service routine has
been initiated to perform a function a sign to a specific priority level, only devices
with higher priority are allowed to interrupt the active service routine. Lower
priority devices will have to wait until the current routine is completed before their
request for service can be acknowledged. For hardware interrupts this priority
scheme is implemented in external hardware. For this reason, the user normally
assigns task that must not be interrupted frequently to higher-priority levels and
those that can be interrupted a lower-priority levels.

-A More common occurrence of multiple interrupt is seen when the processor's

trap flag is set. The trap flag, when set, puts the processor into single-step mode,
where a type-1 interrupt is generated after completion of every instruction. If the
current instruction is INT or INTO, you can see that two interrupts will need
servicing: INT or INTO interrupt and single-step interrupt. Single- step has the
lowest priority of all interrupts and those gets recognized last.
3)Explain in detail the interrupt vector table(IVT) of 8086?

Interrupt Vector Table

Following figure shows the organization of IVT and associated vector assignment.

-All types of interrupts whether hardware or software generated points to the single
entry in the processor interrupt vector table. The interrupt vector table is located in
the first 1024 bytes of the memory and address 00000H to 003FFH. It contains 256
different 4 byte interrupt vectors.

-An interrupt vector contains the address of the interrupt service routines(ISR) of
that interrupt. These table is a collection of 4 byte addresses that indicates where
the processor should jump to execute the associated interrupt service routine.
Because 256 types of inter types supported in real mode the IVT is 1024 bytes its
long.This 1KB memory block is reserved for the table is located in the address
range 00000H to 003FFH.
4)Explain operation of interrupt instructions?

1. CLI(Clear Interrupt Flag):-

-This instruction clears the interrupt flag.

2. STI(Set Interrupt Flag):-

-Instruction sets the interrupt flag.

3.WAIT (Wait for test signal or interrupt signal):-

-When this instruction executes the 8086 enters and idol condition in which it is
doing no processing.The 8086 will stay in this idle state until the 8086TEST input
pin is made low or until an interrupt signal is received on the INTR or the NMl
interrupt input pins. If a valid interrupt occurs while the 8086 is in this idle state
the 8086 will return to the idle state after the interrupt service procedure executes.
It returns to the idle state because the address of the WAIT instruction is the
address pushed on the stack when the 8086 respond to the interrupt request. WAIT
effects no flags. The WAIT instruction is used to synchronize the 8086 with
external hardware such as the 8087 maths cooperation.

4. HLT (Halt until Interrupt or Reset):-

-The HLT instruction will cause the 8086 to stop fetching and executing
instruction. The 8086 will enter a halt state. The only ways to get the processor out
of the heart state are with an interrupt signal on the INTR pin, an interrupt signal
on the NMI pin, or a reset signal on the RESET input.

5. INT n:-

-The INT n instruction calls the interrupt service routine that begins at the address
represented in vector number n. for example an INT 80H

So 00200H call the interrupt service routine whose address is store in vector type
number 00200H-00203H.
6. INTO (Interrupt Overflow):-

-The INTO instruction checks the overflow flag. If 0F = 1, the INTO instruction
cause the procedure whose address is stored in IVT in vector type-4. If 0F = 0 the
INTO instruction performs no operation and the next sequential instruction in the
program executed.

7. IRET (Interrupt Return):-

-The IRET instruction is a special return instruction used to return for both
software and hardware interrupts. The IRET instruction is much like a normal FAR
RET, because it retrieves the address from the stack. An IRET instruction removes
six bytes from the stack: two for IP, two for the CS, and two for the flags.

5) Draw and explain the external hardware interrupt interface signals in minimum
mode interrupt interface?

Minimum- Mode Interrupt Interface

The interrupt interface for 8086 system is shown in below figure.

Fig. Minimum mode 8086 system external hardware interrupt interface

-Here we see that it includes the multiplexed address/data bus and dedicated
interrupt signal lines INTR and INTA. We also see that external circuitry is
required to interface the interrupt inputs, INT32 through INT 255, to the 8086's
interrupt interface.This interface circuitry must identify which of the pending
activity interrupts has the highest priority and then pass its type number to the
microprocessor.

-In this circuit we see that the key interrupt interface signals are the interrupt
request and interrupt acknowledgement. The input at the INTR line signals the
8086 that and external device is requesting service. The 8086 samples this input
during the last clock period of each instruction execution cycle. Logic 1 represents
and active interrupt request.INTR is level triggered therefore eats active 1level
must be maintained until tested by the 8086.

-If it is not maintain the request for service may not be recognized moreover the
logic 1 at I NTR must be removed before the service router runs to completion
otherwise the same inter of make it acknowledged a second time.

-When an interrupt request has been recognized by the 8086 its signals this fact to
external circuitry. It does this with false to logic 0 at its interrupt acknowledgement
output. Actually there are two pulses produced at interrupt acknowledgement
during the interrupt acknowledgement bus cycle. The first poles signals external
circuitry that the interrupt request has been acknowledged and to prepare to send
its type number to the 8086. The second poles tales the external circuitry to put the
type number on the data bus.

-The lower eight lines of the address/data bus AD0 through AD7, are also part of
the interrupt interface.During the second cycle in the interrupt acknowledged bus
cycle, external circuitry must put an 8-bit type number on bus lines AD0 through
AD7. The 8086 reads this number off the Boss 2 identify which external device is
requesting service. It uses the type number to generate the address of the interrupts
vector in the pointer table and to read the new values of CS and IP into the
corresponding internal registers. CS and IP values from the interrupt vector table
are transferred to the 8086 over the data bus. Before loading CS and IP with new
value, their old values and the values of the internal flags are automatically pushed
to the stack part of memory.
6)Draw and explain the external hardware interrupt interface signals in minimum
mod interrupt interface.

-Figure shows the maximum mod interrupt interface of the 8086 microprocessor.
The primary difference between this interrupt interface and that for the minimum
mode is that the 8288 bus bus controller has been added.In the minimum more
system it is the bus controller that produces the interrupt acknowledgement and
ALE signals. Whenever the 8086 outputs and interrupt acknowledgement bus
status code the 8288 generates pulses at it's interrupt acknowledgement output to
signal external circuitry that the 8086 has acknowledged an interrupt request.

Fig.Maximum mode 8086 system external hardware interrupt interface

-Second change in figure is that 8086 provides a new signal for the interrupt
interface. These output labeled block is called the bus priority LOCK signal.
LOCK is applied as an input to a bus arbiter. In response to this signal the
arbitration logic insurance that no other device can take over control of the system
bus until the interrupt acknowledge the cycle is complete.

8) Explain with the help of a flowchart interrupt processing sequence of the 8086
microprocessor?

-Whenever interrupt is encounter processor follow some steps to process the

interrupt. That interrupt processing sequence can be classified into following steps.

1. Get vector number: first step is to obtain interrupt number there are three
possible ways for getting this number are:
  The interrupt number maybe specified directly one of the INT instruction,
like INT 21H gives the interrupt number 21H.
 The processor may automatically generated the number, as it does for INTO,
NMI, and divided error.
 It may have to read the interrupt number from the databus, after receiving
INTR.

Once the interrupt number is obtained this number is used to locate a location in
the IVT by multiplying the number with 4. then IVT gives address of ISR.

2. Save Processor Information: Once the interrupt vector is known processor

perform some steps to save current information.

 Processor pushes the flag register contains on to the stack.

 Processor clears the IF and TF this is important for nested interrupt. If
another interrupt encounters while processing first then these flags will set
again.
 Processor the contents of CS register and IP register. This is a return address.
After interve processing control will return to the address.

3.Fetch new instruction pointer: what's the return address has been used
processor can fetch the new value of IP and CS out of the IVT and begin execution
of the ISR.
 Fig. Flowchart

4. Return from ISR: Once interrupt service is over, the last instruction of the ISR
which is IRET, return the pointer to main program. IRET is similar of RET
instruction of procedure. RET instruction POPs return address out of stack, while
IRET instruction POPs return address as well as flag contents too. As RET is the
last Statement of the procedure similar IRET is the last Statement of the ISR.
9) Explain internal interrupt functions of 8086?

Internal Interrupt Functions

1. Divide-Error(Type-0 or INT 0)

Whenever in division instructions denominators become zero this interrupt

generates.for example

Mov BL,0
DIV BL
These two lines code will generate type-0 interrupt.Processor will found ISR
address from IVT and after execution of ISR control will transfer to the next
instruction.

2. Single-Step (type-1 or INT-1)

This interrupt relies on the setting of the trace flag in the flag register. When the
trace flag is said the 8086 will generate a type 1 interrupt after each instruction
executes. This single step debugger maybe perform to display the contents of each
processor register, the state of the flag, and other useful information after execution
of each instruction in the user program. Assume that the trace flag is set and trace
ISR are display the contents of AX register then following code will display the
contents of AX register after each step.

Mov AX, 1234H ; Display the contents of the AX=1234H

INC AL ; Display the contents of AX=1235H

DEC AH ; Display the contents of AX= 1135H

NOT AX ; Display the contents of AX=EECAH

Whenever this interrupt encounters processor generate a type-1 interrupt and

address of single step ISR is found from the address is stored in memory locations
00004H through 00007H.
3. NMI (type-2 or INT-2)

-The non maskable interrupt is another interrupt that is initiated from external
hardware. However it differs from the other external hardware interrupts in several
ways. First as its name implies it cannot be masked out with the interrupt flag.
Second request for service by this interrupt are signaled to the 8086
microprocessor by applying logic 1at the NMI input, not the INTR input. Third,
the NMI input is positive edge triggered. Therefore, a request for service is
automatically latched internal to the MPU.

-Because NMI can never be ignored by the processor, it finds useful application.
One of them data saving on power fails. We know processor unfortunately forgets
the contents of its registers and flags when power is turned off and thus has no
chance of getting back to the correct place in a program if its power is interrupted.
One way to prevent these from happening and provide a way for the processor to
resume execution is to use NMI to interrupt at the beginning of power failure.
Because computers power supply will continue to supply a stable voltage for a few
microseconds after it loses AC, the processor has plenty of time to execute the
necessary instructions. Suppose that a certain system contains a small amount of
non volatile memory. So in the event of power fail the NMI ISR should store the
content of each processor register in the NVM. These values can then be reloaded
when power comes backup.In this fashion we can recover from a power fail
without loose of intelligence.

-Whenever this interrupt occurs processor generate type 2 interrupt and fetches the
ISR address from the memory location 00008H through 0000BH.

4.Breakpoint (type-3 or INT-3)

These interrupt is used for debugging purpose in the programming. The working of
these interrupt is as follows. A program being debugged will have the first byte of
one of its instructions replaced by the code for breakpoint.

When the processor gets to this instruction it will generate a type 3 interrupt.The
ISR associated with break point is similar to the trace ISR and should be capable of
displaying the contents of processor register and also the address at which the
breakpoint byte with the original first byte of the instruction.
When ever this interrupt occurs processor generated type-3 interrupt and fetches
the ISR address from the memory location 0000CH through 0000FH.

5. Overflow (type-4 or INT-4)

This type-4 interrupt is initiated only when the INTO instruction is executed with
the overflow flag is set.If the overflow flag is cleared, INTO will not generate an
interrupt.

For example:

Mov AL, 70H

Mov BL, 60H

ADD AL, BL

INTO

These series of instructions will generate an overflow interrupt.when ever this

interrupt occurs processor generates type-4 interrupt and fetches the ISR address
from the memory location 00010H through 00013H.
10) Differentiate between Procedure call and ISR call?

Procedure call ISR call

Procedure is called by CALL statement ISR may be called by interrupt type or it

may be hardware generated.

In procedure call only return address is ISR call processor is always called
pushed into the stack,this address may directly while ISR is always called
be one word long. indirectly through IVT

Procedure is always called directly ISR is always called indirectly through

IVT

Last statement of procedure is RET Last statement of ISR is IRET

11) What are the different ways interrupts are generated?

-There are two types of interrupts: software interrupts and hardware interrupts.
Software interrupts are generated by the software instructions like INT and
interrupt number.

For example: INT 21H will generate interrupt of type 21H. INTO will generate
overflow interrupt. BOUND generates a type-5 interrupt. Hardware interrupts are
generated by hardware pins. As NMI and INTR pins are available to generate these
interrupts. One extra pin INTA gives interrupt acknowledgement.

12)What is the IVT address for the INT 21H?

-As 21 hexadecimal is equivalent to 33 decimal so multiply this number by 4.

33 * 4 = 132 decimal =(84)16, so the IP address will be stored at address 00084H

and 00085H and CS value will be store at 00086H and 00087H memory location.
Initial IVT address will be 00084H.
13) Write an interrupt service routine that will multiply the contents of AX by 7.If
the new value of AX is greater than 8400H, call the far routine OVERSAN. Note
OVERSCAN destroys AX, BX, and DI.

Solution:-

PUSH BX

PUSH DI

Mov BL,7

IMUL BL

CMP AX, 8400H

JLE EXIT

PUSH AX

CALL FAR PTR OVERSCAN

POP AX

EXIT: POP DI

POP BX

IRET

14) Show the map of IVT, Stack if an instruction INT 21H is executed, assuming
that following values: SS=1000H, SP=0200H, CS= 2000H, IP=1234H.
Flags=3456H; address of ISR 21 IS 3000H:5678H.

Solution:- To map IVT and Stack we have to calculate some addresses.

1.Stack top address SS * 10 + SP = 10000H + 0200H = 10200H.

2.IVT address for INT 21H is 00084H and 00085H for IP and 00086H and 00087H
for CS.

Now follow interrupt processing sequence.

1.Process encounters INT 21H interrupt.

2.Processor pushes the contents of flag register onto the stack.

3.Processor pushes the contents return address CS:IP onto the stack.

4.Processor fetches the new address of ISR from IVT.

The whole sequence is shown in below figure:

UNIT VI- INTERNET OF THINGS(IOT)

Definition:=>(INTERNET OF THINGS)
• The term IoT (Internet of Things) was coined by Kevin Ashton in 1999. It is referred to as
a network comprised of interconnected physical objects (referred to as "things")
worldwide that are capable of collecting and exchanging data without human
interaction.

• These devices contain embedded systems (software, electronics, networks, and sensors)
that are able to collect data about the surrounding environment, transmit data over a
network, respond to remote commands, or take actions based on data collected.

• There are many IoT devices or things available today, including wearables, implants,
vehicles, machinery, smartphones, appliances, computing systems, or any other item that
can send and receive data.
• Cloud-based storage and computing, Cyber-Physical Systems, and big data networks
can all be integrated with IoT. The IoT primarily focuses on expanding internet
connectivity from standard devices (such as computers, mobile phones, or tablets) to
relatively dumb ones like toasters.
• It turns old "dumb" devices into "smart" ones by making them able to transmit data over
the internet, facilitating communication with people and other IoT-enabled devices.

i.e. Diagram of Internet of Things.

What are Characteristics of IOT?
:=>
Characteristics of IOT:-
The no-need-to-know in terms of the underlying details of infrastructure, applications interface
with the infrastructure via the APIs. The flexibility and elasticity allows these systems to scale
up and down at will utilizing the resources of all kinds CPU, storage, server capacity, load
balancing, and databases The “pay as much as used and needed” type of utility computing and
the always on, anywhere and any place” type of network-based computing. The fundamental
characteristics of the IoT are as follows:

• Interconnectivity: With regard to the IoT, anything can be interconnected with the
global information and communication infrastructure.

• Things-related services: The IoT is capable of providing thing-related services within

the constraints of things, such as privacy protection and semantic consistency between
physical things and their associated virtual things. In order to provide thing-related
services within the constraints of things, both the technologies in physical world and
information world will change.

• Heterogeneity: The devices in the IoT are heterogeneous as based on different

hardware platforms and networks. They can interact with other devices or service
platforms through different networks.

• Dynamic changes: The state of devices change dynamically, e.g., sleeping and waking
up, connected and/or disconnected as well as the context of devices including location
and speed. Moreover, the number of devices can change dynamically.

• Enormous scale: The number of devices that need to be managed and that
communicate with each other will be at least an order of magnitude larger than the
devices connected to the current Internet. Even more critical will be the management
of the data generated and their interpretation for application purposes. This relates to
semantics of data, as well as efficient data handling.

• Safety: As we gain benefits from the IoT, we must not forget about safety. As both the
creators and recipients of the IoT, we must design for safety. This includes the safety of
our personal data and the safety of our physical well-being. Securing the endpoints, the
networks, and the data moving across all of it means creating a security paradigm that
will scale.

• Connectivity: Connectivity enables network accessibility and compatibility.

Accessibility is getting on a network while compatibility provides the common ability to
consume and produce data.
What are the views of IOT Architectural?
:=> IOT architectural view:- IoT architecture consists of different layers of
technologies supporting IoT. It serves to illustrate how various technologies relate
to each other and to communicate the scalability, modularity and configuration of
IoT deployments in different scenarios. The functionality of each layer is described
below:
• Smart device / sensor layer: The lowest layer is made up of smart objects integrated
with sensors. The sensors enable the interconnection of the physical and digital worlds
allowing real-time information to be collected and processed. There are various types
of sensors for different purposes. The sensors have the capacity to take measurements
such as temperature, air quality, speed, humidity, pressure, flow, movement and
electricity etc. In some cases, they may also have a degree of memory, enabling them
to record a certain number of measurements. A sensor can measure the physical
property and convert it into signal that can be understood by an instrument. Sensors
are grouped according to their unique purpose such as environmental sensors, body
sensors, home appliance sensors and vehicle telemetric sensors, etc.
• Gateways and Networks-Massive volume of data will be produced by these tiny
sensors and this requires a robust and high performance wired or wireless network
infrastructure as a transport medium. Current networks, often tied with very different
protocols, have been used to support machine-to-machine (M2M) networks and their
applications. With demand needed to serve a wider range of IoT services and
applications such as high speed transactional services, context- aware applications, etc,
multiple networks with various technologies and access protocols are needed to work
with each other in a heterogeneous configuration. These networks can be in the form
of a private, public or hybrid models and are built to support the communication
requirements for latency, bandwidth or security. Various gateways (microcontroller,
microprocessor) & gateway networks (WI-FI, GSM, GPRS).
• Management Service Layer-The management service renders the processing of
information possible through analytics, security controls, process modeling and
management of devices. One of the important features of the management service
layer is the business and process rule engines. IoT brings connection and interaction of
objects and systems together providing information in the form of events or contextual
data such as temperature of goods, current location and traffic data. Some of these
events require filtering or routing to post-processing systems such as capturing of
periodic sensory data, while others require response to the immediate situations such
as reacting to emergencies on patient’s health conditions. The rule engines support the
formulation of decision logics and trigger interactive and automated processes to
enable a more responsive IoT system.
• Application Layer-The IoT application covers “smart” environments/spaces in domains
such as: Transportation, Building, City, Lifestyle, Retail, Agriculture, Factory, Supply
chain, Emergency, Healthcare, User interaction, Culture and tourism, Environment
and Energy.
 What are conceptual view of IOT?
IOT conceptual view-
• The main tasks of this framework are to analyze and determine the smart activities of
these intelligent devices through maintaining a dynamic interconnection among those
devices. The proposed framework will help to standardize IoT infrastructure so that it
can receive e-services based on context information leaving the current infrastructure
unchanged. The active collaboration of these heterogeneous devices and protocols can
lead to future ambient computing where the maximum utilization of cloud computing
will be ensured.
• This model is capable of logical division of physical devices placement, creation of
virtual links among different domains, networks and collaborate among multiple
application without any central coordination system. IaaS can afford standard
functionalities to accommodate and provides access to cloud infrastructure. The
service is generally offered by modern data centers maintained by giant companies and
organization. It is categorized as virtualization of resources which permits a user to
install and run application over virtualization layer and allows the system to be
distributed, configurable and scalable.
• Total infrastructure system can be categorized into 4 layers to receive context
supported e-services out of raw data from the Internet of Things. These 4 layers
establish a generic framework that does not alter the current network infrastructure
but create an interfacing among services and entities through network virtualization.

1. Connectivity Layer-
This layer includes all the physical devices involved in the framework and the
interconnection among them. Future internet largely depends on the unification of these
common objects found everywhere near us and these should be distinctly identifiable and
controllable.
This layer also involves assigning of low range networking devices like sensors, actuators,
RFID tags etc and resource management checks the availability of physical resources of all
the devices and networks involved in the underlying infrastructure. These devices contain
very limited resources and resource management ensures the maximum utilization with
little overhead. It also allows sharing and distribution of information among multiple
networks or single network divided into multiple domains.

2. Access Layer-
• Context Data will be reached to internet via IoT Gateway as captured by short range
devices in form of raw data. Access layer comprises topology definition, network
initiation, creation of domains etc. This layer also includes connection setup, intra-inter
domain communication, scheduling, packet transmissions between flow-sensors and
IoT gateway. The simulation was run later in this paper for different scenario based on
 this layer. Feature management contains a feature filter which accepts only acceptable
context data and redundant data are rejected. Large number of sensor maintains lots
of features but only a small subset of features is useful generate a context data.
• Feature filter helps to reduce irrelevant data transmission, increases the data transfer
rate of useful data and reduce energy and CPU consumption too. Number of features
can be different based on the application requirements and context data types.

3. Abstraction Layer-
• One of the most important characteristics of OpenFlow is to add virtual layers with the
preset layers, leaving the established infrastructure unchanged. A virtual link can be
created among different networks and a common platform can be developed for
various communication systems. The system is fully a centralized system from physical
layer viewpoint but a distribution of service (flow visor could be utilized) could be
maintained. One central system can monitor, control all sorts of traffics. It can help to
achieve better band-width, reliability, robust routing, etc. which will lead to a better
Quality of Services (QoS).
• In a multi-hopping scenario packets are transferred via some adjacent nodes. So, nodes
near to access points bears too much load in comparison to distant nodes in a
downstream scenario and inactivity of these important nodes may cause the network
to be collapsed. Virtual presence of sensor nodes can solve the problem where we can
create a virtual link between two sensor networks through access point negotiation.
So, we can design a three a three layer platform, where common platform and
virtualization layer are newly added with established infrastructure. Sensors need not
to be worried about reach-ability or their placement even in harsh areas. Packet could
be sent to any nodes even if it is sited on different networks.

4. Service Layer-
• Storage management bears the idea about all sorts of unfamiliar and/or important
technologies and information which can turn the system scalable and efficient. It is not
only responsible for storing data but also to provide security along with it. It also allows
accessing data effectively; integrating data to enhance service intelligence, analysis
based on the services required and most importantly increases the storage efficiency.
Storage and management layer involves data storage & system supervision, software
services and business management & operations. Though they are included in one
layer, the business support system resides slightly above of cloud computing service
whereas Open-Flow is placed below of it as presented to include virtualizations and
monitor management.

• Service management combines the required services with organizational solutions and
thusnewgeneration user service becomes simplified. These forthcoming services are nec
essitated to be co-interrelated and combined in order to meet the demand socio- economic
factors such as environment analysis, safety measurement, climate management,
agriculture modernization etc.
What are logical Design ?
:=> Logical design of IOT-
1. Plug and Play Integration
• If we look at IoT-related technology available today, there is a huge heterogeneity. It
is typically deployed for very specific purposes and the configure requires significant
technical knowledge and may be cumbersome. To achieve a true Internet of Things we
need to move away from such small- scale, vertical application silos, towards a
horizontal infrastructure on which a variety of applications can run simultaneously. This
is only possible if connecting a thing to the Internet of Things becomes as simple as
plugging it in and switching it on. Such plug and play functionality requires an
infrastructure that supports it, starting from the networking level and going beyond it
to the application level. This is closely related to the aspects discussed in the section on
autonomy.
• On the networking level, the plug & play functionality has to enable the
communication, features like the ones provided by IPv6 are in the directions to help in
this process. Suitable infrastructure components have then to be discovered to enable
the integration into the Internet of Things. This includes announcing the functionalities
provided, such as what can be sensed or what can be actuated.

2. Infrastructure Functionality-The infrastructure needs to support applications in finding the

things required. An application may run anywhere, including on the things themselves. Finding
things is not limited to the start-up time of an application. Automatic adaptation is needed
whenever relevant new things become available, things become unavailable or the status of
things changes. The infrastructure has to support the monitoring of such changes and the
adaptation that is required as a result of the changes.

3. Semantic Modeling of Things-To reach the full potential of the Internet of Things, semantic
information regarding the things, the information they can provide or the actuations they can
perform need to be available. It is not sufficient to know that there is a temperature sensor or
an electric motor, but it is important to know which temperature the sensor measures: the
indoor temperature of a room or the temperature of the fridge, and that the electric motor
can open or close the blinds or move something to a different location. As it may not be
possible to provide such semantic information by simply switching on the thing, the
infrastructure should make adding it easy for users. Also, it may be possible to derive semantic
information, given some basic information and additional knowledge, e.g. deriving information
about a room, based on the information that a certain sensor is located in the room. This
should be enabled by the infrastructure.
4. Physical Location and Position-As the Internet of Things is strongly rooted in the physical
world, the
notion of physical location and position are very important, especially for finding things,
but also for deriving knowledge. Therefore, the infrastructure has to support finding things
according to location (e.g. geo-location based discovery). Taking mobility into account,
localization technologies will play an important role for the Internet of Things and may
become embedded into the infrastructure of the Internet of Things.

5. Security and Privacy-In addition, an infrastructure needs to provide support for security
and privacy functions including identification, confidentiality, integrity, non-repudiation
authentication and authorization. Here the heterogeneity and the need for interoperability
among different ICT systems deployed in the infrastructure and the resource limitations of
IoT devices (e.g., Nano sensors) have to be taken into account.

i.e. Logical View

What are the application of IOT?
:=> IOT applications-Potential applications of the IoT are numerous and diverse, permeating
into practically all areas of every-day life of individuals, enterprises, and society as a whole. The
IoT application covers smart environments/spaces in domains such as: Transportation,
Building, City, Lifestyle, Retail, Agriculture, Factory, Supply chain, Emergency, Healthcare, User
interaction, Culture and tourism, Environment and Energy. Below are some of the IoT
applications.
• IOsL (Internet of smart living)-Remote Control Appliances: Switching on and off
remotely appliances to avoid accidents and save energy, Weather: Displays outdoor
weather conditions such as humidity, temperature, pressure, wind speed and rain
levels with ability to transmit data over long distances, “mart Home Appliances:
Refrigerators with LCD screen telling what’s inside, food that’s about to expire,
ingredients you need to buy and with all the information available on a Smartphone
app. Washing machines allowing you to monitor the laundry remotely, and. Kitchen
ranges with interface to a Smartphone app allowing remotely adjustable temperature
control and monitoring the oven’s self-cleaning feature, Safety Monitoring: cameras,
and home alarm systems making people feel safe in their daily life at home, Intrusion
Detection Systems: Detection of window and door openings and violations to prevent
intruders, Energy and Water Use: Energy and water supply consumption monitoring to
obtain advice on how to save cost and resources.
• IOsC ( Internet of smart cities)-Structural Health: Monitoring of vibrations and
material conditions in buildings, bridges and historical monuments, Lightning:
intelligent and weather adaptive lighting in street lights, Safety: Digital video
monitoring, fire control management, public announcement systems, Transportation:
Smart Roads and Intelligent High-ways with warning messages and diversions according
to climate conditions and unexpected events like accidents or traffic jams, Smart
Parking: Real-time monitoring of parking spaces availability in the city making
residents able to identify and reserve the closest available spaces, Waste Management:
Detection of rubbish levels in containers to optimize the trash collection routes.
Garbage cans and recycle bins with RFID tags allow the sanitation staff to see when
garbage has been put out.
• IOsE (Internet of smart environment)-Air Pollution monitoring: Control of CO2
emissions of factories, pollution emitted by cars and toxic gases generated in farms,
Forest Fire Detection: Monitoring of combustion gases and preemptive fire conditions
to define alert zones, Weather monitoring: weather conditions monitoring such as
humidity, temperature, pressure, wind speed and rain, Earthquake Early Detection,
Water Quality: Study of water suitability in rivers and the sea for eligibility in drinkable
use, River Floods: Monitoring of water level variations in rivers, dams and reservoirs
during rainy days, Protecting wildlife: Tracking collars utilizing GPS/GSM modules to
locate and track wild animals and communicate their coordinates via SMS.
• IOsI (Internet of smart industry)-Explosive and Hazardous Gases: Detection of gas
levels and leakages in industrial environments, surroundings of chemical factories and
inside mines, Monitoring of toxic gas and oxygen levels inside chemical plants to ensure
 workers and goods safety, Monitoring of water, oil and gas levels in storage tanks and
Cisterns, Maintenance and repair: Early predictions on equipment malfunctions and
service maintenance can be automatically scheduled ahead of an actual part failure by
installing sensors inside equipment to monitor and send reports.
• IOsH (Internet of smart health)-Patients Surveillance: Monitoring of conditions of
patients inside hospitals and in old people’s home, Medical Fridges: Control of
conditions inside freezers storing vaccines, medicines and organic elements, Fall
Detection: Assistance for elderly or disabled people living independent, Dental:
Bluetooth connected toothbrush with Smartphone app analyzes the brushing uses and
gives information on the brushing habits on the Smartphone for private information or
for showing statistics to the dentist, Physical Activity Monitoring: Wireless sensors
placed across the mattress sensing small motions, like breathing and heart rate and
large motions caused by tossing and turning during sleep, providing data available
through an app on the Smartphone.
• IOsE (internet of smart energy)-Smart Grid: Energy consumption monitoring and
management, Wind Turbines/ Power house: Monitoring and analyzing the flow of
energy from wind turbines & power house, and two-way communication with
consumers’ smart meters to analyze consumption

patterns, Power Supply Controllers: Controller for AC-DC power supplies that
determines required energy, and improve energy efficiency with less energy waste for
power supplies related to computers, telecommunications, and consumer electronics
applications, Photovoltaic Installations: Monitoring and optimization of performance in
solar energy plants.
• IOsA (internet of smart agriculture)-Green Houses: Control micro-climate conditions
to maximize the production of fruits and vegetables and its quality, Compost: Control
of humidity and temperature levels in alfalfa, hay, straw, etc. to prevent fungus and
other microbial contaminants, Animal Farming/Tracking: Location and identification of
animals grazing in open pastures or location in big stables, Study of ventilation
and air quality in farms and detection of harmful gases from excrements, Offspring
Care: Control of growing conditions of the offspring in animal farms to ensure its
survival and health, field Monitoring: Reducing spoilage and crop waste with better
monitoring, accurate ongoing data obtaining, and management of the agriculture
fields, including better control of fertilizing, electricity and watering.
 i.e. Application of IOT

Reference:
https://ijesc.org/upload/8e9af2eca2e1119b895544fd60c3b857.Internet%20of%20
Things-
IOT%20Definition,%20Characteristics,%20Architecture,%20Enabling%20Techn
ologies,%20Application%20&%20Future%20Challenges.pdf

https://www.interviewbit.com/iot-interview-questions/

https://vedveethi.co.in/eNote/IoT/CS-6005%20Unit%201%20-
%20Internet%20of%20Things.htm