Table of Contents

Overview ............................................................................................................................ 2
Source Code Introduction ................................................................................................. 2
Required Dependencies ................................................................................................. 2
Source Code Directory Structure ................................................................................. 2
Understanding the Source Code ................................................................................... 2
Source Code Architecture............................................................................................ 2
Real-Time Application Source Code ........................................................................... 3
Configuration Files ...................................................................................................... 6
FPGA Application Source Code.................................................................................. 6
Web Service Source Code ........................................................................................... 7
LCD Display Firmware Source Code .......................................................................... 9
Running and Building the Source Code ...................................................................... 9
Customization Example – Using Different Module Sets .............................................. 11
Overview ...................................................................................................................... 11
Customizing FPGA Source Code ............................................................................... 11
Replacing Modules .................................................................................................... 11
Changing FPGA VIs ................................................................................................. 11
Changing Module Set Configuration in Web Client ................................................. 13
Rebooting to Safe Mode ............................................................................................ 13
Setting New Module Set Configuration..................................................................... 13
Running Customized Source Code ............................................................................ 13
This article introduces the source code of the NI PMU personality software and how to
customize the source code for different module sets.

You must install the following software applications before you can use the source code of
the NI PMU personality software:
 LabVIEW 2015
 LabVIEW 2015 Real-Time Module
 LabVIEW 2015 FPGA Module
 NI CompactRIO 15.0
 LabVIEW 2015 Electrical Power Suite Professional Edition
 Gemstudio Pro*
Note: Gemstudio Pro is used to develop the LCD display firmware. If you do not need to
develop the LCD display firmware, Gemstudio Pro is not required.

After you download and unzip the source code file, you can find the Source Code folder,
which contains the following four folders:
 The Configuration Files folder contains the system configuration files.
 The FPGA Source Code folder contains the source code of the FPGA application.
 The LCD Display Source Code folder contains the source code of the LCD display
firmware.
 The RT Source Code folder contains the source code of the real-time application.

The following diagram shows the overall architecture of the source code.
 LCD display
(Gemstudio Pro code)

Retrieve network settings Apply new network settings to the system

real-time target

Initialize FPGA configuration Send data,configuration

Send HTTP requests
Voltage/current input signals Web client
FPGA application Real-time application Web service
(HTML,
(LabVIEW FPGA) (LabVIEW) (LabVIEW)
JavaScript, etc.)
Transfer processed data Return new configuration Respond to HTTP requests
via DMA FIFO

Read configuration Write new configuration

Configuration files
(JSON)

C37.118 frames via TCP/UDP

PDC PDC … PDC

 The FPGA application processes the sampled voltage or current signals to obtain the
measured results, and transfers the measured results to the real-time application via
DMA FIFO.
 The real-time application is the core application of the NI PMU personality software.
The real-time application has functions such as generating and sending the reported
data, and interacting with the web service and the LCD display, etc.
 The configuration files store the system configuration. The file format of the
configuration files is JSON.
 The LCD display obtains the system network settings and the system firmware
version and displays the information, and enables users to change the system network
settings.
 The web service enables the communication between the NI PMU personality
software and the web client, so that the users can monitor and configure the NI PMU
personality software in the web client.

In the RT Source Code folder, the GAS_PMU.lvproj is the project of the real-time
application source code, and the Main.vi is the top-level VI of the real-time application.

The following diagram shows the overall architecture of the real-time application
(Main.vi). The real-time application works in two different modes. In normal mode, the
real-time application executes phasors measurement and reporting tasks. The processes
such as the data acquisition process and the communication process run in normal mode.
In safe mode, the real-time application executes system firmware upgrade and module set
configuration customization tasks. The system firmware upgrade process runs in safe
mode. Some common processes such as the background process and the watchdog process
run in both modes.

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 Safe mode processes

System firmware
upgrade

Yes
Normal mode processes

No Initialize PMU
Initialize system Data acquisition Shutdown system
safe mode = configuration
true ?

Communication

Read/write PMU
configuration (for
web service)

Common processes

Background

Read/write module
set configuration
(for web service)

LCD display
interface

Watchdog

The real-time application executes some initialization tasks when starting up such as:
 Initialize the system parameters.
 Initialize the software watchdog and the hardware watchdog in the system.
 Check whether the system is in safe mode and whether to enable the interaction with
the LCD display.

The real-time application initializes the PMU configuration to get ready for phasors
measurement and reporting. The real-time application executes the following tasks for
initializing the PMU configuration.
 Read the PMU configuration from the configuration files in the system.
 Select and open the FPGA bitfile reference according to the configuration. Configure
and start the FPGA application.
The data acquisition process gets the reported data with the following execution flow.
 Read the measured results from the FPGA application via DMA FIFO.
 Post-process the measured results to obtain the reported data.
 Build the data frames from the reported data, and transfer the data frames to the
communication process.

The communication process creates a unique communication thread for each

communication stream channel if the communication stream channel is enabled in the web
client. Each communication thread has five working modes as configured in the web
client: TCP, UDP – only, UDP – spontaneous, UDP – T, and UDP – U. In any of the
working modes, there are a loop for responding to the received commands from the PDCs
and a loop for sending the data frames to the PDCs.

The read/write PMU configuration process is the interface of the real-time application for
exchanging the PMU configuration with the web service. When the web service sends a
request to get the PMU configuration, the real-time application sends the PMU
configuration to the web service. When the web service sends a request to post the new
PMU configuration, the real-time application writes the new PMU configuration to the
configuration file.

The background process executes some background tasks regularly, such as logging the
system events, archiving the logging files, and toggling the LED status, etc.

The read/write module set configuration process is the interface of the real-time
application for exchanging the module set configuration with the web service. When the
web service sends a request to get the module set configuration, the real-time application
sends the module set configuration to the web service. When the web service sends a
request to post the new module set configuration, the real-time application writes the new
module set configuration to the configuration file.

The LCD display interface process is the interface of the real-time application for
communicating with the LCD display.

In normal mode, the real-time application sends the system network settings and the
system firmware version to the LCD display when starting up. In addition, the real-time
application regularly checks whether the users have changed the system network settings
in the LCD display, and applies the new network settings to the system.

In safe mode, the real-time application only sends the system network settings to the LCD
display, so that the users can obtain the system IP address in the LCD display.

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The real-time application uses the watchdog to monitor the processes. In each process
except the watchdog process, there is a software watchdog to check whether the process
hangs abnormally during execution. The watchdog process monitors the status of all the
software watchdogs. If any software watchdog expires, the watchdog process will reboot
the system. In addition, the watchdog process also resets the hardware watchdog regularly.
If the watchdog process does not reset the hardware watchdog before it times out, then the
hardware watchdog will reboot the system.

The system firmware upgrade process receives the system firmware file uploaded from the
web client, and uses the system firmware file to upgrade the system firmware.

After all the processes exit from execution, the real-time application releases the queues
used in the system and reboots the system.

There are two configuration files in the Configuration Files folder. The
PMUConfig.json file stores the PMU configuration, and the ModuleConfig.json
file stores the module set configuration. You must manually store the two configuration
files in the real-time target before running the real-time application.

There are two sets of FPGA application source code for two different module set
configurations.
 The FPGA 9242 9238 Support folder contains the FPGA source code that supports
the default module set configuration with two NI 9242s and two NI 9238s and the
corresponding FPGA bitfiles.
 The FPGA 9225 9227 Support folder contains the FPGA source code that supports
the module set configuration with two NI 9225s and two NI 9227s and the
corresponding FPGA bitfiles.

In either of the above two folders, there are four top-level FPGA VIs for different
combinations of performance class and nominal frequency. In addition, the FPGA 9242
9238 Support folder contains an extra VI - the Synchrophasor Measurement
M_60Hz_1bus.vi for demonstration of how to customize the FPGA source code to
support one-bus module set configuration.

All the top-level FPGA VIs have the same architecture as below.
 FPGA timekeeper loop

Synchronize the
timestamp with GPS

Digital loop

Read digital input signals

from the DI module(s)

Data acquisition loop

Read the voltage/current

Initialize the filter Set the sampling rate of Type cast the sampled Write the sampled data to
1 Start the modules signals from the AI
coefficients in memories the modules data FIFO
modules

Phasor measurement loop

Input the sampled data

Read the sampled data Obtain the measured
and the timestamp to the
from FIFO results and write to FIFO
phasor measurement API

Data communication loop

Transfer the measured

Read the measured
results to the real-time
results from FIFO
application via DMA FIFO

1Initializing the filter coefficients in memories is necessary only for the performance class
of M class.

The web service named PMU is under RT CompactRIO Target in the

GAS_PMU.lvproj. The physical path of the web service source code is …\Source
Code\RT Source Code\WebMethods\.

The following diagram shows how the web service works with the real-time application
and the web client.
Communication via Communication via
Web service
queues or global variables HTTP requests

Requested HTMLs, JavaScripts, etc.

Public content

Real-time application Send HTTP requests1

Web client
(Main.vi) Exchange data, configuration
HTTP method VIs

Respond to HTTP requests

Startup VI2

1The web client sends the HTTP requests to get the data, configuration and post the new
configuration, etc.
2 The startup VI monitors the status of the web service.

The web client source code (the public content) uses some 3 rd-party open source
libraries/frameworks as follows. The physical path of the 3 rd-party libraries source code is
…\Source Code\RT Source Code\WebMethods\Public Content\libs\.
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 AngularJS. AngularJS is a structural framework for dynamic web apps. The source
code is in the angular folder. The web client mainly utilizes the following features of
AngularJS.
 AngularJS lets you use HTML as your template language and lets you
extend HTML's syntax, to render dynamic view that a user sees in the web
browser.
 Data-binding in AngularJS automatically synchronizes the data between the
values of the variables in JavaScript and the view in HTML. For example,
when the values of the reported phasors are updated in JavaScript with the
data sent from the real-time target, the view of HTML can be updated
automatically to display the latest values of the reported phasors.
 A controller in AngularJS is a JavaScript constructor function. You can
attach a controller to a DOM in HTML, to set up the initial state and add
behavior for the DOM.
 The $http service is a core Angular service that facilitates communication
with the remote HTTP servers.
 AngularUI Router is a routing framework for AngularJS, which allows you
to organize the parts of your interface into a state machine, to load different
subpages into the view.
 Bootstrap. Bootstrap is an HTML, CSS, and JS framework for developing
responsive, mobile first projects on the web. The source code is in the bootstrap
folder. The web client mainly utilizes the following features of Bootstrap.
 Bootstrap can organize and format the view of HTML more easily and
efficiently.
 Bootstrap can realize visual dynamics when triggering events.
 Bootstrap has a lot of plugins to improve the user interaction, such as the
modal dialog, etc.
 Easy pie chart. Easy pie chart is a jQuery plugin that uses the canvas element to
render simple pie charts for single values. The source code is in the easypie folder.
The web client uses this plugin to render pie charts for the CPU usages, the memory
usage, and the disk usage of the real-time target.
 The fonts folder contains a 3rd-party library Font Awesome and a customized font
library which provide all the icons used by the web client.
 toastr. toastr is a Javascript library for Gnome / Growl type non-blocking
notifications. The source code is in the toastr folder. The web client uses this library
to notify the users of the results of the HTTP requests to the web server.

The diagram below shows the hierarchy of the web client. The index.html file is the
top-level page and all the other HTML files (subpages) display in the scope of the
index.html file. The index.html file bootstraps the AngularJS application by
referencing the module pmuApp that is defined and configured in the pmuModule.js
file. Some controllers such as startCtrl, appCtrl, moduleCtrl, and initCtrl are defined in the
respective JavaScript files, and are attached to the respective DOMs in the HTML files.
These controllers realize the functions, such as updating the dashboard data, getting the
configuration, and posting the new configuration, etc.
 index.html
(startCtrl)

moduleconfig.html normalmode.html
safemode.html
(moduleCtrl) (appCtrl)

dashboard.html settings.html about.html

(initCtrl) (settingsCtrl) (aboutCtrl)

dashboard.phasors. dashboard.analog. dashboard.digital.

settings.base. settings.comm. settings.sensors. settings.phasors. settings.analog. settings.digital.
html html html
html html html html html html
(phasorsCtrl) (analogCtrl) (digitalCtrl)

You can find the source code of the LCD display firmware in the LCD Display Source
Code folder.
 The PMU.gemp file in the Gemstudio Pro Project folder is the project of the LCD
display firmware.
 The Display folder in the Gemstudio Pro Project folder contains all the pictures
used in the source code of the LCD display firmware.
 The PMUDisplayFirmware.pdb file in the Display Firmware folder is the LCD
display firmware file.
 The Display Upgrade Utility folder contains a LabVIEW project to deploy the LCD
display firmware file to the LCD display.

You can open and edit the PMU.gemp file with the GEMstudio Pro. The work flow of the
source code is as follows.

Eth1 settings
page Users change the settings
Users click the button

Network settings
Restart page
Users click the button page
Real-time application
starts up No Users click the button Eth2 settings
Startup page Main page Users change the settings
System is page
in safe mode?
Users click the button
About page

Yes
Show system IP
in startup page

You can compile the source code in GEMstudio Pro to obtain the LCD display firmware
file (.pdb). After obtaining the LCD display firmware file, you can deploy the LCD
display firmware from your local machine by using the Upgrade Firmware.vi in the
Display Upgrade Utility folder.

You must complete the following steps to run the source code on the real-time target.
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 Install the following software set add-ons in addition to the recommended software
set to the real-time target from NI MAX.
 Language Support for Japanese 15.0.0
 Language Support for Simplified Chinese 15.0.0
 NI System Configuration 15.0.0
 System State Publisher 3.4.0
 NI-VISA 15.0.0
 NI-VISA Server 15.0.0
 NI-Watchdog 15.0.0
 Hardware Configuration Web Support 15.0.0
 HTTP Client with SSL Support 15.0.0
 Network Configuration Web Support 15.0.0
 NI Application Web Server 15.0.0
 NI Web-based Configuration and Monitoring 15.0.0
 NI Wireless Certificate Management Web Service 2.0
 Remote Panel Server for LabVIEW RT 15.0.0
 SMTP Client with SSL Support 15.0.0
 Software Management Web Support 15.0.0
 Time Configuration Web Support 15.0.0
 WebDAV Client with SSL Support 15.0.0
 Copy the app folder in …\Source Code\Configuration Files\ from your
local machine to the following path of the real-time target: /home/lvuser.
 Create a folder with the name of FPGA bitfiles under the following path of the real-
time target: /home/lvuser. Create a folder with the name of 9242_9238 with
default current shunts in the FPGA bitfiles folder. Copy the 4 FPGA bitfiles in
…\Source Code\FPGA Source Code\FPGA 9242 9238 Support\FPGA
Bitfiles to the 9242_9238 with default current shunts folder in the real-time
target.
 Open the file fstab under the following path of the real-time target: /etc. Find the
line “tmpfs /var/volatile tmpfs size=64m 0 0”, and change
“size=64m” to “size=150m”. This step is to increase the size of the tmp folder
which holds the uploaded system firmware file.
 Open the file niwsdebugserver.conf.template under the following path of
the real-time target: /usr/local/natinst/labview/webserver. Change the
values of LimitRequestBody and LimitRequestForm to 150000000. This step
is to increase the uploading file size limit of the debugger web server.
 Restart the real-time target.
 Run the Main.vi and the PMU web service on the real-time target.

You can build the source code with the default build specification under the
GAS_PMU.lvproj to obtain the real-time application. The default build specification
includes a post-build action VI. You can find the VI under My Computer in the
GAS_PMU.lvproj. This VI modifies the application web server configuration to increase
the limit of the uploaded file size for firmware upgrading, and it will automatically run
after the source code building completes.
After running the real-time application in the real-time target, you can retrieve the system
firmware from the real-time target by using the Replication and Deployment (RAD) Utility
to quickly distribute the application to the other real-time targets.

This chapter introduces how to customize module set configuration in the source code
when using different module sets other than the default one with two NI 9242s and two NI
9238s. Generally, you must complete two steps as follows.
 Customize the FPGA source code.
 Change the module set configuration in the web client.

You can customize the FPGA source code based on the default source code under the
FPGA 9242 9238 Support folder.

After opening the Synchrophasor Measurement 9242 9238 Support.lvproj,

you can see 6 modules under FPGA Target.
 Voltage 1. This is the bus 1 voltage input module, and the default module is NI 9242.
 Voltage 2. This is the bus 2 voltage input module, and the default module is NI 9242.
 Current 1. This is the bus 1 current input module, and the default module is NI 9238.
 Current 2. This is the bus 2 current input module, and the default module is NI 9238.
 GPS. This is the GPS module which is used to get the GPS time, and the default
module is NI 9467 and it should not be changed.
 Digital. This is the digital input module, and the default module is NI 9437.

You can replace the above default modules with your customized ones.
 Any voltage or current input module should have three or four input channels.
 If you replace any of the voltage or current input modules, be aware that you should
always set one of the voltage or current input modules as the time master by
exporting its onboard clock, and then set the time source of the other voltage or
current input modules as the exported clock of the time master.
 For the Digital module, you can use either one digital input module with 8 digital
channels or two digital input modules with 4 digital channels for each one.

Find the five FPGA VIs under the FPGA Target as follows.
 Synchrophasor Measurement M_50Hz.vi. This is the FPGA VI for M class
of performance and 50Hz nominal frequency system.
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 Synchrophasor Measurement M_60Hz.vi. This is the FPGA VI for M class
of performance and 60Hz nominal frequency system.
 Synchrophasor Measurement P_50Hz.vi. This is the FPGA VI for P class of
performance and 50Hz nominal frequency system.
 Synchrophasor Measurement P_60Hz.vi. This is the FPGA VI for P class of
performance and 60Hz nominal frequency system.
 Synchrophasor Measurement M_60Hz_1 bus.vi. This is an example for
demonstration of how to customize the FPGA source code to support only one bus. It
is recommended to use this example as a reference when customizing the FPGA
source code.

To customize the FPGA source code, you must change the first four FPGA VIs. In the
FPGA VIs, there are eight Diagram Disable Structures, each Diagram Disable Structure
has three Subdiagrams which are “9242_9238”, “9225_9227”, and “customized”. By
default, the Subdiagram of “9242_9238” is enabled in the FPGA VIs. You can enable the
Subdiagram of “customized”, and add your customized code in the Subdiagram of
“customized”. Follow the steps below to change the FPGA VIs.
 Set the sampling rate of the voltage and current input modules as 50kS/s.
 Start the voltage and current input modules.
 Read the digital input values from the digital modules. The PMU system supports 8
digital input channels, but if you do not have digital input channels in the customized
code, you can simply assign 0 to the lower byte of the 16-bit Digital indicator.
 Read the bus wiring types from RT target.
 The wiring types array contain the wiring types of the two buses, but if you
only have one bus in the customized code, the wiring types array will only
have one element.
 The usage of the bus wiring types depends on the type of the voltage input
channels. For single-ended channels such as NI 9242, you must use the bus
wiring types to convert the sampled voltage signals if necessary. For
differential channels such as NI 9225, you can change the wiring of the
input voltage cables to determine the bus wiring type, so you do not need to
use the bus wiring types in the FPGA code. Refer to the source code under
the FPGA 9225 9227 Support folder for the different usage of the bus
wiring types.
 Read the sampled data from the voltage and current input modules. You must always
place the voltage and current input channels in the order of Voltage 1, Voltage 2,
Current 1, and Current 2 from top to bottom.
 Type cast the sampled data from each channel to fixed-point<±,24,1> by using a
Fixed-Point to Integer Cast node and an Integer to Fixed-Point Cast node, and build
the converted data into an array.
 Type cast the measured results from fixed-point <+,32,6> to different data types to
scale the measured results according the above step.
 Stop the voltage and current input modules.

After changing the code in the four FPGA VIs, you can compile the FPGA bitfiles for the
four FPGA VIs, and name the FPGA bitfiles as follows:
 M_50Hz.lvbitx for Synchrophasor Measurement M_50Hz.vi.
 M_60Hz.lvbitx for Synchrophasor Measurement M_60Hz.vi.
 P_50Hz.lvbitx for Synchrophasor Measurement P_50Hz.vi.
 P_60Hz.lvbitx for Synchrophasor Measurement P_60Hz.vi.

Run the source code in the real-time target, and reboot the application to safe mode by the
following two ways.
 Click the Reboot to safe mode button in the About page of the web client.
 The application will automatically reboot to safe mode if it detects a system error.

You can access the Module Set Configuration page in safe mode by clicking the
Customize Module Set Configuration button.

To add new module set configuration, click the Add New Module Set Configuration
button. Then you can edit the name of the new module set configuration, the number of
voltage and current channels, and the group delay of voltage and current modules. After
setting these values, you can select the new module set configuration and save the
changes.

Follow the steps below to run the customized source code in the real-time target.
 Create a folder with the same name of the new module set configuration under the
following path of the real-time target: /home/lvuser/FPGA bitfiles.
 Copy the four new FPGA bitfiles to the created folder.

Run the Main.vi in the real-time target.

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