CENG3430 Rapid Prototyping of Digital Systems

Lecture 12:
VHDL versus Verilog

Ming-Chang YANG
[email protected]
Outline
• VHDL vs. Verilog
– Background
– Syntax and Popularity
– Operators
– Overall Structure
– External I/O Declaration
– Concurrent Statements
– Sequential Statements
• Edge Detection
– Wire vs. Reg
– Structural Design
– Design Constructions
– Case Study: Flip-flop
CENG3430 Lec12: VHDL versus Verilog 2
What are VHDL and Verilog?

• They are both hardware description languages for

modeling hardware.
• They are each a notation to describe the behavioral
and structural aspects of an electronic digital circuit.

CENG3430 Lec12: VHDL versus Verilog 3

VHDL: Background
• VHSIC Hardware Description Language
– VHSIC: Very High Speed Integrated Circuit.

• Developed by Department of Defense (1981)

– In 1986 rights where given to IEEE.
– Became a standard and published in 1987.
– Revised standard we know now published in 1993 (VHDL
1076-1993) regulated by VHDL international (VI).

CENG3430 Lec12: VHDL versus Verilog 4

VHDL: Design Concept
• VHDL uses top-down approach to partition a design
into small building blocks (i.e., components).
– Entity: Describe interface signals and basic building blocks.
– Architecture: Describe behavior, each entity can have
multiple Architectures.

Component A

Component B Component C

Connected by port map in architecture body

CENG3430 Lec12: VHDL versus Verilog 5
Verilog: Background
• Developed by Gateway Design Automation (1980)
– Later acquired by Cadence Design (1989) who made it
public in 1990
– Became a standardized in 1995 by IEEE (Std 1364)
regulated by Open Verilog International (OVI)

CENG3430 Lec12: VHDL versus Verilog 6

Verilog: Design Concept
• The building block in Verilog is called module.
– There is only one module per file (.v) usually.
– Modules connect through their ports (similarly as in VHDL).
– A top level module invokes instances of other modules.

Top Module
Module Module Module

Connected by relating I/O and internal wires

CENG3430 Lec12: VHDL versus Verilog 7

Syntax and Popularity

Popularity
VHDL is more popular with Verilog is more popular with
European companies. US companies.

Programming Style (Syntax)

VHDL is similar to Ada Verilog is similar to C/Pascal
programming language. programming language.
VHDL is NOT case-sensitive. Verilog is case-sensitive.
VHDL is more “verbose” than Verilog.
CENG3430 Lec12: VHDL versus Verilog 9
Operators
VHDL Verilog VHDL Verilog
Add + + Bitwise Negation not ~
Subtract - - Bitwise NAND nand ~&
Multiplication * * Bitwise NOR nor ~|
Division / / Bitwise XNOR xnor ~^
Modulo mod % Greater (or Equal) >, >= >, >=
Absolute abs N/A Less (or Equal) <, <= <, <=
Exponentiation ** ** Logical Equality = ==
Concatenation & { , } Logical Inequality /= !=
Left Shift sll << Logical AND and &&
Right Shift srl >> Logical OR or ||
Bitwise AND and & Logical Negation not !
Bitwise OR or | Case Equality N/A ===
Bitwise XOR xor ^ Case Inequality N/A !==
CENG3430 Lec12: VHDL versus Verilog 10
Outline
• VHDL vs. Verilog
– Background
– Syntax and Popularity
– Operators
– Overall Structure
– External I/O Declaration
– Concurrent Statements
– Sequential Statements
• Edge Detection
– Wire vs. Reg
– Structural Design
– Design Constructions
– Case Study: Flip-flop
CENG3430 Lec12: VHDL versus Verilog 11
Overall Structure
VHDL (.vhd) Verilog (.v)
-- Library Declaration // One Module
library IEEE; module mux ( ... );
...
-- Entity Declaration
entity mux is
...
end mux ...
-- Architecture Body
architecture arch of mux is
begin
...
end arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 12
External I/O Declaration
VHDL Verilog
-- Library Declaration // One Module
… module mux (a, b, s, y);
-- Entity Declaration input a,b,s;
entity mux is output y;
port(a,b,s: in std_logic;
y: out std_logic);
end mux
-- Architecture Body ...
architecture arch of mux is
begin
...
end arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 13
Concurrent & Sequential Statements
VHDL Verilog
-- Entity Declaration // One Module
entity mux is module mux (a, b, s, y);
port(a,b,s: in std_logic; input a,b,s;
y: out std_logic); output y;
end mux
architecture arch of mux is -- concurrent statements
begin
-- concurrent statements always @(...)
process (...) begin begin
-- sequential statements -- sequential statements
end process; end process;
end arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 14
1) Concurrent Statement
VHDL: inside architecture body, outside the process
signal a, b: std_logic_vector(7 downto 0); -- array
signal c, d, e: std_logic; LHS <= RHS;
a(3 downto 0) <= b(7 downto 4); • LHS must be signal.
b(7 downto 4) <= “0000”; • The LHS will be updated
whenever RHS changes.
c <= d and e; -- bitwise AND

Verilog: outside the always@ block

wire [7:0] a, b; // array
wire c, d, e; assign LHS = RHS;
assign a[3:0] = c[7:4]; • LHS must be wire.
assign b[7:4] = 'b0000; // binary • The LHS will be updated
whenever RHS changes.
assign c = d & e; // bitwise AND
CENG3430 Lec12: VHDL versus Verilog 15
 Student ID: Date:
Class Exercise 12.1 Name:

• Translate the following VHDL program to Verilog:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity abc is
port (a,b,c: in std_logic;
y: out std_logic);
end abc;
architecture abc_arch of
abc is
signal x : std_logic;
begin
x <= a nor b;
y <= x and c;
end abc_arch;
CENG3430 Lec12: VHDL versus Verilog 16
2) Sequential Statement
VHDL Verilog
architecture arch of ex is module ex (…);
begin reg a, b, c;
process( sensitivity list ) always @ ( conditions )
variable a, b, c; begin
begin
-- LHS could be signals // LHS must be reg (not wire)
(suggested) or variables
-- signal assignment (<=) // blocking assignment (=)
for both combinational logic for combinational logic
and sequential logic // non-blocking assignment
-- variable assignment (:=) (<=) for sequential logic
end; end
end arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 18
2) Sequential Statements: Blocking
• Blocking assignments (=) in a sequential block (i.e.,
always@) are executed before the execution of the
statements that follow it.
– All blocking assignments are executed in a sequentially way.
• Usage: Use blocking assignments in always@ blocks
to synthesize combinational logic (i.e. no clock!).
reg r1, r2, r3;
...
a r1
always @ (a or b)
begin b
r1 = a & b; r3
r2 = a | b;
r3 = r1 | r2; r2
end
CENG3430 Lec12: VHDL versus Verilog 19
 Student ID: Date:
Class Exercise 12.2 Name:

• Translate the following Verilog program to VHDL:

reg r1, r2, r3;

...
always @ (a or b)
begin
r1 = a & b;
r2 = a | b;
r3 = r1 | r2;
end

CENG3430 Lec12: VHDL versus Verilog 20

2) Sequential Statements: Non-Blocking
• Non-blocking assignments (<=) in a sequential
block (i.e., always@) are executed within the same
time step regardless of the order.
– All non-blocking assignments will take effect at the next
clock edge (concurrently, not sequentially!).
• Usage: Use non-blocking assignments in always@
blocks to synthesize sequential logic (i.e. has clock!).
reg r1, r2;
... a r1 r2
always @ (posedge clk) D Q D Q
begin
r1 <= a;
r2 <= r1; clk
end
CENG3430 Lec12: VHDL versus Verilog 22
Edge Detection

rising/positive edge falling/negative edge

VHDL Verilog
process (clk) always @ (posedge clk)
begin or
sensitivity list
... always @ (negedge clk)
if rising_edge(CLK) begin
or conditions
if falling_edge(CLK) ...
...
end conditions end
CENG3430 Lec12: VHDL versus Verilog 23
 Student ID: Date:
Class Exercise 12.3 Name:

• Translate the following Verilog program to VHDL:

reg r1, r2;

...
always @ (posedge clk)
begin
r1 <= a;
r2 <= r1;
end

CENG3430 Lec12: VHDL versus Verilog 24

“wire” vs. “reg” in Verilog
• Wire: Has no memory
– It must be physical wire in the circuit.
– It does not hold the value.
– Usage: Cannot use “wire” in the left-hand-side of
assignments inside always@ blocks!

• Reg: Has memory

– It could be a flip-flop or a physical wire.
– It holds the value until a new value is assigned.
– Usage: Cannot use “reg” in the left-hand side of
assignments outside always@ blocks (i.e., concurrent
assignment)!

CENG3430 Lec12: VHDL versus Verilog 26

Outline
• VHDL vs. Verilog
– Background
– Syntax and Popularity
– Operators
– Overall Structure
– External I/O Declaration
– Concurrent Statements
– Sequential Statements
• Edge Detection
– Wire vs. Reg
– Structural Design
– Design Constructions
– Case Study: Flip-flop
CENG3430 Lec12: VHDL versus Verilog 27
Structural Design in VHDL (1/2)
• Structural Design in VHDL: Like a circuit but describe
it by text.
Component A

Component B Component C

Connected by port map in architecture body

• Design Steps:
Step 1: Create entities
Step 2: Create components from entities
Step 3: Use “port map” to relate the components
CENG3430 Lec12: VHDL versus Verilog 28
Structural Design in VHDL (2/2)
1 library IEEE; 1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL; 2 use IEEE.STD_LOGIC_1164.ALL;
3 entity and2 is Step 1 3 ----------------------------------------------
4 port (a,b: in STD_LOGIC; 4 entity test is
5 c: out STD_LOGIC ); 5 port ( in1: in STD_LOGIC; in2: in STD_LOGIC;
6 end and2; 6 in3: in STD_LOGIC;
7 architecture and2_arch of and2 is 7 out1: out STD_LOGIC );
8 begin 8 end test;
9 c <= a and b; 9 architecture test_arch of test is
10 end and2_arch; 10 component and2 --create component Step 2
11 --------------------------------- 11 port (a,b: in std_logic; c: out std_logic);
12 library IEEE; 12 end component ;
13 use IEEE.STD_LOGIC_1164.ALL; 13 component or2 --create component
14 entity or2 is Step 1 14 port (a,b: in std_logic; c: out std_logic);
15 port (a,b: in STD_LOGIC; 15 end component ;
16 c: out STD_LOGIC ); 16 signal inter_sig: std_logic;
17 end or2; 17 begin Step 3
18 architecture or2_arch of or2 is 18 label1: and2 port map (in1, in2, inter_sig);
19 begin 19 label2: or2 port map (inter_sig, in3, out1);
20 c <= a or b; 20 end test_arch;
21 end or2_arch;
CENG3430 Lec12: VHDL versus Verilog 29
Structural Design in Verilog (1/2)
• Structural Design in Verilog: One top module, several
(sub) modules.
Top Module
Module Module Module

Connected by relating I/O and internal wires

• Design Steps:
Step 1: Create (sub) module(s) (usually in separate .v files)
Step 2: Define a top-module to interconnect module(s)

CENG3430 Lec12: VHDL versus Verilog 30

Structural Design in Verilog (2/2)
and2.v top_module.v
module and2( Step 1 module top_module( Step 2
input a, input in1, input in2, input in3,
input b, output out1 );
output c wire inter_sig;
); and2 and2_ins(
assign c = a & b; .a(in1),
endmodule .b(in2),
or2.v .c(inter_sig)
module or2( Step 1 );
input a, or2 or2_ins(
input b, .a(inter_sig),
output c .b(in3),
); .c(out1)
assign c = a | b; );
endmodule endmodule
CENG3430 Lec12: VHDL versus Verilog 31
 Student ID: Date:
Class Exercise 12.4 Name:

• Implement the following circuit in Veirlog:

out1
in1 out2
in2 out3
in3
in4

CENG3430 Lec12: VHDL versus Verilog 32

Design Constructions (1/4)
in1
out1
in2
VHDL: when-else (concurrent, outside process)
architecture arch of ex is
begin
out1 <= '1' when in1 = '1' and in2 = '1' else '0';
end arch ex_arch;

Verilog: assign ? : (concurrent, outside always@ block)

module ex (...);
assign out1 = (in1=='b1 && in2=='b1) ? 'b1 : 'b0;
// 'b: binary; 'o: octal; 'd: decimal; 'h: hexadecimal
endmodule
CENG3430 Lec12: VHDL versus Verilog 34
Design Constructions (2/4)
in1
out1
in2
VHDL: if-then-else Verilog: if-else
(sequential, inside process) (sequential, inside always@)
process(in1, in2) always @(in1, in2)
begin begin
if in1='1' and in2='1' if (in1=='b1 && in2=='b1)
then begin
out1 <= '1'; out1 = 'b1;
else end
out1 <= '0'; else
end if; begin
end process; out1 = 'b0;
end
end
CENG3430 Lec12: VHDL versus Verilog 35
Design Constructions (3/4)
in1
out1
in2
VHDL: case-when Verilog: case
(sequential, inside process) (sequential, inside always@)
process(b) always @(b)
begin begin
case b is case (b)
when "00"|"11" => 'b00 || 'b11:
out1 <= '0'; out1 = 'b0;
out2 <= '1'; out2 = 'b1;
when others => default:
out1 <= '1'; out1 = 'b1;
out2 <= '0'; out2 = 'b0;
end case; endcase
end process; end
CENG3430 Lec12: VHDL versus Verilog 36
Design Constructions (4/4)
in1(3:0) out1(3:0)

VHDL: for-in-to-loop Verilog: for-loop

(sequential, inside process) (sequential, inside always@)
process(in1) always @(in1)
begin begin
for i in 0 to 3 loop for(idx=0; idx<4; idx+=1)
out1(i) <= not in1(i); begin
end loop; out1[idx] = ~in1[idx];
end process; end
end
CENG3430 Lec12: VHDL versus Verilog 37
Outline
• VHDL vs. Verilog
– Background
– Syntax and Popularity
– Operators
– Overall Structure
– External I/O Declaration
– Concurrent Statements
– Sequential Statements
• Edge Detection
– Wire vs. Reg
– Structural Design
– Design Constructions
– Case Study: Flip-flop
CENG3430 Lec12: VHDL versus Verilog 38
Posedge Flip-flop with Sync Reset (1/2)
VHDL Verilog
entity dff is module dff(
port(D,CLK,RESET: input D,
in std_logic; input CLK,
Q: out std_logic); input RESET,
end dff; output reg Q);
architecture dff_arch of always @(posedge CLK)
dff is begin begin
process(CLK) begin
if rising_edge(CLK)then if (RESET) begin
if (RESET = '1') then Q <= 1'b0;
Q <= '0'; end
else else begin
Q <= D; Q <= D;
end if; end
end if;
end process; end
end dff_arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 39
Posedge Flip-flop with Sync Reset (2/2)
Verilog
module dff(  Input must be wire.
input D,  Output could be either wire or reg.
input CLK, • The default option is wire.
input RESET, • But you can specify an output
output reg Q); as wire or reg depending on
always @(posedge CLK) how you will assign it a value.
begin
if (RESET) begin
Q <= 1'b0;
end
else begin
Q <= D;
end

end
endmodule
CENG3430 Lec12: VHDL versus Verilog 40
Posedge Flip-flop with Async Reset (1/2)
VHDL Verilog
entity dff is module dff(
port(D,CLK,RESET: input D,
in std_logic; input CLK,
Q: out std_logic); input RESET,
end dff; output reg Q);
architecture dff_arch of always @(posedge CLK or
dff is begin posedge RESET)
process(CLK,RESET) begin begin
if (RESET = '1') if (RESET) begin
then Q <= 1'b0;
Q <= '0'; end
elsif rising_edge(CLK) else begin
then Q <= D;
Q <= D; end
end if;
end process; end
end dff_arch; endmodule
CENG3430 Lec12: VHDL versus Verilog 41
Posedge Flip-flop with Async Reset (2/2)
Verilog
module dff(
input D,
input CLK,
input RESET,
output reg Q);
always @(posedge CLK or Question: What if we do not
posedge RESET) specify “posedge” for the
begin RESET signal?
if (RESET) begin
Q <= 1'b0; [Synth 8-434] mixed level sensitive
end and edge triggered event controls are
else begin not supported for synthesis!
Q <= D;
end positive level

end positive edge negative edge

endmodule
CENG3430 Lec12: VHDL versus Verilog
negative level negative level 42
Summary
• VHDL vs. Verilog
– Background
– Syntax and Popularity
– Operators
– Overall Structure
– External I/O Declaration
– Concurrent Statements
– Sequential Statements
• Edge Detection
– Wire vs. Reg
– Structural Design
– Design Constructions
– Case Study: Flip-flop
CENG3430 Lec12: VHDL versus Verilog 43