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UNIT-II

Machine Instruction Characteristics: The operation of the processor is determined by the

instructions it executes, referred to as machine instructions or computer instructions. The collection of
different instructions that the processor can execute is referred to as the processor’s instruction set.

Elements of a Machine Instruction: Each instruction must contain the information required by the
processor for execution. These elements are as follows:

• Operation code: Specifies the operation to be performed (e.g., ADD, I/O). The operation
is specified by a binary code, known as the operation code, or opcode.
• Source operand reference: The operation may involve one or more source operands,
that is, operands that are inputs for the operation.
• Result operand reference: The operation may produce a result.
• Next instruction reference: This tells the processor where to fetch the next instruction
after the execution of this instruction is complete.

In most cases, the next instruction to be fetched immediately follows the current instruction.

Instruction Representation: Within the computer, each instruction is represented by a sequence of bits.
The instruction is divided into fields, corresponding to the constituent elements of the instruction. A
simple example of an instruction format is shown in the following figure.

During instruction execution, an instruction is read into an instruction register (IR) in the
processor. The processor must be able to extract the data from the various instruction fields to perform the
required operation.

It is difficult for both the programmer and the reader to deal with binary representations of
machine instructions. To overcome this problem uses symbolic representation of machine instructions as
shown below.

ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory
Instruction Types: Depends on types of operations performed by the instructions, are classified into the
following categories:

• Data processing: Arithmetic and logic instructions. Arithmetic instructions provide

computational capabilities for processing numeric data. Logic (Boolean) instructions operate on
the bits of a word as bits rather than as numbers.
• Data storage: Movement of data into or out of register and or memory locations
• Data movement: I/O instructions
• Control: Test and branch instructions
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Number of Addresses: In general, arithmetic and logic instructions will require the most operands.
Virtually all arithmetic and logic operations are either unary (one source operand) or binary (two source
operands). Thus, we need a maximum of two addresses to reference source operands. The result of an
operation must be stored, suggesting a third address, which defines a destination operand. Finally, after
completion of an instruction, the next instruction must be fetched, and its address is needed. An
instruction could plausibly be required to contain four address references: two source operands, one
destination operand, and the address of the next instruction.
Three-Address Instructions: The program to demonstrate execution of X = (A + B) * (C + D) using
three address instruction is as shown below.
S. No Program instructions
1 ADD Y, A, B
2 ADD Z, C, D
3 MUL X, Y, Z
Two-Address Instructions: The program to demonstrate execution of X = (A + B) * (C + D) using three
address instruction is as shown below.

S. No Program Instructions
1 ADD A, B
2 ADD C, D
3 MUL A,C
4 MOV X, A
One-Address Instructions: The program to demonstrate execution of X = (A + B) * (C + D) using one
address instruction is as shown below.

S. No Program Instructions
1 LOAD A
2 ADD B
3 STORE Y
4 LOAD C
5 ADD D
6 MUL Y
7 STORE X
Zero-Address Instructions: The program to demonstrate execution of X = (A + B) * (C + D) using zero
address instruction is as shown below.
S. No Program Instructions
1 PUSH A
2 PUSH B
3 ADD
4 PUSH C
5 PUSH D
6 ADD
7 MUL
8 POP X
Type of Operands: Each instruction in a program specifies operation to be performed and data to
be processed. An instruction is divided into two parts: operation code (opcode) and its operands. The
operand is another name for data. The most important general categories of data are

• Addresses: The addresses are in fact a form of data. In many situations, some
calculations must be performed on the operand reference in an instruction to determine
the physical address.
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• Numbers: All computers support numeric data types. The common numeric data types
are
 Binary integer or binary fixed point
 Binary floating point
 Decimal
• Characters: A common form of data is text or character strings. Most of the computers
use ASCII code for character.
• Logical data: Most of the processors interpret data as a bit, byte, word or double word.
When data is viewed as n 1-bit items of data, each item having the value 0 or 1, it is
considered as a logical data. With logical data, memory can be used most efficiently.

Types of Operations: The following are different types of operations

1. Data Transfer
2. Arithmetic
3. Logical
4. Conversion
5. Input/output
6. Transfer of Control
1. Data Transfer Operations: The following table represents lists of data transfer
instructions.

Instruction
S. No Symbol Description
Name

1 Push PUSH It is used to insert data onto top of the stack

2 Pop POP It causes to delete top item from the stack

3 Load LOAD It causes transfer of data from given memory location to the processor

4 Store STOR It causes transfer of data from processor to specified memory location.
5 Move MOV It causes transfer of data from source to destination.
6 Exchange XCH It copies the contents of source into the destination.
7 Clear CLEAR Transfer word of 0’s to destination
Considers 1’s in register B and the corresponding bits in register A are
8 Set SET
set to 1

2. Arithmetic Instructions: Arithmetic Instructions performs arithmetic operations like addition,

subtraction, multiplication and division. The following are different types of arithmetic
instructions

Instruction
S. No Symbol Description
Name

1 Addition ADD It adds the value of two operands

2 Subtraction SUB It subtracts the value of two operands
It divides the two operands by considering one as dividend and
3 Division DIV
other as divisor.
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4 Multiplication MUL It multiplies two operands

5 Increment INC Adds 1 to operand

6 Decrement DEC Subtracts 1 from operand

7 Absolute ABS Replace operand by its absolute value (positive rendering value)
8 Negation NEG It simply changes the sign of the given operand value.

3. Logical Instructions: These type of instructions performs logical operations like AND, OR,
NOT, shift and rotate operations on the binary data. The following are different types of logical
and bit manipulation instructions.

i. Logical AND: It performs logical AND operation between the value of two registers.
This instruction compares individual bits of two operands. If any one of the operand bit is
‘0’, the resultant also will be zero. In remaining case the resultant bit will be ‘1’. The
following example demonstrates logical AND operation between two operands.

0101 1010
1001 0010
-------------------

Logical AND 0 0 0 1 0 0 1 0
-------------------

ii. Logical OR: It performs logical OR operation between the value of two registers. This
instruction compares individual bits of two operands. If any one of the operand bit is ‘1’,
the resultant also will be ‘1’. In remaining case the resultant bit will be ‘0’. The following
example demonstrates logical OR operation between two operands.

0101 1010
1001 0010
-------------------

Logical OR 1101 1010

-------------------

iii. Logical NOT: It performs logical NOT operation for the given operand. This instruction
simply complements the given operand. The following example demonstrates logical
NOT operation.
1001 0010
-------------------

Logical NOT 0 1 1 0 1 1 0 1

iv. Logical Exclusive-OR: It performs logical OR operation between the value of two
registers. This instruction compares individual bits of two operands. If one of the operand
bit is ‘1’ and other operand bit is ‘0’, the resultant bit will be ‘1’. In remaining cases,
resultant bit will be ‘0’. The following example demonstrates logical OR operation
between two operands.

0101 1010
1001 0010
-------------------

Logical Exclusive-OR 1100 1000

-------------------
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v. Logical shift: In logical shift micro operation the vacant position created within the
register due to shift operation is filled with zero. There are two logical shift micro
operations: logical shift left (shl) and logical right shift (shr). This can be represented
diagrammatically as shown below.

For example R1 register contains the following data.

0 1 1 0 1 0 1 1
Contents of R1 before shift

Contents of R1 after right shift 1 0 1 1 0 1 0 1

Contents of R1 after left shift 1 1 0 1 0 1 1 0

vi. Arithmetic Shift: There are two arithmetic shifts. Arithmetic Left shift (ashl) is similar
to logical left shift micro operation. In Arithmetic Right shift (ashr), it is necessary to
repeat the leftmost bit for the vacated position. This can be represented diagrammatically
as shown bellow.

Contents of R1 before shift 0 1 1 0 1 0 1 1

Contents of R1 after arithmetic right shift

0 0 1 1 0 1 0 1

Contents of R1 after arithmetic left shift 0 1 0 1 0 1 1 0

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vii. Rotate Shift: The Rotate or Circular Shift circulates the bits of the register around the
two ends without loss of information. Two types of circular shift micro operations are
Circular Left Shift or Left Rotate (cil) and Circular Right Shift or Right Rotate(cir). This
can be represented diagrammatically as shown below.

Contents of R1 before shift 0 1 1 0 1 0 1 1

Contents of R1 after Right Rotate 1 0 1 1 0 1 0 1

Contents of R1 after Left Rotate 1 1 0 1 0 1 1 0

4. Conversion Instruction: This instruction converts the contents of a word from one form to
another. I.e. it converts from decimal number to its equivalent binary form.
5. Input/output Instructions: The following are different types of input/output instructions.

Instruction
S. No Symbol Description
Name
1 Read READ Transfer data from specified I/O port or device to destination
2 Write WRITE Transfer data from specified source to I/O port or device

6. Transfer of Control Instructions: Transfer of Control instructions are used to switch the
control to different locations. The following are different types of Transfer of control
instructions.
Branch instructions: A branch instruction, also called a jump instruction, has the
address of the next instruction to be executed as operand. The instruction is a conditional
branch instruction, if the branch is made only if a certain condition is satisfied. Otherwise,
the next instruction in sequence is executed. A branch instruction in which the branch is
always taken is an unconditional branch. The following are some examples for conditional
branching instructions.

• BRO X: This statement causes branch to specified location ‘X’, if overflow occurs.
• BRN X: This statement causes branch to specified location ‘X’, if result is negative.
• BRZ X: This statement causes branch to specified location ‘X’, if the result is zero.
• BRP X: This statement causes branch to specified location ‘X’, if the result is positive.
• BRE R1, R2, X: This statement causes branch to specified location ‘X’, if the contents of
register R1 equals to the contents of register R2.

The following example shows how an unconditional and a conditional branch can be
used to create a repeating loop of instructions.
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The instructions in locations 202 through 210 will be executed repeatedly until
the result of subtracting Y from X is 0.

 Skip Instructions: Another form of transfer-of-control instruction is the skip

instruction. The skip implies that one instruction to be skipped; thus, the required address
equals the address of the next instruction plus one. A typical example is the increment-
and-skip-if-zero (ISZ) instruction. Consider the following program

In the above program, the two transfer-of-control instructions are used to

implement an iterative loop. Assume R1 contains a negative number. At the end of the
loop, R1 is incremented. If it is not 0, the program branches back to the beginning of the
loop. Otherwise, the branch is skipped, and the program continues with the next
instruction after the end of the loop.

Procedure Call Instructions: A procedure is a self-contained computer program that

is incorporated into a larger program. At any point in the program the procedure may be
called. The processor is instructed to go and execute the entire procedure and then return
to the point from which the call took place. The two principal reasons for the use of
procedures are economy and modularity. A procedure allows the same piece of code to
be used many times.
The procedure mechanism involves two basic instructions: a call instruction that
branches from the present location to the procedure, and a return instruction that returns
from the procedure to the place from which it was called.
The following diagram explains the use of procedures to construct a program. In
this example, there is a main program starting at location 4000.This program includes a
call to procedure PROC1, starting at location 4500.When this call instruction is
encountered, the processor suspends execution of the main program and begins execution
of PROC1 by fetching the next instruction from location 4500.Within PROC1, there are
two calls to PROC2 at location 4800. In each case, the execution of PROC1 is suspended
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and PROC2 is executed. The RETURN statement causes the processor to go back to
the calling program and continue execution at the instruction after the corresponding
CALL instruction.

Addressing Modes: The operation field of an instruction specifies the operation to be performed.
This operation must be executed on some data stored in computer registers or memory words. The way
the operands are chosen during program execution is dependent on the addressing mode of the instruction.
The following arte different types of addressing modes:
1. Immediate addressing mode
2. Direct addressing mode
3. Indirect addressing mode
4. Register addressing mode
5. Register indirect addressing mode
6. Displacement addressing mode
7. Stack addressing mode

1. Immediate Addressing: This is the simplest form of addressing. Here, the operand is given in
the instruction itself. This mode is used to define constant or set initial values of variables. The
advantage of this mode is that no memory reference other than instruction fetch is required to
obtain operand. General format is as shown below:

Opcode Immediate Operand

For example,

ADD R1, #3 R1  R1 + 3

In the above example, Immediate Operand is #3 which is added to contents of R1 and the
result is stored back into R1 register.
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2. Direct Addressing Mode: A very simple form of addressing is direct addressing, in which the
address field contains the effective address of the operand. It requires only one memory reference
and no special calculation. General format is as shown below:

Opcode Operand Address(1001)

Operand Data 1001

Main Memory

For example, ADD R1, (1001) R1  R1 + M [1001]

In this example, contents of register R1 and data present at address 1001 in memory are
added and result is stored back into register R1

3. Indirect addressing mode: In this addressing mode, the address field of the instruction refers to
the address of a word in memory, which in turn contains the full length address of the operand.
The advantage of this mode is that for the word length of N, an address space of 2N can be
addressed. The disadvantage is that instruction execution requires two memory references to fetch
the operand. Instruction format with indirect memory addressing mode is as shown below.
Opcode Operand Address(1000)

2468
100 0

Operand Data 2468

4. Register addressing mode: Register addressing mode is similar to direct addressing. The only
difference is that the address field of the instruction refers to a register rather than a memory
location and 3 to 5 bits are used as address field to reference 8 to 32 generate purpose registers.
The advantages of register addressing are Small address field is needed in the instruction.
Instruction format for Register addressing mode is as shown below.

Opcode Register Operand

R0

R1 Operand Register Stack

R2

5. Register indirect addressing mode: This mode is similar to indirect addressing. The address
field of the instruction refers to a register. The register contains the effective address of the
operand. This mode uses one memory reference to obtain the operand. Instruction format for
Register Indirect addressing mode is as shown below.
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Opcode Register Operand

R0

R1 Register Stack
Memory

R2 Address
of
Operand Data
Operand

6. Displacement addressing mode: In displacement addressing mode there are 3 types of

addressing modes. They are as shown below:
o Relative addressing Mode: In this addressing mode, the instruction contains a relative
address which is to be added to the contents of program counter to get the effective
address.

Effective Address = (PC ) + Address specified in the instruction

Instruction format with Relative addressing mode is as shown below.

Opcode Operand Address

+ Operand Data
PC

Data

o Base Register addressing mode: In this addressing mode, the instruction contains an
address which is to be added to the data present in the basic register to get the effective
address. Thus,

Effective Address = BR + Address specified in the instruction

Instruction format with Base register addressing mode is as shown below.
Opcode Operand Address

BR + Operand Data

Data
o Indexing addressing: In this addressing mode, the instruction contains an address which
is to be added to the data present in the indexed register to get the effective address. Thus,
Effective Address = IR + Address Specified in the instruction
Instruction format with Base register addressing mode is as shown below.
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Opcode Operand Address

+ Operand Data
IR

Data

7. Stack Addressing Mode: The stack is a reserved block of locations. Items are appended to the
top of the stack so that, at any given time, the block is partially filled. The stack mode of
addressing is a form of implied addressing. The machine instructions need not include a memory
reference but implicitly operate on the top of the stack.

Instruction Formats: An instruction format defines the layout of the bits of an instruction. An
instruction format must include an opcode and, implicitly or explicitly, zero or more operands. Each
explicit operand is referenced using one of the addressing modes.
Fixed Length Instructions:
PDP-8: One of the simplest instruction designs for a general-purpose computer was for the PDP-
8 [BELL78b].The PDP-8 uses 12-bit instructions and operates on12-bit words. There is a single
general-purpose register, the accumulator.

The above figure shows the PDP-8 instruction format. There are a 3-bit opcode and three
types of instructions. For op codes 0 through 5, the format is a single-address memory reference
instruction including a page bit and an indirect bit. Thus, there are only six basic operations.
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PDP-10: The PDP-10 was designed to be a large-scale time-shared system. The PDP-10 has a
36-bit word length and a 36-bit instruction length. The fixed instruction format is shown below.
The opcode occupies 9 bits, allowing up to512 operations. In fact, a total of 365 different
instructions are defined. Most instructions have two addresses, one of which is one of 16 general-
purpose registers. The other operand reference starts with an18-bit memory address field.

Variable Length Instructions:

PDP-11: The PDP-11 was designed to provide a powerful and flexible instruction set within the
constraints of a 16-bit minicomputer.
The PDP-11 employs a set of eight 16-bit general-purpose registers. Two of these
registers have additional significance: one is used as a stack pointer for special-purpose stack
operations, and one is used as the program counter, which contains the address of the next
instruction.
The following figure shows the PDP-11 instruction formats. Thirteen different formats
are used, encompassing zero, one, and two-address instruction types. The op code can vary from
4 to 16 bits in length. Register references are 6 bits in length. Three bits identify the register, and
the remaining 3 bits identify the addressing mode.
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Assembly Language: Assembly language is a programming language that is one step away from
machine language. To overcome the complexities in Machine Language, an assembly language is
developed by IBM in 1950. Assembly languages are programming languages that use symbolic notation
to represent machine language instructions. The general format of assembly language instruction is as
shown below.

L2: SUB R1, R2 ; subtract contents of register R2 from

; Contents of R1 and store result in R1
JG L2 ; jump to L2 if result of subtraction is; positive

Here, Label is the symbolic name used to point the instruction. Instruction consists of opcode and
operand. If multiple operands are to be specified, their locations are separated by comma. The text written
after semicolon is the comment which is non-executable, which increases the readability of a program.
Advantages:
• Easy to understand
• Easy to remember
• Easy to read
• Easy to use
• Debugging is easy
• Assembly language programs occupies less space in memory
Disadvantages:
• Machine dependent
• Hard to learn
• Execution time of assembly language program is more than machine language program

Processor Organization: Every Processor performs the following:

• Fetch instruction: The processor reads an instruction from memory (register, cache, main
memory).
• Interpret instruction: The instruction is decoded to determine what action is required.
• Fetch data: The execution of an instruction may require reading data from memory or an I/O
module.
• Process data: The execution of an instruction may require performing some arithmetic or logical
operation on data.
• Write data: The results of an execution may require writing data to memory or an I/O module.

To do these things, the processor needs to store some data temporarily. It must remember the
location of the last instruction so that it can know where to get the next instruction. It needs to store
instructions and data temporarily while an instruction is being executed. In other words, the processor
needs a small internal memory.
The following figure is a simplified view of a processor, indicating its connection to the rest of
the system via the system bus. The ALU does the actual computation or processing of data. The
control unit controls the movement of data and instructions into and out of the processor and controls
the operation of the ALU and consisting of a set of storage locations, called registers.
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The following figure is a slightly more detailed view of the processor. The data transfer and logic
control paths are indicated, including an element labeled internal processor bus. This element is
needed to transfer data between the various registers and the ALU.

Register Organization: The registers in the processor perform two roles:

• User-Visible Registers: Enable the machine- or assembly language programmer to minimize
main memory references by optimizing use of registers. Different types of User-visible registers
are as follows:
1. General purpose Registers: General-purpose registers can be assigned to a variety of
functions by the programmer. General-purpose register can contain the operand for any
opcode. In some cases, general-purpose registers can be used for addressing functions.
2. Data Registers: Data registers may be used only to hold data and cannot be employed in
the calculation of an operand address.
3. Address Registers: Address Registers contain address of the operands. Examples
include the following:
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a. Segment pointers: A segment register holds the address of the base of the
segment.
b. Index registers: These are used for indexed addressing and may be auto indexed.
c. Stack pointer: This allows implicit addressing; that is, push, pop, and other stack
instructions need not contain an explicit stack operand.
4. Condition codes: Condition codes are bits set by the processor hardware as the result of
operations. For example, an arithmetic operation may produce a positive, negative, zero,
or overflow result. In addition to the result it-self being stored in a register or memory, a
condition code is also set.

• Control and status registers: Used by the control unit to control the operation of the processor
and by privileged, operating system programs to control the execution of programs. The
following are different types of control and status registers.
1. Program counter (PC): Contains the address of an instruction to be fetched.
2. Instruction register (IR): Contains the instruction most recently fetched. (Currently
executing instruction)
3. Memory address registers (MAR): Contains the address of a location in memory.
4. Memory buffer register (MBR): Contains a word of data to be written to memory or the
word most recently read

Instruction Cycle: Instruction cycle includes the following stages:

• Fetch: Read the next instruction from memory into the processor.
• Execute: Interpret the opcode and perform the indicated operation.
• Interrupt: If interrupts are enabled and an interrupt has occurred, save the current process state
and service the interrupt.

The Indirect Cycle: The execution of an instruction may involve one or more operands in
memory, each of which requires a memory access. Further, if indirect addressing is used, then
additional memory accesses are required as shown in the above diagram.
After an instruction is fetched, it is examined to determine if any indirect addressing is
involved. If so, the required operands are fetched using indirect addressing. Following execution,
an interrupt may be processed before the next instruction fetch. The following diagram
represents instruction cycle with interrupts.
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Data Flow: During the fetch cycle, an instruction is read from memory. The following figure
shows the flow of data during this cycle. The PC contains the address of the next instruction to be
fetched. This address is moved to the MAR and placed on the address bus.
The control unit requests a memory read, and the result is placed on the data bus and
copied into the MBR and then moved to the IR. Meanwhile, the PC is incremented by 1,
preparatory for the next fetch. Once the fetch cycle is over, the control unit examines the contents
of the IR to determine if it contains an operand specifies using indirect addressing. If so, an
indirect cycle is performed.

Data Flow, Fetch Cycle

Indirect Cycle is a simple cycle. The right-most N bits of the MBR, which contain the
address reference, are transferred to the MAR. Then the control unit requests a memory read, to
get the desired address of the operand into the MBR.
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The fetch and indirect cycles are simple and predictable. The execute cycle takes many
forms; the form depends on which of the various machine instructions is in the IR. This cycle
may involve transferring data among registers, read or write from memory or I/O, and/or the
invocation of the ALU.
Like the fetch and indirect cycles, the interrupt cycle is simple and predictable. The
current contents of the PC must be saved so that the processor can resume normal activity after
the interrupt. Thus, the contents of the PC are transferred to the MBR to be written into memory.
The special memory location reserved for this purpose is loaded into the MAR from the control
unit.

Data Flow, Interrupt Cycle

Instruction Pipelining: Greater performance can be achieved by taking advantage of

improvements in technology, such as faster circuitry and by using multiple registers rather than a single
register, and the use of a cache memory. Another organizational approach, which is instruction
pipelining.
The process of executing more than one instruction at a time is called as pipelining. Consider
two-stage instruction pipelining as shown below. Here instruction processing is subdivided into two
stages: fetch instruction and execute instruction. The pipeline has two independent stages. The first stage
fetches an instruction and buffers it. When the second stage is free, the first stage passes it the buffered
instruction. While the second stage is executing the instruction, the first stage takes advantage of any
unused memory cycles to fetch and buffer the next instruction. This is called instruction pre fetch or
fetches overlap. In general, pipelining requires registers to store data between stages.
If the fetch and execute stages were of equal duration, the instruction cycle time would be
decreased. In general,
• The execution time will generally be longer than the fetch time. Execution will involve reading
and storing operands and the performance of some operation. Thus, the fetch stage may have to
wait for some time before transmitting data to execute stage.
• A conditional branch instruction makes the address of the next instruction to be fetched unknown.
Thus, the fetch stage must wait until it receives the next instruction address from the execute
stage. The execute stage may then have to wait while the next instruction is fetched.
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(a) Simplified view

(b) Expanded view

Six Stage Instruction Pipelining: Consider the following decomposition of the instruction
processing.
• Fetch instruction (FI): Read the next expected instruction into a buffer.
• Decode instruction (DI): Determine the opcode and the operand specifies.
• Calculate operands (CO): Calculate the effective address of each source operand. This may
involve displacement; register indirect, indirect, or other forms of address calculation.
• Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be
fetched.
• Execute instruction (EI): Perform the indicated operation and store the result, if any, in the
specified destination operand location.
• Write operand (WO): Store the result in memory.

Let all stages required equal duration. Using this assumption, the following figure shows that a six-
stage pipeline can reduce the execution time for 9instructions from 54 time units to 14 time units.
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Several factors limit the performance enhancement. If the six stages are not of equal duration,
there will be some waiting involved at various pipeline stages. Another difficulty is the conditional
branch instruction, which can invalidate several instruction fetches. A similar unpredictable event is an
interrupt.

The following figure illustrates the effects of the conditional branch. Assume that instruction 3
is a conditional branch to instruction 15. Until the instruction is executed, there is no way of knowing
which instruction will come next (not determined until the end of time unit 7). At this point, the pipeline
must be cleared of instructions that are not useful. During time unit 8, instruction 15 enters the pipeline.
No instructions completed during time units 9 through 12; this is the branch penalty.

The following figure represents the flowchart for Six-Stage CPU Instruction Pipeline.
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Pipeline Hazards: A pipeline hazard occurs when the pipeline, or some portion of the pipeline,
must stall because conditions do not permit continued execution. Such a pipeline stall is also referred to as
a pipeline bubble. There are three types of hazards: resource, data, and control.

Resource Hazards: A resource hazard occurs when two (or more) instructions that are already in the
pipeline need the same resource. A resource hazard is sometime referred to as a structural hazard.

Let us consider a simple example of a resource hazard. Assume a simplified five-stage pipeline,
in which each stage takes one clock cycle. Now assume that main memory has a single port and that all
instruction fetches and data reads and writes must be performed one at a time as shown below.
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Data Hazards: A data hazard occurs when there is a conflict in the access of an operand location. For
example, two instructions in a program are to be executed in sequence and both access a particular
memory or register operand. If the two instructions are executed in strict sequence, no problem occurs.
However, if the instructions are executed in a pipeline, then it is possible for the operand value to be
updated in such a way as to produce a different result.
For example, consider the following x 86 machine instruction sequences:
ADD R1, R2
SUB R1, R3
The first instruction adds the contents of registers R1 and R2 and stores the result in R1. The
second instruction subtracts the contents of R3 from R1 and stores the result in R1. The following figure
shows the pipeline behavior. The ADD instruction does not update register R1 until the end of stage 5,
which occurs at clock cycle 5. But the SUB instruction needs that value at the beginning of its stage 2,
which occurs at clock cycle 4. To maintain correct operation, the pipeline must stall for two clocks cycles.

There are three types of data hazards:

• Read after write (RAW), or true dependency: An instruction modifies a register or
memory location and a succeeding instruction reads the data in that memory or register
location. A hazard occurs if the read takes place before the write operation is complete.
• Write after read (RAW), or antidependency: An instruction reads a register or
memory location and a succeeding instruction writes to the location. A hazard occurs if
the write operation completes before the read operation takes place.
• Write after write (RAW), or output dependency: Two instructions both write to the
same location. A hazard occurs if the write operations take place in the reverse order of
the intended sequence.

Control Hazards: A control hazard, also known as a branch hazard, occurs when the pipeline makes the
wrong decision on a branch prediction.
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Dealing with Branches: One of the major problems in designing an instruction pipeline is conditional
branch instruction. Until the instruction is actually executed, it is impossible to determine whether the
branch will be taken or not. A variety of approaches have been taken for dealing with conditional
branches:
• Multiple streams
• Pre fetch branch target
• Loop buffer
• Branch prediction
• Delayed branch
• Multiple Streams: A simple pipeline suffers a penalty for a branch instruction be-cause it must
choose one of two instructions to fetch next and may make the wrong choice. A brute-force
approach is to replicate the initial portions of the pipeline and allow the pipeline to fetch both
instructions, making use of two streams.
There are two problems with this approach:
o With multiple pipelines there are contention delays for access to the registers and
to memory.
o Additional branch instructions may enter the pipeline (either stream) before the
original branch decision is resolved. Each such instruction needs an additional
stream.
• Pre fetch Branch Target: When a conditional branch is recognized, the target of the branch is
pre fetched, in addition to the instruction following the branch. This target is then saved until the
branch instruction is executed. If the branch is taken, the target has already been pre fetched.
• Loop Buffer: A loop buffer is a small, very high speed memory maintained by the instruction
fetches stage of the pipeline and containing the n most recently fetched instructions, in sequence.
If a branch is to be taken, the hardware first checks whether the branch target is within the buffer.
If so, the next instruction is fetched from the buffer.
• Branch Prediction: Various techniques can be used to predict whether a branch will be taken.
Among the more common are the following:
o Predict never taken
o Predict always taken
o Predict by opcode
o Taken/not taken switch
o Branch history table
The first three approaches are static: they do not depend on the execution history up to
the time of the conditional branch instruction. The next two approaches are dynamic: They
depend on the execution history.
The first two approaches are the simplest. These either always assume that the branch
will not be taken or continue to fetch instructions in sequence, or they always assume that the
branch will be taken and always fetch from the branch tar-get.
The final static approach makes the decision based on the opcode of the branch
instruction. The processor assumes that the branch will be taken for certain branch opcodes
and not for others.
Dynamic branch strategies attempt to improve the accuracy of prediction by recording the
history of conditional branch instructions in a program.
In Taken/not taken switch system, a tag bit is included to each instruction, which contains
either 1 or 0. 1 indicates branch to be taken and 0 indicates no branch.
Branch history table is a small cache memory. Each record in the table contains three
fields: address of the instruction, history bits, and address of the target branch.

• Delayed Branch: It is possible to improve pipeline performance by automatically rearranging

instructions within a program, so that branch instructions occur later than actually desired.
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Frequently asked Questions

1. Briefly explain about Machine Instructions Characteristics?

2. What types of operands are typical in machine instruction sets?
3. Describe various arithmetic and logic instructions set operations?
4. Explain about various logic and shift micro operations?
5. List some data transfer instructions and explain with example?
6. Briefly explain about program control transfer instructions? Or Discuss Program control
instruction in detail?
7. Explain in detail about various addressing modes with examples?
8. Explain different Instruction Formats?
9. Write short note on Assembly Level language?
10. Write short note on Processor Organization and Register organization?
11. What is Instruction Cycle? (Or)
Draw and explain about the instructions cycle state diagram? (Or)
List various states of an instruction cycle? (Or)
Describe an instruction execution using a state diagram?
12. What is pipeline? Give detailed picture of Pipeline? (Or)
What is pipeline? Explain pipeline process with an example?
Discuss about flow of instruction execution unit pipelined processor?
13. What is meant by Instruction Pipelining? Explain about four segment pipelining?
14. Highlight on the problems in operating instruction pipelining?
15. Draw a space time diagram for six segment pipeline showing the time it takes to process eight
tasks?
16. Formulate a six segment instruction pipeline for a computer. Specify the operations to be
performed in each segment?
17. Explain four possible hardware schemes that can be used in an instruction pipeline in order to
minimize the performance degradation caused by instruction branching?