Coimbatore-641 107

DEPARTMENT OF COMPUTER SCIENCE AND

ENGINEERING

LAB MANUAL

(CS3351) -DIGITAL SYSTEMS LABORATORY

(Regulation 2021)

SEMESTER-III
Academic Year 2023-2024

Prepared by Verified By
Mrs.P.Kowsalya, AP/ECE HOD/ECE
 SYLLABUS

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using
basic gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters.
8. Design and implement Shift-Registers.
9. Simulator based study of Computer Architecture.
 INDEX

Mark
S. Signat
Date Experiment Name Obse
No Rec Viva ure
rvati
ord voce
on
.COM V+ TEAM

Average Mark :
EXP.NO.:1a STUDY OF LOGIC GATES
DATE:

AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
functions. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the
inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs
are high.
. NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:
SYMBOL: PIN DIAGRAM:

X-OR GATE :
SYMBOL : PIN DIAGRAM :

WWW.VIDYARTHIPLUS.COM V+ TEAM
2-INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:

Result:

Thus the Logic Gates are verified using Integrated Circuits.

EXPT NO.:1b VERIFICATION OF BOOLEAN THEOREMS
DATE: USING DIGITAL LOGIC GATES

AIM:
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

BOOLEAN THEOREM:
Theorem : 1. x + x = x ; x . x = x
2. x + 1 = 1 ; x . 0 = 0
3. (x’)’ = x ( Involution )
4. Associative x + (y + z) = (x + y) + z
x . (y . z) = (x . y) . z
5. De Morgan’s (x + y)’ = x’ . y’
(x . y)’ = x’ + y’
6. Absorption x + x.y = x
x . (x + y) = x
Truth Table
 WWW.VIDYARTHIPLUS.COM

M
 WWW.VIDYARTHIPLUS.COM

THEOREM: 5 DE-MORGAN’S LAW:

(i) X . Y = (X+Y))

WWW
 WWW.VIDYARTHIPLUS.COM

PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Give the logical inputs as per the truth table.
3. The corresponding output is verified with their truth table.

RESULT:
Thus the Boolean Theorems are verified by using Logic gates.
EXPT NO: 2 DESIGN OF ADDER AND SUBTRACTOR
DATE:

AIM:

To design and construct half adder, full adder, half subtractor and full

subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum
‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a
carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from
the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half
adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be
taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.
LOGIC DIAGRAM

HALF ADDER:

TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

+ B CARRY = AB
S=A B
LOGIC DIAGRM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER:

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

K-Map for CARRY:

LOGIC DIAGRAM:
HALF SUBTRACTER

TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

LOGIC DIAGRAM:
FULL SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

K-Map for Borrow:

PROCEEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

RESULT:
Thus the Half/Full Adder And Subtractor is implemented and designed.
EXPT NO.: 3 DESIGN OF 4-BIT ADDER /SUBTRACTOR
DATE:

AIM:
To design and implement 4-bit adder/ subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:
4- BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are connected
in chain through the full adder. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.
4 -BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing subtraction.
4 -BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit
is adder circuit. When M=1, it becomes subtractor.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.
PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4 – bit binary adder / subtractor is implemented and designed.

EXPT NO.:4 DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
DATE:

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is
a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the
input lines must supply the bit combination of elements as specified by code and the
output lines generate the corresponding bit combination of code. Each one of the four
maps represents one of the four outputs of the circuit as a function of the four input
variables. A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic diagram
that implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

V+ TEAM
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

G3 = B 3
K-Map for G2:
K-Map for G1:

K-Map for G0:

TRUTH TABLE:
| Binary input | Gray code output
|

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
V+ TEAM
 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

M
TRUTH TABLE:
| Gray Code | Binary Code
|
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

WWW.VIDYARTHIPLUS.COM V+ TEAM
 WWW.VIDYARTHIPLUS.COM

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

WWW.VIDYARTHIPLUS.COM V+ TEAM
 WWW.VIDYARTHIPLUS.COM

K-Map for E0:

TRUTH TABLE:
| BCD input | Excess – 3 output
|
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

WWW.VIDYARTHIPLUS.COM V+ TEAM
 WWW.VIDYARTHIPLUS.COM

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

WWW.VIDYARTHIPLUS.COM V+ TEAM
 WWW.VIDYARTHIPLUS.COM

K-Map for B:

K-Map for C:

K-Map for D:

WWW.VIDYARTHIPLUS.COM V+ TEAM
 WWW.VIDYARTHIPLUS.COM

TRUTH TABLE:

| Excess – 3 Input BCD Output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:
Thus the following code converters are designed and implemented

 Binary to Gray Code Converter

 Gray to Binary Code Converter
 BCD to Excess-3 Code Converter
 Excess-3 to BCD Code Converter
EXP.NO.5a DESIGN OF BCD ADDER

DATE:

AIM:

To design and implement BCD adder using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 2

2. OR GATE IC 7432 1

3. AND GATE IC 7408 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 40

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater
than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented
in BCD and should appear in the form listed in the columns.

A BCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
LOGIC DIAGRAM:
BCD ADDER

K MAP

Y = S4 (S3 + S2)
TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the BCD adder using IC7483 is implemented and designed.

EXP.NO.5b. DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

DATE:

AIM:

To design and implement encoder and decoder using logic gates and study of IC 7445 and IC
74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2

2. OR GATE IC 7432 3

3. NOT GATE IC 7404 1

2. IC TRAINER KIT - 1

3. PATCH CORDS - 27

THEORY:

ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has
2n input lines and n output lines. In encoder the output lines generates the binary code corresponding
to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is assumed that only one input has
a value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when
all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER

TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1
DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits
than the output code. Each input code word produces a different output code word i.e there is one to
one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2 n possible outputs. 2n output values are from 0 through
out 2n – 1.

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:
 INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the encoder and decoder using logic gates are designed and implemented.

EXP NO.:6 DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

 DEMULTIPLEXER
DATE :

AIM:
To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

WWW.VIDYARTHIPLUS.COM V+ TEAM
TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

RESULT:
Thus the Multiplexer and Demultiplexer using logic gates is designed and
implemented.
EXPT NO. :7 DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER

DATE :

AIM:

To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down counter
is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter follows
reverse sequence.
K MAP

WWW.VIDYARTHIPLUS.COM V+ TEAM

STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LOGIC DIAGRAM:

TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

WW.VIDYARTHIPLUS.COM V+ TEAM
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the 3 bit synchronous up/down counter is designed and implemented.
EXPT NO.:8 DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS
DATE:

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

WWW.VIDY
1 1 0 ARTHIPLUS.COM V+ TEAM
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

RTHIPLUS.COM
V+ TEAM
 WWW.VIDYARTHIPLUS.COM

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

WWW.VIDYARTHIPLUS.COM V+ TEAM
WWW.VIDYARTHIPLUS.CO

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the shift registers are designed and implemented.
EXPT NO. :9 IMPLEMENTATION OF PRBS GENERATORS AND
DATE : ACCUMULATOR. TEST BENCH CREATION AND
FUNCTIONAL VERIFICATION

AIM:

To write a code and to implement PRBS Generators and Accumulators.

TOOLS REQUIRED:

Xilinix ISE 9.1, ModelSim SE 6.0

PROCEDURE:

a) Open file menu from sub menu. Click open

b) Enter the project name and select HDL.

c) Select the device family.

e) Create a new source and enter HDL file name and also the module name.

f) Enter the input and the output variables.

g) Enter the coding in the program window and also save the program

h) Run the model sim simulator and enter the inputs.

i) Obtain the corresponding output waveforms.

PROGRAM (PRBS Generators )

module prbs(a,clk,clr);

output [3:0] a;

input clk,clr;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if(clr)

begin
tmp = 4'b1111;

end

else

begin

tmp = { tmp[0]^tmp[1],tmp[3],tmp[2],tmp[1]};

end

end

assign a=tmp;

endmodule

TEST BENCH (PRBS)

module main;
reg clk, reset;
wire rand;
prbs pr (rand, clk, reset);

initial
begin
forever
begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
endmodule

PROGRAM (Accumulator )

module accumod (in, acc, clk, reset);

input [7:0] in;

input clk, reset;

output [7:0] acc;

reg [7:0] acc;

always@(clk) begin

if(reset)

acc <= 8′b00000000;

else

acc <= acc + in;

end

endmodule

TEST BENCH (Accumulator)

module accumt_b;

reg [7:0] in;

reg clk;

reg reset;

wire [7:0] acc;

accumod uut ( .in(in), .acc(acc),.clk(clk),.reset(reset) );

initial begin
#5 reset<=1′b1;

#5 reset<=1′b0;

clk =1′b0;

in = 8′b00000001;

#50 in = 8′b00000010;

#50 in = 8′b00000011;

end

always #10 clk = ~clk;

initial#180 $stop;

endmodule
Simulated Waveform for PRBS generator:

Simulated Waveform for Accumulator

RESULT:

Thus the implementation of PRBS generators and accumulator test bench creation and its
functions are verified.