Introduction to Synthesis

HDL
Design

HDL Constraints

Provided by
Standard Custom Block
Simulation
Cell Designers
Synthesis Library
Macros
(ROM RAM PLA
& uP Core)
Gate Level
Netlist

Simulation Place
and
Route

Full Chip
Parasitic Layout
Gate Level Extraction
Netlist
Simulation
Sign−Off

1001
Introduction to Synthesis

HDL
Design

HDL Constraints

Provided by
Standard Custom Block
Simulation
Cell Designers
Synthesis Library
Macros
(ROM RAM PLA
& uP Core)
Gate Level
Netlist

Simulation Place
and
Route

Full Chip
Parasitic Layout
Gate Level Extraction
Netlist
Simulation
Sign−Off

1002
Introduction to Synthesis

HDL Constraints

Standard
Cell
Synthesis Library

Gate Level
Netlist

• HDL (Hardware Description Language)

SystemVerilog file (.sv)
• Constraints
Synopsys Design Constraints file (.sdc)
• Standard Cell Library
Liberty file (.lib)

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Introduction to Synthesis

Timing Related Constraints

• Clock Constraints

• Input Constraints

• Output Constraints

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Introduction to Synthesis

Timing Related Constraints

• Clock Constraints

What the synthesis tool needs to know about the clock

• Input Constraints

• Output Constraints

1004
Introduction to Synthesis

Timing Related Constraints

• Clock Constraints

What the synthesis tool needs to know about the clock

• Input Constraints

What the synthesis tool needs to know about the inputs

• Output Constraints

1004
Introduction to Synthesis

Timing Related Constraints

• Clock Constraints

What the synthesis tool needs to know about the clock

• Input Constraints

What the synthesis tool needs to know about the inputs

• Output Constraints

What the synthesis tool needs to know about the outputs

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Introduction to Synthesis

Clock Constraints
Period
Ideal Clock

Latency

Transition

Uncertainty

t=0

• Specify Clock Perid

create clock -period period value -name clock name clock port

• Model Clock Tree uncertainty = skew + jitter

set clock latency delay clock object
set clock transition transition clock object
set clock uncertainty uncertainty clock object

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Introduction to Synthesis

Input Constraints
Reference
Ideal Clock

Minimum Input Delay

Maximim Input Delay

t=0

• Specify Input Delay

set input delay max value -max -clock clock name port pin list

set input delay min value -min -clock clock name port pin list

With a longer input delay, our circuit has less time to respond before the next clock edge.

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Introduction to Synthesis

Output Constraints
Reference
Ideal Clock

Minimum Output Delay

Maximim Output Delay

t=0

• Specify Output Delay

set output delay max value -max -clock clock name port pin list
set output delay min value -min -clock clock name port pin list
With a longer output delay, our circuit has to produce an output earlier in the clock cycle.

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Introduction to Synthesis

Synthesis constraints (1)

• Specify Clock Frequency
create_clock -period 20 -name master_clock [get_ports Clock]

• Model Clock Tree uncertainty = skew + jitter

set_clock_latency 2.5 [get_clocks master_clock]
set_clock_transition 0.5 [get_clocks master_clock]
set_clock_uncertainty 1.0 [get_clocks master_clock]

• Specify Input and Output Timing

set_output_delay 2.0 -max -network_latency_included -clock master_clock \
[all_outputs]
set_output_delay 0.1 -min -network_latency_included -clock master_clock \
[all_outputs]

set_input_delay 2.0 -max -network_latency_included -clock master_clock \

[remove_from_collection [all_inputs] [get_ports Clock]]
set_input_delay 0.1 -min -network_latency_included -clock master_clock \
[remove_from_collection [all_inputs] [get_ports Clock]]

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Introduction to Synthesis

Synthesis constraints (2)

• Specify Input Drive and Output Load

set_load 1.0 -max [all_outputs]
set_load 0.01 -min [all_outputs]

set_driving_cell -max -library c35_IOLIB_WC -lib_cell BU24P -pin PAD [all_inputs]

set_driving_cell -min -library c35_IOLIB_WC -lib_cell BU1P -pin PAD [all_inputs]

• Specify Timing Exclusions

set_ideal_network [get_ports nReset]

• Other constraints
set_max_area 0

1009