Computer Architecture

Chapter: 1
1-Architecture: is those attributes of a system visible to the programmer, direct
impact on the logical execution of a program.
‫ هي سمات النظام المرئي ل مبرمج تأثيرمباشر على التنفيذ المنطفى ل برنامج‬:‫الهندسة المعمارية‬

Architectural attributes include: Instruction set, number of bits, I/O mechanisms,

addressing techniques.
‫ معالجة‬، ‫ اإلخراج‬/ ‫ آليات اإلدخال‬، ‫ وعدد بت‬، ‫ مجموعة التعليمات‬:‫تشمل السمات المعمارية‬
‫التقنيات‬
2-Organization: is the operational units and their interconnections that realize the
architectural specifications Organizational
‫هو الوحدات التشغيلية وترابطها التى تحقق المواصفات المعماريى‬:‫التنظيم‬
attributes include: Control signals, interfaces between the computer and
peripherals, memory technology
‫ تكنولوجيا الذاكرة‬، ‫ إشارات التحكم والواجهات بين الكمبيوتر واألجهزة الطرفية‬:‫تشمل السمات التنظيمية‬
3-Structure: is the way in which components relate to each other
‫ هو الطريقة التي ترتبط بها المكونات ببعضها البعض‬:‫الهيكل‬
4-Function: is the operation of each individual component as part of the structure
‫ هى تشغيل كل مكون على حدة كجزء من الهيكل‬:‫الوظيفة‬
5-short-term:is temporarily store at least those pieces of data that are being
worked on at any given
‫يتم تخزين مؤقتا على األقل تلك األجزاء من البيانات التي يتم العمل عليها في اى معطى‬
6-long-term: function, Files of data are stored on the computer for subsequent
retrieval and update. ‫تخزين البيانات على المدى الطويل وظيفة يتم تخزين ملفات البيانات على‬
‫الكمبيوتر لاللحقة االسترجاع و التحديث‬
7. List and briefly define the main structural components of a computer.
• Central Processing Unit (CPU): Controls the operation of the computer and
performs its data processing functions. Often referred to as processor.
• Main Memory: Stores data.
• I/O: Moves data between the computer and its external environment.
• System Interconnection: Some mechanism that provides communication among
CPU, main memory, and I/O.
5. List and briefly define the main structural components of a processor (CPU).
• Control Unit: Controls the operation of the CPU and hence the computer.
• Arithmetic and Logic Unit (ALU): Performs the computer's data processing
functions.
• Registers: Provides storage internal to the CPU.
• CPU Interconnection: Some mechanisms that provide communication among
the control unit, ALU, and registers.

Chapter: 2
1. Describe the Registers of IAS
1. Memory Buffer Register (MBR): Holds a word to be stored in
memory, sent to the I/O unit, or receives a word from memory or I/O.
2. Memory Address Register (MAR): Specifies the memory address of
the word to be read into or written from the MBR.
3. Instruction Register (IR): Contains the 8-bit opcode instruction
currently being executed.
4. Instruction Buffer Register (IBR): Temporarily holds the righthand
instruction from a word in memory.
5. Program Counter (PC): Holds the address of the next instruction pair
to be fetched from memory.
6. Accumulator (AC) and Multiplier Quotient (MQ): Temporarily stores
operands and results of Arithmetic Logic Unit (ALU) operations.
2. Describe the IAS Instruction Cycle
➢Fetch
• Opcode of the next instruction is loaded into the IR
• Address portion is loaded into the MAR
• Instruction either taken from the IBR or obtained from memory by
loading the PC into the MAR, memory to the MBR, then the MBR to the
IBR and the IR
• To simplify electronics, only one data path from MBR to IR
➢ Execute
• Circuitry interprets the opcode and executes the instruction
• Moving data, performing an operation in the ALU, etc.
3. Draw and Describe the Flowchart of IAS Operation

• A microprocessor executes a program by repeatedly cycling through

the following three steps:
• Fetch an instruction from memory and place it in the CPU.
• Decode the instruction; if other information is required by the
instruction, fetch the other information. In the decode step, the
program counter is updated to point to the next instruction.
• Execute the instruction (do what the instruction says). Results are
returned to registers and memory during this step.
• ‫يقوم المعالج الدقيق بتنفيذ برنامج عن طريق التدوير بشكل متكرر من خالل الخطوات‬
‫الثالث التالية‬:
 ‫‪.‬جلب تعليمات من الذاكرة ووضعها في وحدة المعالجة المركزية •‬
‫فك شفرة التعليمات‪ .‬إذا كانت التعليمات مطلوبة معلومات أخرى ‪ ،‬فقم بإحضار المعلومات •‬
‫‪.‬األخرى‪ .‬في خطوة فك التشفير ‪ ،‬يتم تحديث عداد البرنامج لإلشارة إلى التعليمات التالية‬
‫تنفيذ التعليمات (افعل ما تقوله التعليمات)‪ .‬يتم إرجاع النتائج إلى السجالت والذاكرة أثناء •‬
‫‪.‬هذه الخطوة‬

‫‪Chapter: 3‬‬

‫‪ →→ https://youtu.be/sI8S2RFinYg?si=5yfxCjMzRA2TyBBo‬شرح المسألة‬
Describe the advantages and disadvantages of the Addressing Modes.
1. Immediate Addressing:
• No memory reference to fetch data
• Fast
• Limited range

2. Direct Addressing:
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space

3. Indirect Addressing:
• Large address space
• Multiple memory accesses to find operand
• Hence slower
4. Register Addressing:
• Limited number of registers
• Very small address field needed
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
• Direct addressing
5. Register Indirect Addressing:
• Indirect addressing
• Large address space
• One fewer memory access than indirect addressing

6. Displacement Addressing:
• Memory Efficiency
• Limited Address Range
Chapter: 4
1-The Difference between Dynamic RAM, Static RAM

2-What are the differences among ROM, EPROM, EEPROM, and flash memory?
Chapter: 5
1. What are the Direct Mapping pros & cons?
Pros:
• Simple
• Inexpensive
Cons:
• Fixed location for given block :

➢ If a program accesses 2 blocks that map to the same line repeatedly, cache
misses are very high.
2. What are the differences among direct, associative, and set-associative
mapping?
Direct Mapping: One-to-one mapping, simple but less flexible.
Associative Mapping: Any block can map to any line in the cache, providing
maximum flexibility but with higher complexity and cost.
Set-Associative Mapping: A compromise that divides the cache into sets,
allowing more flexibility than direct mapping while maintaining some simplicity
compared to associative mapping.
‫ بسيط ولكنه أقل مرونة‬، ‫ رسم الخرائط الفردي‬:‫رسم الخرائط المباشرة‬.
‫ مما يوفر‬، ‫ يمكن ألي كتلة التعيين إلى أي سطر في ذاكرة التخزين المؤقت‬:‫رسم الخرائط الترابطية‬
‫أقصى قدر من المرونة ولكن مع تعقيد وتكلفة أعلى‬.
‫ مما يسمح بمزيد من المرونة‬، ‫ حل وسط يقسم ذاكرة التخزين المؤقت إلى مجموعات‬:‫تعيين االرتباط‬
‫من التعيين المباشر مع الحفاظ على بعض البساطة مقارنة بالتعيين الترابطي‬.

3. List and define the fields of the main memory address for: • direct-mapped
cache. • associative cache • set-associative cache.
• Direct-Mapped Cache Fields:
Tag: The most significant bits of the address, used to uniquely identify a block
within the cache.
Block Offset: The least significant bits of the address, indicating the specific
word within a block.
Block Index: It's derived from the lower-order bits of the address, pointing to a
unique cache line where a block can reside
• Associative Cache Fields:
Tag: The entire address is used as the tag, as a block can be placed in any cache
line.
Word Offset: The least significant bits of the address, pointing the specific word
within a block.
• Set-Associative Cache Fields:
Tag: The most significant bits of the address, identifying a block within a
specific set.
Set Index: The middle bits of the address, selecting the set where a block can
reside.
Block Offset: The least significant bits of the address, determining the exact
word within a block

Chapter: 6
1. Define the terms seek time, rotational delay, and transfer time.
• Seek time
➢Moving head to correct track.
• Rotational time
➢ Waiting for the start of the sector containing data is under the
head.
• Transfer time
➢Waiting for data to rotate under head.

2. Explain briefly the seven RAID levels.

Chapter: 7
1-List and describe the three techniques for performing I/O.

1) Programmed I/O
• CPU has direct control over I/O

➢ Sensing status.
➢ Read/write commands.
➢ Transferring data.
• CPU waits for I/O module to complete operation
• Wastes CPU time
Steps:
• CPU requests I/O operation.
• I/O module performs operation.
• I/O module sets status bits.
• CPU checks status bits periodically.
• I/O module does not inform CPU directly.
• I/O module does not interrupt CPU.
• CPU may wait or come back later.

2)Interrupt driven
• Overcomes CPU waiting.
• No repeated CPU checking of device.
• I/O module interrupts when ready.
Steps:
• CPU issues read command.
• I/O module gets data from peripheral while CPU does other work.
• I/O module interrupts CPU.
• CPU requests data.
• I/O module transfers data.

2) Direct Memory Access (DMA)

• A dedicated I/O processor (DMA controller) takes over data transfer between
the I/O device and memory, bypassing the CPU entirely.
Steps:
• CPU tells DMA controller:

➢ Read/Write.
➢ Device address.
➢ Starting address of memory block for data.
➢Amount of data to be transferred.
• CPU carries on with other work.
• DMA controller deals with transfer.
• DMA controller sends interrupt when finished.
2. Describe in details the Direct Memory Access (DMA) Function, operation, and the using of bus.
Chapter: 8
 ‫اللى انا فهمتة أن المسألة دى لما تيجى دول التلت خطوات اللى احنا هنعملهم‬
Block Diagrams ‫ نرسم ال‬-1
Execution for unsigned Binary Multiplication ‫ نطلع ال‬-2
Flowchart ‫ نرسم ال‬-3
‫و فى مثال مش محلول هو حطة فى الساليد بتاعة هحطة هنا و هحط لينك فديو‬
‫شرح للجزء دا‬
Draw the Block Diagram, Flowchart, and the Execution for
Unsigned Binary Multiplication of 11 by 13
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