0% found this document useful (0 votes)
8 views12 pages

Chapter 2 (Exercise)

The document provides a comprehensive overview of x86 processor architecture, including the CPU's basic elements, instruction execution cycle, multitasking, and memory management. It details the x86 processor's modes of operation, general-purpose and segment registers, and various CPU status flags. Additionally, it discusses input-output systems, including types of RAM, USB advantages, and the role of device drivers.

Uploaded by

18-QADEER AHMAD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
8 views12 pages

Chapter 2 (Exercise)

The document provides a comprehensive overview of x86 processor architecture, including the CPU's basic elements, instruction execution cycle, multitasking, and memory management. It details the x86 processor's modes of operation, general-purpose and segment registers, and various CPU status flags. Additionally, it discusses input-output systems, including types of RAM, USB advantages, and the role of device drivers.

Uploaded by

18-QADEER AHMAD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

NAME QADEER AHMAD ROLL # 19-CS-18

CHAPTER # 2

(x86 Processor Architecture)


2.1 section review
Question#1:

The central processor unit (CPU) contains registers and


what other basic elements?
Control Unit, Arithmetic Logic Unit, and the clock.
Question#2:

The central processor unit is connected to the rest of


the computer system using what three buses?
Data Bus, Control Bus, Address Bus.
Question#3:

Why does memory access take more machine cycles


than register access?
Conventional memory is outside the CPU, and it responds more slowly to access
requests. Registers are hard-wired inside the CPU.
Question#4:

What are the three basic steps in the instruction


execution cycle?
Fetch, Decode, Execute
Question#5:

Which two additional steps are required in the


instruction execution cycle when a memory operand is used?

Fetch memory operands, store memory operands.


Question#6:

During which stage of the instruction execution cycle is


the program counter incremented?
During the fetch step.

Question#7:

After a program has been loaded into memory, how


does it begin execution?
The OS executes a branch (like a GOTO) to the first machine instruction in the
program.
Question#8:

Define multitasking?
The CPU executes multiple tasks (programs) by rapidly switching from one
program to the next. This gives the impression that all programs are executing at
the same time.

Question#9:

What is the function of the OS scheduler?


The OS scheduler determines how much time to allot to each task, and it switches
between tasks.

Question#10:

When the processor switches from one task to another,


what values in the first task’s state must be preserved?
The program counter, the task’s variables, and the CPU registers (including the
status flags).
Question#11:

When the processor switches from one task to


another, what values in the first task’s state must be preserved?
. The program counter, the task’s variables, and the CPU registers (including the
status flags). . The program counter, the task’s variables, and the CPU registers
(including the status flags).

(x86 Architecture Details)


2.2 section review

Question#1:

What are the x86 processor’s three basic modes of


operation?

 Protected Mode.
 Real-address mode.
 System management mode.

Question#2:

Name all eight 32-bit general-purpose registers.


EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP
Question#3:

Name all six segment registers.

CS, DS, SS, ES, FS, GS


Question#4:

What special purpose does the ECX register serve?


Loop counter
Question#5:

Besides the stack pointer (ESP), what other register


points to variables on the stack?
EBP.

Question#6:

Name at least four CPU status flags.


Most common: Carry, Sign, Zero, Overflow. Less common: Auxiliary Carry,
Parity.
Question#7:

Which flag is set when the result of an unsigned


arithmetic operation is too large to fit into the destination?
Carry.
Question#8:

Which flag is set when the result of a signed arithmetic


operation is either too large or too small to fit into the destination?
Overflow.
Question#9:

Which flag is set when an arithmetic or logical


operation generates a negative result?
Sign flag will be set when arithmetic or logical operation generates a negative
result.
Question#10:

Which part of the CPU performs floating-point


arithmetic?
Floating-Point Unit perform the Floating-Point arithmetic.
Question#11:

How many bits long are the FPU data registers?


80 bits long FPU data register.
Question#12:

Which Intel processor was the first member of the


IA-32 family?
The Intel 80386.
Question#13:

Which Intel processor first introduced superscalar


execution?
The Pentium Intel processor first introduced superscalar execution.
Question#14:

Which Intel processor first used MMX technology?


The Pentium II.
Question#13:

Describe the CISC design approach.


CISC means complex instruction set. it a large collection of instructions, some of
which perform sophisticated operations that might be typical of a high-level
language.
(x86 Memory Management)
2.3 section review

Question#1:

What is the range of addressable memory in protected


mode?
4 GByte ( 0 to FFFFFFFFh)is the range of a addressable memory in protected
mode.

Question#2:

What is the range of addressable memory in real-


address mode?
1 MByte (0 to FFFFFh) is the range of the addressable memory in real-address
mode.

Question# 3:
The two ways of describing an address in real-address
mode are segment-offset and ______________.
Linear (absolute).

Question#4:

In real-address mode, convert the following


hexadecimal segment-offset address to a linear address: 0950:0100.
09600h.

Question#5:
In real-address mode, convert the following hexadecimal
segment-offset address to a linear address: 0CD1:02E0.
0CFF0h linear address.

Question#6:

In MASM’s flat segmentation model, how many bits


hold the address of an instruction or variable?
32 bits hold the address of an instruction in MASM’s.

Question#7:

In protected mode, which register references the


descriptor for the stack segment?
SS register reference the descriptor for the stack segment.

Question#8:

In protected mode, which table contains pointers to


memory segments used by a single program?
Local descriptor table.

Question# 9:

In the flat segmentation model, which table contains


pointers to at least two segments?
Global descriptor table contains pointers to at least two segments.

Question#10:

What is the main advantage to using the paging


feature of x86 processors?
The total size of all programs loaded into memory can exceed the amount of
physical memory installed in the computer.
Question#11:

Challenge: Can you think of a reason why MS-DOS


was not designed to support protectedmode programming?
This is an open-ended question, of course. It is a fact that MS-DOS first had to run
on the 8086/8088 processors, which only supported Real-address mode. When
later processors came out that supported Protected mode, my guess is that
Microsoft wanted MS-DOS to continue to run on the older processors. Otherwise,
customers with older computers would refuse to upgrade to new versions of MS-
DOS.

Question#12:

Challenge: In real-address mode, demonstrate two


segment-offset addresses that point to the same linear address.
The following segment-offset addresses point to the same linear address:
0640:0100 and 0630:0200.
(Input-Output System)
2.4 Section Review
Question#1:

Describe SRAM and its most common use.


SRAM is an acronym for Static RAM, used in CPU cache memory.

Question#2:

Describe VRAM.
VRAM (video ram) holds displayable video data. When CRT monitors are used,
VRAM is dual ported, allowing one port to continuously refresh the display while
another port writes data to the display.

Question#3:

List at least two features found in the Intel P965


Express chipset.
Select any two features from the following list:

(1) Intel Fast Memory Access uses an updated Memory Controller Hub (MCH).

(2) I/O Controller Hub (Intel ICH8/R/DH) that supports serial ATA devices (disk
drives).

(3) Support for 10 USB ports, 6 PCI express slots, networking, and Intel Quiet
System technology.

(4) High definition audio chip.


Question#4:
Name four types of RAM mentioned in this chapter.
Dynamic RAM, Static RAM, Video RAM, and CMOS RAM.

Question#5:

Which type of RAM is used for Level 2 cache memory?


Static RAM is used for level 2 cache memory.

Question#6:

What advantages does a USB device offer over a


standard serial or parallel device?
The computer can query a device connected via USB to find out its name and
device type and the type of driver it supports. The computer can also suspend
power to individual devices. None of these capabilities is possible with serial and
parallel ports.

Question#7:
What is the purpose of the 8259A PIC controller?
The 8259 is the interrupt controller chip, sometimes called PIC, that schedules
hardware interrupts and interrupts the CPU.

Question#8:

What are the main differences between Wi-Fi and


Bluetooth?
Bluetooth is a wireless communication protocol for exchanging small amounts of
data over short distances. It is commonly used with mobile devices such as cell
phones and PDAs. Wi-Fi devices operate at a greater speed and capacity than
Bluetooth. Wi-Fi devices often communicate with each other when in the range of
a wireless network.
(Input-Output System)
2.5 section review

Question#1:

Of the four levels of input/output in a computer system,


which is the most universal and portable?
The application program level.

Question#2:

What characteristics distinguish BIOS-level


input/output?
BIOS functions communicate directly with the system hardware. They are
independent of the operating system.

Question#3:

Why are device drivers necessary, given that the BIOS


already has code that communicates with the computer’s hardware?
New devices are invented all the time with capabilities that were often not
anticipated when the BIOS was written.

Question#4:

In the example regarding displaying a string of


characters, which level exists between the operating system and the
video controller card?

The BIOS level.

Question#5:

At which level(s) can an assembly language program


manipulate input/output?
The operating system, BIOS, and hardware levels.

Question#6:

Why do game programs often send their sound output


directly to the sound card’s hardware
ports?
Game programs often try to take advantage of the latest features in specialized
sound cards.
It should be noted that MS-DOS game applications were more prone to do this
than games running under MS-Windows. In fact, Windows-NT, 2000, and XP all
prevent applications from directly accessing system hardware

You might also like