ECE 301/302 Lab 3

Design of a Two-Stage MOSFET Amplifier

Circuit Topology
The following figure shows the two-stage dual-supply MOSFET amplifier circuit that will be designed in this lab.

VDD

RD
RG1
M4
vin M1

vout
RB1 RB2
RL
RG2
M3 M2 M6 M5

−VSS

DC drain currents of M1 and M4 are set by the two current mirrors as follows:

VSS − VGS3 k0 W
ID1 = ID2 = ID3 = = n (VGS3 − Vtn )2 (1)
RB1 2 L
VSS − VGS6 k0 W
ID4 = ID5 = ID6 = = n (VGS6 − Vtn )2 (2)
RB2 2 L
For M1 , M2 and M5 , the following should be satisfied for the active operation:

VDS ≥ Vov = VGS − Vtn (3)

The signal swing at the drain of M1 is limited by VDD and −VSS + Vov 2 + Vov 1 , provided that the gate bias of
M1 is arranged to have the maximum possible swing. However, the minimum value at Vd1 is usually limited by
−VSS + Vov 5 + VGS4 , which is typically higher than −VSS + Vov 2 + Vov 1 . In order to maximize the symmetrical swing,
the DC bias at VD1 may be centered between the upper and the lower limit. However, centering the DC bias is not
always necessary, since it may conflict with other specifications. Nevertheless, the difference between VD1 and the
upper or lower limit should be greater than the desired swing at that node.
As in the case of BJT emitter-follower, MOS source follower bias current can be determined from

0-to-peak output swing

ID5 ≥ (4)
RL

AC small-signal parameters can be obtained as:

vout RD RL RL
Av = ≈− = −gm1 RD (5)
vin 1 1 1
RL + RL +
gm1 gm4 gm4

where r
W W
gm = kn0 Vov = 2kn0 ID (6)
L L

CD4007 transistor array will be used for the implementation of the amplifier. Device parameters of CD4007 are
approximately given as follows:

1
 CD4007N CD4007P
kn0 = 70 µA/V 2 kp0 = 15 µA/V 2
Vtn = 1.4 V Vtp = −1.65 V
W = 170 µm W = 360 µm
L = 10 µm L = 10 µm
λn = 0.016 V −1 λp = 0.01 V −1

Connection diagram of the CD4007 chip (top view) is shown below.

VDD
14 13 12 11 10 9 8

N
P P

P N

1 2 3 4 5 6 7
−VSS

Note that all P-channel substrates are connected to VDD and all N-channel substrates are connected to −VSS .

Calculations and Simulations

Design a common-source MOSFET amplifier with a source follower using the following specifications:
VDD = VSS = 5 V RL = 5 kΩ Operating frequency: 5 kHz
Rin ≥ 100 kΩ |Av | = 30 Zero-to-peak un-clipped swing at Vout ≥ 2.5 V
Isupply ≤ 1.5 mA

1. Show all your calculations, design procedure, and final component values.
2. Verify your results using a circuit simulator. Submit all necessary simulation plots showing that the specifica-
tions are satisfied. Also provide the circuit schematic with DC bias points annotated.

3. Using a circuit simulator, perform Fourier analysis and determine the input and the output signal amplitudes
resulting in 5% total harmonic distortion (THD) at the output. Provide the simulation results.

Measurements
1. Construct the amplifier you designed.
2. Measure ID1 , ID4 , VD1 , VD2 and VD5 . If any DC bias value (especially ID ) is significantly different than the one
obtained from simulations, modify your circuit (i.e. change RB1 , RB2 , RG 1 , or RG 2 ) to get the desired DC bias
before you move onto the next step.
3. Measure Av , Rin , and Isupply (for both VDD and −VSS ).

4. Measure the maximum un-clipped output signal amplitude.

5. Find the input signal amplitude resulting in 5% THD measurement at the output.

Report
1. Include calculations, schematics, simulation plots, and measurement plots.
2. Prepare a table showing calculated, simulated and measured results.
3. Compare the results and comment on the differences.

2
Demonstration
1. Construct the amplifier you designed on your breadboard and bring it to your lab session.
2. Your name and UIN must be written on the side of your breadboard.

3. Submit your report to your TA at the beginning of your lab session.

4. Measure Av , Rin , and Isupply (for both VDD and −VSS ).
5. Apply the input signal resulting in 5% THD at the output from your earlier measurements. Show the input
and output waveforms, and THD measurement at the output.