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Soc Soumik1

The document outlines two assignments focused on SOC design and verification, specifically implementing an 8-bit binary adder and an integer adder using VHDL. Each section includes VHDL code, testbenches, and expected simulation outputs. The first assignment tests various addition scenarios while the second assignment demonstrates a simple integer addition.

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6 views6 pages

Soc Soumik1

The document outlines two assignments focused on SOC design and verification, specifically implementing an 8-bit binary adder and an integer adder using VHDL. Each section includes VHDL code, testbenches, and expected simulation outputs. The first assignment tests various addition scenarios while the second assignment demonstrates a simple integer addition.

Uploaded by

soumik.es23
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment 1 & 2: SOC Design and Verification

(EE642)
Soumik Chakraborty
Reg. No.: 24-24-05
M.Tech VLSI and Embedded System
May 10, 2025

Submitted to:
Mr. Abhilash MT
Assistant Professor
Department of Electronics Engineering

1
1 Lab 1: 8-bit Binary Adder
1.1 VHDL Code
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . NUMERIC_STD . ALL ;
4

5 entity adder8bit is
6 Port (
7 a : in std_logic_vector (7 downto 0) ;
8 b : in std_logic_vector (7 downto 0) ;
9 cin : in std_logic ;
10 sum : out std_logic_vector (7 downto 0) ;
11 cout : out std_logic
12 );
13 end adder8bit ;
14

15 architecture Behavioral of adder8bit is


16 signal temp_sum : unsigned (8 downto 0) ; -- Temporary sum with
carry
17 begin
18 process (a , b , cin )
19 variable input_a : unsigned (7 downto 0) ;
20 variable input_b : unsigned (7 downto 0) ;
21 begin
22 input_a := unsigned ( a ) ;
23 input_b := unsigned ( b ) ;
24 temp_sum <= ( ’0 ’ & input_a ) + ( ’0 ’ & input_b ) + ( "
00000000 " & cin ) ;
25 sum <= std_logic_vector ( temp_sum (7 downto 0) ) ;
26 cout <= temp_sum (8) ;
27 end process ;
28 end Behavioral ;

1.2 Testbench
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . NUMERIC_STD . ALL ;
4

5 entity tb_adder8bit is
6 end tb_adder8bit ;
7

8 architecture test of tb_adder8bit is


9 component adder8bit
10 Port (
11 a : in std_logic_vector (7 downto 0) ;
12 b : in std_logic_vector (7 downto 0) ;
13 cin : in std_logic ;

2
14 sum : out std_logic_vector (7 downto 0) ;
15 cout : out std_logic
16 );
17 end component ;
18

19 signal a , b , sum : std_logic_vector (7 downto 0) := ( others = >


’0 ’) ;
20 signal cin , cout : std_logic := ’0 ’;
21

22 begin
23 UUT : adder8bit port map (
24 a = > a , b = > b , cin = > cin , sum = > sum , cout = > cout
25 );
26

27 stimulus : process
28 begin
29 -- Test case 1: 15 + 1 + 0 = 16
30 a <= " 00001111 " ; -- 15
31 b <= " 00000001 " ; -- 1
32 cin <= ’0 ’;
33 wait for 10 ns ;
34 report " Test 1: 15 + 1 = " & integer ’ image ( to_integer (
unsigned ( sum ) ) ) & " , Carry : " & std_logic ’ image ( cout ) ;
35

36 -- Test case 2: 255 + 1 = 0 with carry


37 a <= " 11111111 " ; -- 255
38 b <= " 00000001 " ; -- 1
39 cin <= ’0 ’;
40 wait for 10 ns ;
41 report " Test 2: 255 + 1 = " & integer ’ image ( to_integer (
unsigned ( sum ) ) ) & " , Carry : " & std_logic ’ image ( cout ) ;
42

43 -- Test case 3: 100 + 55 = 155


44 a <= std_logic_vector ( to_unsigned (100 , 8) ) ;
45 b <= std_logic_vector ( to_unsigned (55 , 8) ) ;
46 cin <= ’0 ’;
47 wait for 10 ns ;
48 report " Test 3: 100 + 55 = " & integer ’ image ( to_integer (
unsigned ( sum ) ) ) & " , Carry : " & std_logic ’ image ( cout ) ;
49

50 wait ;
51 end process ;
52 end test ;

1.3 Simulation Output


Expected textual output from the testbench:
Test 1: 15 + 1 = 16, Carry: ’0’
Test 2: 255 + 1 = 0, Carry: ’1’
Test 3: 100 + 55 = 155, Carry: ’0’

3
[Simulation waveform placeholder]

4
2 Lab 2: Integer Adder (Inputs 3, 4; Output 7)
2.1 VHDL Code
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . NUMERIC_STD . ALL ;
4

5 entity int_add is
6 Port (
7 a : in integer ;
8 b : in integer ;
9 sum : out integer
10 );
11 end int_add ;
12

13 architecture Behavioral of int_add is


14 function add_integers (x , y : integer ) return integer is
15 begin
16 return x + y ;
17 end function ;
18 begin
19 sum <= add_integers (a , b ) ;
20 end Behavioral ;

2.2 Testbench
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . NUMERIC_STD . ALL ;
4

5 entity tb_int_add is
6 end tb_int_add ;
7

8 architecture test of tb_int_add is


9 component int_add
10 Port (
11 a : in integer ;
12 b : in integer ;
13 sum : out integer
14 );
15 end component ;
16

17 signal a , b , sum : integer := 0;


18

19 begin
20 UUT : int_add port map (
21 a = > a , b = > b , sum = > sum
22 );
23

5
24 stimulus : process
25 begin
26 -- Test case : 3 + 4 = 7
27 a <= 3;
28 b <= 4;
29 wait for 10 ns ;
30 report " Test : 3 + 4 = " & integer ’ image ( sum ) ;
31

32 wait ;
33 end process ;
34 end test ;

2.3 Simulation Output


Expected textual output from the testbench:

Test: 3 + 4 = 7

[Simulation waveform placeholder]

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