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End Semester

The document is an exam paper for the course IEC 121 Digital Design and Electric Circuits at the Indian Institute of Information Technology Kottayam. It includes various questions related to digital design concepts, such as binary coded systems, sequence detectors, shift registers, timing diagrams, and state machines. The exam is scheduled for July 2023 and consists of multiple problems requiring detailed solutions.

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saikiranpyarasani4
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9 views4 pages

End Semester

The document is an exam paper for the course IEC 121 Digital Design and Electric Circuits at the Indian Institute of Information Technology Kottayam. It includes various questions related to digital design concepts, such as binary coded systems, sequence detectors, shift registers, timing diagrams, and state machines. The exam is scheduled for July 2023 and consists of multiple problems requiring detailed solutions.

Uploaded by

saikiranpyarasani4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Roll No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY KOTTAYAM


Department of Electronics and Communication Engineering
IEC 121 Digital Design and Electric circuits
End Semester Examination, July 2023

Course Instructors: Dr. Narendra Kumar Reddy/Dr.Milind Thomas/Dr. Rajesh G


Time: 09:30 AM – 12:30 PM Semester II Max marks: 100

Answer all questions


Write necessary steps for each question

1. For each of the following circuits, find the output 𝑌 . (10)

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2. (a) A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base–5 (5)
number is represented by its corresponding 3-bit binary code. In this numbering system, which
number in base–5 system corresponds to the BCP code 100010011001 ?

(b) Two numbers represented in signed 2’s complement form are P = 11101101 and Q = 11100110. If (5)
Q is subtracted from P, what is the value obtained in signed 2’s complement form?

3. A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial (10)
state of the counter is 0002 . The output is pulled high (𝑖.𝑒., multiplexer output will be logic 1 if it is
disabled). Write the output sequence of the circuit for the first 8 clock pulses.

4. Design a sequence detector using Mealy model FSM which produces an output ‘1’ every time the (10)
sequence 0101 is detected and an output ‘0’ otherwise.

5. A 4–bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (10)
(𝑄 0 𝑄 1 𝑄 2 𝑄 3 ). The D input is derived from 𝑄 0 , 𝑄 2 and 𝑄 3 through two XOR gates as shown in figure.

(a) Write the 4-bit values (𝑄 0 𝑄 1 𝑄 2 𝑄 3 ) after each clock pulse till the pattern (1000) reappears on
(𝑄 0 𝑄 1 𝑄 2 𝑄 3 ).
(b) To what values should the shift register be intialized so that the pattern (1001) occurs after the first
clock pulse?

6. (a) Draw the timing diagram for 𝑉 and 𝑍 for the circuit. Assume that the AND gate has a delay of 10ns (5)
and the OR gate has a delay of 5ns.

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(b) For the circuit shown in figure below, two 4-bit parallel-in serial-out shift registers loaded with the (5)
data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state.
What are the full-adder outputs 𝑆 and 𝐶𝑜 after applying two clock pulses?

7. A 2-input up/down synchronous counter using two toggle flip-flops is shown in the figure below. The (10)
counter’s sequence is to be controlled by the input M as follows:
(i) For M=1, sequence of 𝑄 1 , 𝑄 0 is 00, 01, 10, 11, 00, 01, ...
(ii) For M=0, sequence of 𝑄 1 , 𝑄 0 is 00, 11, 10, 01, 00, 11, ...

(a) Design the necessary feedback logic for 𝑇1 and 𝑇0 .


(b) Realize the feedback logic using inverters and 4-input multiplexers only. Use 𝑄 1 and 𝑄 0 as the
control inputs of the multiplexer with 𝑄 1 as the MSB.

8. For the function 𝑓 (𝑎, 𝑏, 𝑐, 𝑑, 𝑒) = Σ 𝑚(6, 7, 9, 11, 12, 13, 16, 17, 18, 20, 21, 23, 25, 28), using a Karnaugh (10)
map,

(a) Find the essential prime implicants (three).


(b) Find the minimum sum of products (7 terms).
(c) Find all of the prime implicants (twelve).

9. Use a 4-to-1 multiplexer and a minimum number of external gates to realize the function 𝐹 (𝑤, 𝑥, 𝑦, 𝑧) = (10)
Σ 𝑚(3, 4, 5, 7, 10, 14) + Σ 𝑑 (1, 6, 15). The inputs are only available uncomplemented.

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10. A state machine is required to cycle through the following sequence of states: (10)
000 → 001 → 010 → 011 → 100 → 101 → 110 → 111
One possible implementation of the state machine is shown figure. Specify what signals should be
applied to each of the multiplexer inputs.

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