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VLSI-Testing MODULE5

The document covers VLSI Design and Testing for Electronics & Communication Engineering students, focusing on sequential MOS logic circuits and structured design/testing methodologies. It outlines techniques for reducing IC design complexity, testing categories, and logic verification principles, including fault models like Stuck-At and short/open circuit models. The content is structured for a course with specified hours and assessment criteria.

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siriramesh83
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19 views64 pages

VLSI-Testing MODULE5

The document covers VLSI Design and Testing for Electronics & Communication Engineering students, focusing on sequential MOS logic circuits and structured design/testing methodologies. It outlines techniques for reducing IC design complexity, testing categories, and logic verification principles, including fault models like Stuck-At and short/open circuit models. The content is structured for a course with specified hours and assessment criteria.

Uploaded by

siriramesh83
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI Design and Testing

B.E., VI Semester, Electronics & Communication Engineering


NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)

Subject Code: BEC602 IA Marks 50


Number of Lecture Hours/Week :04 Exam Marks 50
Total Hours of Pedagogy 50 Exam Hours 03

Prepared by
Mr. PRADEEPA S C
Asst.Professor
EC Dept.
JNNCE,Shimoga.
Module-5
Sequential MOS Logic Circuits:
Introduction, Behaviour of Bistable Elements
(Excluding Mathematical analysis) SR Latch Circuit,
Clocked Latch and Flip-Flop Circuits, Clocked SR
Latch, Clocked JK Latch.
[Text2: 8.1, 8.2, 8.3, 8.4]
Structured Design and Testing: Introduction, Design
Styles, Testing
[Text1: 6.1, 6.2. 6.5]
Structured Design and Testing
Design Styles
Techniques for reducing the complexity of IC design
1. Structured design strategies.
• Hierarchy
• Modularity
• Regularity
• Locality
2. Handcrafted mask layout
3. Gate array design
Testing and Verification
Tests fall into three main categories.
1. The first set of tests verifies that the chip performs its
intended function. Run before tapeout to verify the
functionality of the circuit. functionality tests or logic
verification.
2. The second set of tests are run on the first batch of chips
that return from fabrication. These tests confirm that the
chip operates as it was intended and help debug any
discrepancies.
3. The third set of tests verify that every transistor, gate,
and storage element in the chip functions correctly.
Testing
Logic Verification Principles
• To test this circuit exhaustively, a
sequence of 2N inputs (or test vectors)
must be applied and observed to fully
exercise the circuit. This combinational
circuit is converted to a sequential
circuit with addition of M registers, as
shown in Figure 15.6(b).
• A minimum of 2N+M test vectors must
be applied to exhaustively test the
circuit.

FIGURE 15.6 The combinational explosion in test vectors


Fault Models
To deal with the existence of good and bad parts, it is necessary to
propose a fault model; i.e., a model for how faults occur and their impact
on circuits.

Types of models:
1. Stuck-At model.
2. Short Circuit/Open Circuit model.
1. Stuck-At model.
In the Stuck-At model, a faulty gate input is modeled as a
stuck at zero (Stuck-At-0, S-A-0) or stuck at one (Stuck-At-l, S-
A-l).
This model dates from board-level designs, where it was
determined to be adequate for modeling faults.

These faults most frequently occur due to gate oxide


shorts (the nMOS gate to GND or the pMOS gate to
VDD) or metal-to-metal shorts.
2.Short-Circuit and Open-Circuit Faults
Two bridging or shorted faults are shown in Figure
15.12.
The short S1 results in an S-A-0 fault at input A,
while short S2 modifies the function
of the gate.

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