Department of Electronics and Communication Engineering

GITAM Institute of Technology, GITAM University, Visakhapatnam

4/4 B.Tech. ECE Ist Semester

EUREC711 - VHDL/Verilog
Simulation Laboratory Manual

EEC421 - VLSI DESIGN

LABORATORY
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

EEC421 – VLSI Design Laboratory

Modelling, Functional Simulation, Synthesis and Implementation of the following digital
circuits (with Xilinx Vivado tools) using VHDL/Verilog Hardware Description Languages,
Tanner tools

Part I: Combinational Logic: Basic gates, multiplexer, comparator, adder/substractor,

multipliers, decoders, address decoders, parity generator, ALU.

Part II: Sequential Logic: D-Latch, D-Flip flop, JK-Flip flop, registers, ripple counters,
synchronous counters, shift registers (serial-to-parallel, parallel-to-serial), cyclic encoder/
decoder.

Part III: Memories and State Machines: Read only memory (ROM), random access memory
(RAM), mealy state machine, moore state machine, arithmetic multipliers using FSMs.

Part IV: FPGA System Design: Demonstration of FPGA and CPLD boards, demonstration of
digital design using FPGAs and CPLDs. Implementation of UART/GCD processors on
FPGA/CPLD kit.

Part V: Full Custom IC Design Flow: Schematic, symbol, simulation, layout, DRC, LVS,
RCX, post layout simulation of CMOS inverter, NAND gate, D-flip flop.
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Lab- I
Study of VLSI Design Styles
FPGA – Introduction

The full form of FPGA is “Field Programmable Gate Array”. It contains ten thousand to
more than a million logic gates with programmable interconnection. Programmable
interconnections are available for users or designers to perform given functions easily. A
typical model FPGA chip is shown in the given figure. There are I/O blocks, which are
designed and numbered according to function. For each module of logic level composition,
there are CLB’s Configurable Logic Blocks.

CLB performs the logic operation given to the module. The inter connection between CLB
and I/O blocks are made with the help of horizontal routing channels, vertical routing
channels and PSM Programmable Multiplexers.

The number of CLB it contains only decides the complexity of FPGA. The functionality of
CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After
programming, CLB and PSM are placed on chip and connected with each other with routing
channels.

Advantages

 It requires very small time; starting from design process to functional chip.
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 No physical manufacturing steps are involved in it.
 The only disadvantage is, it is costly than other styles.

Gate Array Design

The gate array GAGA ranks second after the FPGA, in terms of fast prototyping capability.
While user programming is important to the design implementation of the FPGA chip,
metal mask design and processing is used for GA. Gate array implementation requires a
two-step manufacturing process.

The first phase results in an array of uncommitted transistors on each GA chip. These
uncommitted chips can be stored for later customization, which is completed by defining
the metal interconnects between the transistors of the array. The patterning of metallic
interconnects is done at the end of the chip fabrication process, so that the turn-around time
can still be short, a few days to a few weeks. The figure given below shows the basic
processing steps for gate array implementation.

Typical gate array platforms use dedicated areas called channels, for inter-cell routing
between rows or columns of MOS transistors. They simplify the interconnections.
Interconnection patterns that perform basic logic gates are stored in a library, which can
then be used to customize rows of uncommitted transistors according to the netlist.

In most of the modern GAs, multiple metal layers are used for channel routing. With the use
of multiple interconnected layers, the routing can be achieved over the active cell areas; so
that the routing channels can be removed as in Sea-of-Gates SOGSOG chips. Here, the entire
chip surface is covered with uncommitted nMOS and pMOS transistors. The neighboring
transistors can be customized using a metal mask to form basic logic gates.

For inter cell routing, some of the uncommitted transistors must be sacrificed. This design
style results in more flexibility for interconnections and usually in a higher density. GA chip
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utilization factor is measured by the used chip area divided by the total chip area. It is
higher than that of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cell based design requires development of a full custom mask set. The standard
cell is also known as the polycell. In this approach, all of the commonly used logic cells are
developed, characterized and stored in a standard cell library.

A library may contain a few hundred cells including inverters, NAND gates, NOR gates,
complex AOI, OAI gates, D-latches and Flip-flops. Each gate type can be implemented in
several versions to provide adequate driving capability for different fan-outs. The inverter
gate can have standard size, double size, and quadruple size so that the chip designer can
select the proper size to obtain high circuit speed and layout density.

Each cell is characterized according to several different characterization categories, such as,

 Delay time versus load capacitance

 Circuit simulation model
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data

For automated placement of the cells and routing, each cell layout is designed with a fixed
height, so that a number of cells can be bounded side-by-side to form rows. The power and
ground rails run parallel to the upper and lower boundaries of the cell. So that, neighboring
cells share a common power bus and a common ground bus. The figure shown below is a
floorplan for standard-cell based design.
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Full Custom Design

In a full-custom design, the entire mask design is made new, without the use of any library.
The development cost of this design style is rising. Thus, the concept of design reuse is
becoming famous to reduce design cycle time and development cost.

The hardest full custom design can be the design of a memory cell, be it static or dynamic.
For logic chip design, a good negotiation can be obtained using a combination of different
design styles on the same chip, i.e. standard cells, data-path cells, and programmable logic
arrays PLAs PLAs.

Practically, the designer does the full custom layout, i.e. the geometry, orientation, and
placement of every transistor. The design productivity is usually very low; typically a few
tens of transistors per day, per designer. In digital CMOS VLSI, full-custom design is
hardly used due to the high labor cost. These design styles include the design of high-
volume products such as memory chips, high-performance microprocessors and FPGA.
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Study of Programmable Logic Devices

The function provided by each of the 7400-series parts is fixed and cannot be tailored to suit a particular design
situation. This fact, coupled with the limitation that each chip contains only a few logic gates, makes these chips
inefficient for building large logic circuits. It is possible to manufacture chips that contain relatively large
amounts of logic circuitry with a structure that is not fixed. Such chips were first introduced in the 1970s and are
called programmable logic devices (PLDs).

A PLD is a general-purpose chip for implementing logic circuitry. It contains a collection of logic circuit
elements that can be customized in different ways. A PLD can be viewed as a “black box” that contains logic
gates and programmable switches, as illustrated in Figure 3.24. The programmable switches allow the logic gates
inside the PLD to be connected together to implement whatever logic circuit is needed.

Programmable Logic Array (PLA)

Several types of PLDs are commercially available. The first developed was the programmable logic array
(PLA). The general structure of a PLA is depicted in Figure 3.25. Based on the idea that logic functions can be
realized in sum-of-products form, a PLA

Programmable logic device as a black box

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comprises a collection of AND gates that feeds a set of OR gates. As shown in the figure, the PLA’s inputs x1; :
: : ; xn pass through a set of buffers (which provide both the true value and complement of each input) into a
circuit block called an AND plane, or AND array. The AND plane produces a set of product terms P1; : : : ;Pk.
Each of these terms can be configured to implement any AND function of x1; : : : ; xn. The product terms serve
as the inputs to an OR plane, which produces the outputs f1; : : : ; fm. Each output can be configured to realize
any sum of P1; : : : ;Pk and hence any sum-of-products function of the PLA inputs.

A more detailed diagram of a small PLA is given in Figure 3.26, which shows a PLA with three inputs, four
product terms, and two outputs. Each AND gate in the AND plane has six inputs, corresponding to the true and
complemented versions of the three input signals. Each connection to an AND gate is programmable; a signal
that is connected to an AND gate is indicated with a wavy line, and a signal that is not connected to the gate is
shown with a broken line. The circuitry is designed such that any unconnected AND-gate inputs do not affect the
output of the AND gate. In commercially available PLAs, several methods of realizing the programmable
connections exist. Detailed explanation of how a PLA can be built using transistors is given in section 3.10. In
Figure 3.26 the AND gate that produces P1 is shown connected to the inputs x1 and x2. Hence P1 D x1x2.
Similarly, P2 D x1x3, P3 D x1x2x3, and P4 D x1x3. Programmable connections also exist for the OR plane.
Output f1 is connected to product terms P1, P2, and P3. It therefore realizes the function f1 D x1x2 C x1x3 C
x1x2x3. Similarly, output

Gate-level diagram of a PLA.

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f2 = x1x2Cx1x2x3Cx1x3. Although Figure 3.26 depicts the PLA programmed to implement the functions
described above, by programming the AND and OR planes differently, each of the outputs f1 and f2 could
implement various functions of x1, x2, and x3. The only constraint on the functions that can be implemented is
the size of the AND plane because it produces only four product terms. Commercially available PLAs come in
larger sizes than we have shown here. Typical parameters are 16 inputs, 32 product terms, and eight outputs.
Although Figure 3.26 illustrates clearly the functional structure of a PLA, this style of drawing is awkward for
larger chips. Instead, it has become customary in technical literature to use the style shown in Figure 3.27. Each
AND gate is depicted as a single horizontal line attached to an AND-gate symbol. The possible inputs to the
AND gate are drawn as vertical lines that cross the horizontal line. At any crossing of a vertical and horizontal
line, a programmable connection, indicated by an X, can be made. Figure 3.27 shows the programmable
connections needed to implement the product terms in Figure 3.26. Each OR gate is drawn in a similar manner,
with a vertical line attached to an OR-gate symbol.

Customary schematic for the PLA in Figure

The AND-gate outputs cross these lines, and corresponding programmable connections can be formed. The
figure illustrates the programmable connections that produce the functions f1 and f2 from Figure 3.26. The PLA
is efficient in terms of the area needed for its implementation on an integrated circuit chip. For this reason, PLAs
are often included as part of larger chips, such as microprocessors. In this case a PLA is created so that the
connections to the AND and OR gates are fixed, rather than programmable. In section 3.10 we will show that
both fixed and programmable PLAs can be created with similar structures.

Programmable Array Logic (PAL)

In a PLA both the AND and OR planes are programmable. Historically, the programmable switches presented
two difficulties for manufacturers of these devices: they were hard to fabricate correctly, and they reduced the
speed-performance of circuits implemented in the PLAs. These drawbacks led to the development of a similar
device in which the AND plane is programmable, but the OR plane is fixed. Such a chip is known as a
programmable array logic (PAL) device. Because they are simpler to manufacture, and thus less expensive than
PLAs, and offer better performance, PALs have become popular in practical applications
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An example of a PAL with three inputs, four product terms, and two outputs is given in Figure 3.28. The product
terms P1 and P2 are hardwired to one OR gate, and P3 and P4 are hardwired to the other OR gate. The PAL is
shown programmed to realize the two logic functions f1 D x1x2x3Cx1x2x3 and f2 D x1x2Cx1x2x3. In
comparison to the PLA in Figure 3.27, the PAL offers less flexibility; the PLA allows up to four product terms
per OR gate, whereas the OR gates in the PAL have only two inputs. To compensate for the reduced flexibility,
PALs are manufactured in a range of sizes, with various numbers of inputs and outputs, and different numbers of
inputs to the OR gates. An example of a commercial PAL is given in Appendix E.

So far we have assumed that the OR gates in a PAL, as in a PLA, connect directly to the output pins of the chip.
In many PALs extra circuitry is added at the output of each OR gate to provide additional flexibility. It is
customary to use the term macrocell to refer to the OR gate combined with the extra circuitry. An example of the
flexibility that may be provided in a macrocell is given in Figure 3.29. The symbol labeled flip-flop represents a
memory element. It stores the value produced by the OR gate output at a particular point in time and can hold
that value indefinitely. The flip-flop is controlled by the signal called clock. When clock makes a transition from
logic value 0 to 1, the flip-flop stores the value at its D input at that time and this value appears at the flip-flop’s
Q output. Flip-flops are used for implementing many types of logic circuits, as we will show in Chapter 7.

In section 2.7.2 we discussed a 2-to-1 multiplexer circuit. It has two data inputs, a select input, and one output.
The select input is used to choose one of the data inputs as

An example of a PAL.
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Extra circuitry added to OR-gate outputs

the multiplexer’s output. In Figure 3.29 a 2-to-1 multiplexer selects as an output from the PAL either the OR-
gate output or the flip-flop output. The multiplexer’s select line can be programmed to be either 0 or 1. Figure
3.29 shows another logic gate, called a tri-state buffer, connected between the multiplexer and the PAL output.
We discuss tri-state buffers in section 3.8.8. Finally, the multiplexer’s output is “fed back” to the AND plane in
the PAL. This feedback connection allows the logic function produced by the multiplexer to be used internally in
the PAL, which allows the implementation of circuits that have multiple stages, or levels, of logic gates.

A number of companies manufacture PLAs or PALs, or other, similar types of simple PLDs (SPLDs). Apartial
list of companies, and the types of SPLDs that they manufacture, is given in Appendix E. An interested reader
can examine the information that these companies provide on their products, which is available on
theWorldWideWeb (WWW). TheWWW locator for each company is given in Table E.1 in Appendix E.

Programming of PLAs and PALs

In Figures 3.27 and 3.28, each connection between a logic signal in a PLA or PAL and the AND/OR gates is
shown as an X. We describe how these switches are implemented using transistors in section 3.10. Users’
circuits are implemented in the devices by configuring, or programming, these switches. Commercial chips
contain a few thousand programmable switches; hence it is not feasible for a user of these chips to specify
manually the desired programming state of each switch. Instead,CADsystems are employed for this purpose. We
introduced CAD tools in Chapter 2 and described methods for design entry and simulation of circuits. For CAD
systems that support targeting of circuits to PLDs, the tools have the capability to automatically produce the
necessary information for programming each of the switches in the device. A computer system that runs the
CAD tools is connected by a cable to a dedicated programming unit. Once the user has completed the design of a
circuit, the CAD tools generate a file, often called a programming file or fuse map, that specifies the state that
each switch in the PLD should have, to realize correctly the designed circuit. The PLD is placed into the
programming unit, and the programming file is transferred from the computer system. The programming unit
then places the chip into a special programming mode and configures each switch individually. A photograph of
a programming unit is shown in Figure 3.30. Several adaptors are shown beside the main unit; each adaptor is
used for a specific type of chip package. The programming procedure may take a few minutes to complete.
Usually, the programming unit can automatically “read back” the state of each switch after programming, to
verify that the chip has been programmed correctly. A detailed discussion of the process involved in using CAD
tools to target designed circuits to programmable chips is given in Appendices B, C, and D.

PLAs or PALs used as part of a logic circuit usually reside with other chips on a printed circuit board (PCB). The
procedure described above assumes that the chip can be removed from the circuit board for programming in the
programming unit. Removal is made possible by using a socket on the PCB, as illustrated in Figure 3.31.
Although PLAs and PALs are available in the DIP packages shown in Figure 3.21a, they are also available in
another popular type of package, called a plastic-leaded chip carrier (PLCC), which is depicted in Figure 3.31.
On all four of its sides, the PLCC package has pins that “wrap around” the edges of the chip, rather than
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extending straight down as in the case of a DIP. The socket that houses the PLCC is attached by solder to the
circuit board, and the PLCC is held in the socket by friction.

A PLD programming unit (courtesy of Data IO Corp.).

A PLCC package with socket

Instead of relying on a programming unit to configure a chip, it would be advantageous to be able to perform the
programming while the chip is still attached to its circuit board. This method of programming is called in-system
programming (ISP). It is not usually provided for PLAs or PALs, but is available for the more sophisticated
chips that are described below

Complex Programmable Logic Devices (CPLDs)

PLAs and PALs are useful for implementing a wide variety of small digital circuits. Each device can be used to
implement circuits that do not require more than the number of inputs, product terms, and outputs that are
provided in the particular chip. These chips are limited to fairly modest sizes, typically supporting a combined
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number of inputs plus outputs of not more than 32. For implementation of circuits that require more inputs and
outputs, either multiple PLAs or PALs can be employed or else a more sophisticated type of chip, called a
complex programmable logic device (CPLD), can be used. A CPLD comprises multiple circuit blocks on a single
chip, with internal wiring resources to connect the circuit blocks. Each circuit block is similar to a PLA or a
PAL; we will refer to the circuit blocks as PAL-like blocks. An example of a CPLD is given in Figure 3.32. It
includes four PAL-like blocks that are connected to a set of interconnection wires. Each PAL-like block is also
connected to a subcircuit labeled I/O block, which is attached to a number of the chip’s input and output pins.

Structure of a complex programmable logic device (CPLD).

Figure 3.33 shows an example of the wiring structure and the connections to a PAL-like block in a CPLD. The
PAL-like block includes 3 macrocells (real CPLDs typically have about 16 macrocells in a PAL-like block), each
consisting of a four-input OR gate (real CPLDs usually provide between 5 and 20 inputs to each OR gate). The
OR-gate output is connected to another type of logic gate that we have not yet introduced. It is called an
Exclusive-OR (XOR) gate. We discuss XOR gates in section 3.9.1. The behavior of an XOR gate is the same as
for an OR gate except that if both of the inputs are 1, the XOR gate produces a 0. One input to the XOR gate in
Figure 3.33 can be programmably connected to 1 or 0; if 1, then the XOR gate complements the OR-gate output,
and if 0, then the XOR gate has no effect. In many CPLDs the XOR gates can be used in other ways also, which
we will see in Example 4.19, in Chapter 4. The macrocell also includes a flip-flop, a multiplexer, and a tri-state
buffer. As we mentioned in the discussion for Figure 3.29, the flip-flop is used to store the output value produced
by the OR gate. Each tri-state buffer (see section 3.8.8) is connected to a pin on the CPLD package. The tri-state
buffer acts as a switch that allows each pin to be used either as an output from the CPLD or as an input. To use a
pin as an output, the corresponding tri-state buffer is enabled, acting as a switch that is turned on. If the pin is to
be used as an input, then the tri-state buffer is disabled, acting as a switch that is turned off. In this case an
external source can drive a signal onto the pin, which can be connected to other macrocells using the
interconnection wiring. The interconnection wiring contains programmable switches that are used to connect the
PAL-like blocks. Each of the horizontal wires can be connected to some of the vertical wires that it crosses, but
not to all of them. Extensive research has been done to decide how many switches should be provided for
connections between the wires. The number of switches is chosen to provide sufficient flexibility for typical
circuits without wasting
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A section of the CPLD

many switches in practice. One detail to note is that when a pin is used as an input, the macrocell associated with
that pin cannot be used and is therefore wasted. Some CPLDs include additional connections between the
macrocells and the interconnection wiring that avoids wasting macrocells in such situations.

Commercial CPLDs range in size from only 2 PAL-like blocks to more than 100 PALlike blocks. They are
available in a variety of packages, including the PLCC package that is shown in Figure 3.31. Figure 3.34a shows
another type of package used to house CPLD chips, called a quad flat pack (QFP). Like a PLCC package, the
QFP package has pins on all four sides, but whereas the PLCC’s pins wrap around the edges of the package, the
QFP’s pins extend outward from the package, with a downward-curving shape. The QFP’s pins

JTAG programming
Figure 3.34 CPLD packaging and programming
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are much thinner than those on a PLCC, which means that the package can support a larger number of pins;
QFPs are available with more than 200 pins, whereas PLCCs are limited to fewer than 100 pins. Most CPLDs
contain the same type of programmable switches that are used in SPLDs, which are described in section 3.10.
Programming of the switches may be accomplished using the same technique described in section 3.6.3, in which
the chip is placed into a special purpose programming unit. However, this programming method is rather
inconvenient for large CPLDs for two reasons. First, large CPLDs may have more than 200 pins on the chip
package, and these pins are often fragile and easily bent. Second, to be programmed in a programming unit, a
socket is required to hold the chip. Sockets for large QFP packages are very expensive; they sometimes cost
more than the CPLD device itself. For these reasons, CPLD devices usually support the ISP technique. A small
connector is included on the PCB that houses the CPLD, and a cable is connected between that connector and a
computer system. The CPLD is programmed by transferring the programming information generated by a CAD
system through the cable, from the computer into the CPLD. The circuitry on the CPLD that allows this type of
programming has been standardized by the IEEE and is usually called a JTAG port. It uses four wires to transfer
information between the computer and the device being programmed. The term JTAG stands for Joint Test
Action Group. Figure 3.34b illustrates the use of a JTAG port for programming two CPLDs on a circuit board.
The CPLDs are connected together so that both can be programmed using the same connection to the computer
system. Once a CPLD is programmed, it retains the programmed state permanently, even when the power supply
for the chip is turned off. This property is called nonvolatile programming. CPLDs are used for the
implementation of many types of digital circuits. In industrial designs that employ some type of PLD device,
CPLDs are used in about half the cases (SPLDs are used in only a small fraction of recently produced designs).
A number of companies offer competing CPLDs. Appendix E lists, in Table E.2, the names of the major
companies involved and shows the company’s WWW locator. The reader is encouraged to examine the product
information that each company provides on its Web pages. One example of a commercially available CPLD is
described in detail in Appendix E. This CPLD family, manufactured by Altera and called the MAX 7000, is used
in several examples presented later in the book.

Field-Programmable Gate Arrays

The types of chips described above, 7400 series, SPLDs, and CPLDs, are useful for implementation of a wide
range of logic circuits. Except for CPLDs, these devices are rather small and are suitable only for relatively
simple applications. Even for CPLDs, only moderately large logic circuits can be accommodated in a single chip.
For cost and performance reasons, it is prudent to implement a desired logic circuit using as few chips as
possible, so the amount of circuitry on a given chip and its functional capability are important. One way to
quantify a circuit’s size is to assume that the circuit is to be built using only simple logic gates and then estimate
how many of these gates are needed. A commonly used measure is the total number of two-input NAND gates
that would be needed to build the circuit; this measure is often called the number of equivalent gates.

Using the equivalent-gates metric, the size of a 7400-series chip is simple to measure because each chip contains
only simple gates. For SPLDs and CPLDs the typical measure used is that each macrocell represents about 20
equivalent gates. Thus a typical PAL that has eight macrocells can accommodate a circuit that needs up to about
160 gates, and a large CPLD that has 1000 macrocells can implement circuits of up to about 20,000 equivalent
gates. By modern standards, a logic circuit with 20,000 gates is not large. To implement larger circuits, it is
convenient to use a different type of chip that has a larger logic capacity. A field-programmable gate array
(FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs
are quite different from SPLDs and CPLDs because FPGAs do not contain AND or OR planes. Instead, FPGAs
provide logic blocks for implementation of the required functions. The general structure of an FPGA is illustrated
in Figure 3.35a. It contains three main types of resources: logic blocks, I/O blocks for connecting to the pins of
the package, and interconnection wires and switches. The logic blocks are arranged in a two-dimensional array,
and the interconnection wires are organized as horizontal and vertical routing channels between rows and
columns of logic blocks. The routing channels contain wires and programmable switches that allow the logic
blocks to be interconnected in many ways. Figure 3.35a shows two locations for
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General structure of an FPGA

Pin grid array (PGA) package (bottom view)

A field-programmable gate array (FPGA).

programmable switches; the blue boxes adjacent to logic blocks hold switches that connect the logic block input
and output terminals to the interconnection wires, and the blue boxes that are diagonally between logic blocks
connect one interconnection wire to another (such as a vertical wire to a horizontal wire). Programmable
connections also exist between the I/O blocks and the interconnection wires. The actual number of
programmable switches and wires in an FPGA varies in commercially available chips.

FPGAs can be used to implement logic circuits of more than a few hundred thousand equivalent gates in size.
Two examples of FPGAs, called the Altera FLEX 10K and the Xilinx XC4000, are described in Appendix E.
FPGAs are available in a variety of packages, including the PLCC and QFP packages described earlier. Figure
3.35b depicts another type of package, called a pin grid array (PGA). A PGA package may have up to a few
hundred pins in total, which extend straight outward from the bottom of the package, in a grid pattern. Yet
another packaging technology that has emerged is known as the ball grid array (BGA). The BGA is similar to
the PGA except that the pins are small round balls, instead of posts. The advantage of BGA packages is that the
pins are very small; hence more pins can be provided on the package.

Each logic block in an FPGA typically has a small number of inputs and one output. A number of FPGA
products are on the market, featuring different types of logic blocks. The most commonly used logic block is a
lookup table (LUT), which contains storage cells that are used to implement a small logic function. Each cell is
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capable of holding a single logic value, either 0 or 1. The stored value is produced as the output of the storage
cell. LUTs of various sizes may be created, where the size is defined by the number of inputs. Figure 3.36a
shows the structure of a small LUT. It has two inputs, x1 and x2, and one

A two-input lookup table (LUT).

output, f . It is capable of implementing any logic function of two variables. Because a two-variable truth table
has four rows, this LUT has four storage cells. One cell corresponds to the output value in each row of the truth
table. The input variables x1 and x2 are used as the select inputs of three multiplexers, which, depending on the
valuation of x1 and x2, select the content of one of the four storage cells as the output of the LUT. We introduced
multiplexers in section 2.7.2 and will discuss storage cells in Chapter 10. To see how a logic function can be
realized in the two-inputLUT, consider the truth table in Figure 3.36b. The function f1 from this table can be
stored in the LUT as illustrated in Figure 3.36c. The arrangement of multiplexers in the LUT correctly realizes
the function f1. When x1 D x2 D 0, the output of the LUT is driven by the top storage cell, which represents the
entry in the truth table for x1x2 D 00. Similarly, for all valuations of x1 and x2, the logic value stored in the
storage cell corresponding to the entry in the truth table chosen by the particular valuation appears on the LUT
output. Providing access to the contents of storage cells is only one way in which multiplexers can be used to
implement logic functions. A detailed presentation of the applications of multiplexers is given in Chapter 6.
Figure 3.37 shows a three-input LUT. It has eight storage cells because a three-variable truth table has eight
rows. In commercial FPGA chips, LUTs usually have either four or five inputs, which require 16 and 32 storage
cells, respectively. In Figure 3.29 we showed that PALs usually have extra circuitry included with their AND-
OR gates. The same is true for FPGAs, which usually have extra circuitry, besides a LUT, in each logic block.
Figure 3.38 shows how a flip-flop may be included in an FPGA logic block. As discussed for Figure 3.29, the
flip-flop is used to store the value of its D input under control of its clock input. Examples of logic blocks in
commercial FPGAs are presented in Appendix E. For a logic circuit to be realized in an FPGA, each logic
function in the circuit must be small enough to fit within a single logic block. In practice, a user’s circuit is
automatically.
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A three-input LUT

Inclusion of a flip-flop in an FPGA logic block.

translated into the required form by using CAD tools (see section 4.12). When a circuit is implemented in an
FPGA, the logic blocks are programmed to realize the necessary functions and the routing channels are
programmed to make the required interconnections between logic blocks. FPGAs are configured by using the
ISP method, which we explained in section 3.6.4. The storage cells in the LUTs in an FPGA are volatile, which
means that they lose their stored contents whenever the power supply for the chip is turned off. Hence the FPGA
has to be programmed every time power is applied. Often a small memory chip that holds its data permanently,
called a programmable read-only memory (PROM), is included on the circuit board that houses the FPGA. The
storage cells in the FPGA are loaded automatically from the PROM when power is applied to the chips. A small
FPGA that has been programmed to implement a circuit is depicted in Figure 3.39. The FPGA has two-input
LUTs, and there are four wires in each routing channel. The figure shows the programmed states of both the
logic blocks and wiring switches in a section of the FPGA. Programmable wiring switches are indicated by an X.
Each switch shown in blue is turned on and makes a connection between a horizontal and vertical wire. The
switches shown in black are turned off. We describe how the switches are implemented by using transistors in
section 3.10.1. The truth tables programmed into the logic blocks in the top row of the FPGA correspond to the
functions f1 D x1x2 and f2 D x2x3. The logic block in the bottom right of the figure is programmed to produce f
D f1 Cf2 D x1x2 Cx2x3.

Using CAD Tools to Implement Circuits in CPLDs and FPGAs

In section 2.8 we suggested that the reader should work through Tutorial 1, in Appendix B, to gain some
experience using real CAD tools. Tutorial 1 covers the steps of design entry and functional simulation. Now that
we have discussed some of the details of the implementation of circuits in chips, the reader may wish to
experiment further with the CAD tools. In Tutorial 2, section C.3, we illustrate how to download a circuit from a
computer into a CPLD or FPGA.
 Department of Electronics and Communication Engineering
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A section of a programmed FPGA.

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Vivado Design Flow

Introduction
This lab guides you through the process of using Vivado IDE to create a simple HDL design targeting the Nexys4
board. You will simulate, synthesize, and implement the design with default settings. Finally, you will generate
the bitstream and download it in to the hardware to verify the design functionality

Objectives
After completing this lab, you will be able to:
 Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA device located on the Nexys4
board
 Use the provided Xilinx Design Constraint (XDC) file to constrain the pin locations
 Simulate the design using the Vivado simulator
 Synthesize and implement the design
 Generate the bitstream
 Configure the FPGA using the generated bitstream and verify the functionality

Procedure
This lab is broken into steps that consist of general overview statements providing information on the detailed
instructions that follow. Follow these detailed instructions to progress through the lab1.

Design Description
The design consists of some inputs directly connected to the corresponding output LEDs. Other inputs are
logically operated on before the results are output on the remaining LEDs as shown in Figure 1.

Figure 1. The Completed Design

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General Flow

Step 1: Step 2: Step 3: Step 4:

Create a Simulate the Synthesize Implement
Vivado Design using the Design the Design
Project using Vivado
IDE Simulator

Step 5: Step 6:
Perform the Verify
Timing Functionality
Simulation in Hardware

Create a Vivado Project using IDE Step 1

1-1. Launch Vivado and create a project targeting the XC7A100TCSG324-1 device
(Nexys4) and using the Verilog HDL. Use the provided lab1.v and lab1.xdc files
from the 2014_2_artix7_sources\lab1 directory.

1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2014.2 > Vivado
2014.2

1-1-2. Click Create New Project to start the wizard. You will see Create A New Vivado Project dialog box.
Click Next.

1-1-3. Click the Browse button of the Project location field of the New Project form, browse to
c:\xup\fpga_flow\2014_2_artix7_labs, and click Select.

1-1-4. Enter lab1 in the Project name field. Make sure that the Create Project Subdirectory box is checked.
Click Next.
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Figure 2. Project Name and Location entry

1-1-5. Select RTL Project option in the Project Type form, and click Next.

1-1-6. Using the drop-down buttons, select Verilog as the Target Language and Simulator Language in the
Add Sources form.

Figure 3. Selecting Target and Simulator language

1-1-7. Click on the Add Files… button, browse to the c:\xup\fpga_flow\2014_2_artix7_sources\lab1

directory, select lab1.v, click OK, and then click Next to get to the Add Existing IP form.

1-1-8. Since we do not have any IP to add, click Next to get to the Add Constraints form.

1-1-9. The constraint file lab1_nexys4.xdc are automatically added. Highlight and delete the XDC file not for the
target board by clicking on the “X” on the right hand side of the window.
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If no files are added, click on the Add Files… button, browse to the
c:\xup\fpga_flow\2014_2_artix7_sources\lab1 directory (if necessary), lab1_nexys4.xdc and click OK
(if necessary), and then click Next.

This Xilinx Design Constraints file assigns the physical IO locations on FPGA to the switches and LEDs
located on the board. This information can be obtained either through the board’s schematic or the
board’s user guide.

1-1-10. In the Default Part form, using the Parts option and various drop-down fields of the Filter section. If
using the Nexys4 board, select the XC7A100TCSG324-1 part. Click Next.

Figure 4. Part Selection for the Nexys4

You can select the Boards Specify option, select Artix-7 under the Library filter and select the
appropriate board.

1-1-11. Click Finish to create the Vivado project.

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Use the Windows Explorer and look at the c:\xup\fpga_flow\2014_2_artix7_labs\lab1 directory. You will
find that the lab1.cache and lab1.srcs directories and the lab1.xpr (Vivado) project file have been
created. The lab1.cache directory is a place holder for the Vivado program database. Two directories,
constrs_1 and sources_1, are created under the lab1.srcs directory; deep down under them, the copied
lab1.xdc (constraint) and lab1.v (source) files respectively are placed.

Figure 5. Generated directory structure

1-2. Open the lab1.v source and analyze the content.

1-2-1. In the Sources pane, double-click the lab1.v entry to open the file in text mode.

Figure 6. Opening the source file

1-2-2. Notice in the Verilog code that the first line defines the timescale directive for the simulator. Lines 2-5 are
comment lines describing the module name and the purpose of the module.

1-2-3. Line 7 defines the beginning (marked with keyword module) and Line 19 defines the end of the module
(marked with keyword endmodule).

1-2-4. Lines 8-9 defines the input and output ports whereas lines 12-17 defines the actual functionality.

1-3. Open the lab1_nexys4.xdc source and analyze the content.

1-3-1. In the Sources pane, expand the Constraints folder and double-click the lab1.xdc entry to open the file
in text mode.
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Figure 7. Opening the constraint file

1-3-2. For the lines 5-20 defines the pin locations of the input switches [7:0] and lines 25-40 defines the pin
locations of the output LEDs [7:0].

1-4. Perform RTL analysis on the source file.

1-4-1. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and
click on Schematic.

The model (design) will be elaborated and a logic view of the design is displayed.

Figure 8. A logic view of the design

Notice that some of the switch inputs go through gates before being output to LEDs and the rest go
straight through to LEDs as modeled in the file.

Simulate the Design using the Vivado Simulator Step 2

2-1. Add the lab1_tb.v testbench file.
2-1-1. Click Add Sources under the Project Manager tasks of the Flow Navigator pane.

Figure 9. Add Sources

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2-1-2. Select the Add or Create Simulation Sources option and click Next.

Figure 10. Selecting Simulation Sources option

2-1-3. In the Add Sources Files form, click the Add Files… button.

2-1-4. Browse to the c:\xup\fpga_flow\2014_2_artix7_sources\lab1 folder and select lab1_tb.v and click OK.

2-1-5. Click Finish.

2-1-6. Select the Sources tab and expand the Simulation Sources group.

The lab1_tb.v file is added under the Simulation Sources group, and lab1.v is automatically placed in its
hierarchy as a dut (device under test) instance.

Figure 11. Simulation Sources hierarchy

2-1-7. Using the Windows Explorer, verify that the sim_1 directory is created at the same level as constrs_1
and sources_1 directories under the lab1.srcs directory, and that a copy of lab1_tb.v is placed under
lab1.srcs > sim_1 > imports > lab1.

2-1-8. Double-click on the lab1_tb in the Sources pane to view its contents.
 Department of Electronics and Communication Engineering
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Figure 12. The self-checking testbench

The testbench defines the simulation step size and the resolution in line 1. The testbench module
definition begins on line 5. Line 15 instantiates the DUT (device/module under test). Lines 17 through 26
define the same module functionality for the expected value computation. Lines 28 through 39 define
the stimuli generation, and compare the expected output with what the DUT provides. Line 41 ends the
testbench. The $display task will print the message in the simulator console window when the
simulation is run.

2-2. Simulate the design for 200 ns using the Vivado simulator.

2-2-1. Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane.

A Project Settings form will appear showing the Simulation properties form.

2-2-2. Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click OK.
 Department of Electronics and Communication Engineering
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Figure 13. Setting simulation run time

2-2-3. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow
Navigator pane.

The testbench and source files will be compiled and the Vivado simulator will be run (assuming no
errors). You will see a simulator output similar to the one shown below.

Figure 14. Simulator output

You will see four main views: (i) Scopes, where the testbench hierarchy as well as glbl instances are
displayed, (ii) Objects, where top-level signals are displayed, (iii) the waveform window, and (iv) Tcl
Console where the simulation activities are displayed. Notice that since the testbench used is self-
checking, the results are displayed as the simulation is run.
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Notice that the lab1.sim directory is created under the lab1 directory, along with several lower-level
directories.

Figure 15. Directory structure after running behavioral simulation

You will see several buttons next to the waveform window which can be used for the specific purpose as
listed in the table below.
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Table 1: Various buttons available to view the waveform
Waveform options
Save the
waveform
Zoom In
Zoom Out
Zoom Fit
Zoom to cursor
Go to Time 0
Go to Last Time
Previous
Transition
Next Transition
Add Marker
Previous Marker
Next Marker
Swap Cursors
Snap to Transition
Floating Ruler

2-2-4. Click on the Zoom Fit button ( ) to see the entire waveform.

Notice that the output changes when the input changes.

You can also float the simulation waveform window by clicking on the Float button on the upper right
hand side of the view. This will allow you to have a wider window to view the simulation waveforms. To
reintegrate the floating window back into the GUI, simply click on the Dock Window button.

Figure 16. Float Button

Figure 17. Dock Window Button

2-3. Change display format if desired.

2-3-1. Select i[31:0] in the waveform window, right-click, select Radix, and then select Unsigned Decimal to
view the for-loop index in integer form. Similarly, change the radix of switches[7:0] to Hexadecimal.
Leave the leds[7:0] and e_led[7:0] radix to binary as we want to see each output bit.
2-4. Add more signals to monitor the lower-level signals and continue to run the
simulation for 500 ns.
2-4-1. Expand the lab1_tb instance, if necessary, in the Scopes window and select the dut instance.
The swt[7:0] and led[7:0] signals will be displayed in the Objects window.
 Department of Electronics and Communication Engineering
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Figure 18. Selecting lower-level signals

2-4-2. Select swt[7:0] and led[7:0] and drag them into the waveform window to monitor those lower-level
signals.

2-4-3. On the simulator tool buttons ribbon bar, type 500 over in the simulation run time field, click on the drop-
down button of the units field and select ns ( ) if we want to run for 500
ns (total of 700 ns), and click on the ( ) button.

The simulation will run for an additional 500 ns.

2-4-4. Click on the Zoom Fit button and observe the output.

Figure 19. Running simulation for additional 500 ns

Observe the Tcl Console window and see the output is being displayed as the testbench uses the
$display task.

Figure 20. Tcl Console output after running the simulation for additional 500 ns

2-4-5. Close the simulator by selecting File > Close Simulation.

2-4-6. Click OK and then click No to close it without saving the waveform.
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Synthesize the Design Step 3

2-5. Synthesize the design with the Vivado synthesis tool and analyze the Project
Summary output.

2-5-1. Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane.

The synthesis process will be run on the lab1.v file (and all its hierarchical files if they exist). When the
process is completed a Synthesis Completed dialog box with three options will be displayed.

2-5-2. Select the Open Synthesized Design option and click OK as we want to look at the synthesis output
before progressing to the implementation stage.

Click Yes to close the elaborated design if the dialog box is displayed.

2-5-3. Select the Project Summary tab and understand the various windows.

If you don’t see the Project Summary tab then select Layout > Default Layout, or click the Project

Summary icon .

Figure 21. Project Summary view

Click on the various links to see what information they provide and which allows you to change the
synthesis settings.

2-5-4. Click on the Table tab in the Project Summary tab.

Notice that there are an estimated three LUTs and 16 IOs (8 input and 8 output) that are used

Figure 22. Resource utilization estimation summary for the Nexys4

 Department of Electronics and Communication Engineering
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2-5-5. In The Flow Navigator, under Synthesis (expand Synthesized Design if necessary), click on Schematic
to view the synthesized design in a schematic view.

Figure 23. Synthesized design’s schematic view

Notice that IBUFs and OBUFs are automatically instantiated (added) to the design as the input and
output are buffered. The logical gates are implemented in LUTs (1 input is listed as LUT1, 2 input is
listed as LUT2, and 3 input is listed as LUT3). Four gates in RTL analysis output are mapped onto four
LUTs in the synthesized output.

Using Windows Explorer, verify that lab1.runs directory is created under lab1. Under the runs
directory, synth_1 directory is created which holds several files related to synthesis.

Figure 24. Directory structure after synthesizing the design

Implement the Design Step 4

3-1. Implement the design with the Vivado Implementation Defaults (Vivado
Implementation 2014) settings and analyze the Project Summary output.

3-1-1. Click on Run Implementation under the Implementation tasks of the Flow Navigator pane.

The implementation process will be run on the synthesized design. When the process is completed an
Implementation Completed dialog box with three options will be displayed.
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3-1-2. Select Open implemented design and click OK as we want to look at the implemented design in a
Device view tab.

3-1-3. Click Yes, if prompted, to close the synthesized design.

The implemented design will be opened.

3-1-4. In the Netlist pane, select one of the nets (e.g. led_OBUF[1]) and notice that the net displayed in the
X1Y1 clock region in the Device view tab (you may have to zoom in to see it).

3-1-5. If it is not selected, click the Routing Resources icon to show routing resources.

Figure 25. Selecting a net

Figure 26. Viewing implemented design for the Nexys4

Close the implemented design view and select the Project Summary tab (you may have to change to
the Default Layout view) and observe the results.

Select the Post-Implementation tab.

Notice that the actual resource utilization is three LUTs and 16 IOs. Also, it indicates that no timing
constraints were defined for this design (since the design is combinatorial).
 Department of Electronics and Communication Engineering
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Figure 27. Implementation results for the Nexys4

Using the Windows Explorer, verify that impl_1 directory is created at the same level as synth_1 under
the lab1.runs directory. The impl_1 directory contains several files including the implementation report
files.

3-1-6. In Vivado, select the Reports tab in the bottom panel (if not visible, click Window in the menu bar and
select Reports), and double-click on the Utilization Report entry under the Place Design section. The
report will be displayed in the auxiliary view pane showing resource utilization. Note that since the
design is combinatorial no registers are used.

Figure 28. Available reports to view

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Perform Timing Simulation Step 5
4-1. Run a timing simulation.

4-1-1. Select Run Simulation > Run Post-Implementation Timing Simulation process under the Simulation
tasks of the Flow Navigator pane.

The Vivado simulator will be launched using the implemented design and lab1_tb as the top-level
module.

Using the Windows Explorer, verify that timing directory is created under the lab1.sim > sim_1 > impl
directory. The timing directory contains generated files to run the timing simulation.

4-1-2. Click on the Zoom Fit button to see the waveform window from 0 to 200 ns.

4-1-3. Right-click at 50 ns (where the switch input is set to 0000000b) and select Markers > Add Marker.

4-1-4. Similarly, right-click and add a marker at around 55.000 ns where the leds changes.

4-1-5. You can also add a marker by clicking on the Add Marker button ( ). Click on the Add Marker button
and left-click at around 60 ns where e_led changes.

Figure 29. Timing simulation output

Notice that we monitored the expected led output at 10 ns after the input is changed (see the testbench)
whereas the actual delay is about 5.000 ns.

4-1-6. Close the simulator by selecting File > Close Simulation without saving any changes.

Generate the Bitstream and Verify Functionality Step 6

5-1. Connect the board and power it ON. Generate the bitstream, open a hardware
session, and program the FPGA.

5-1-1. Make sure that the Micro-USB cable is connected to the JTAG PROG connector (next to the power
supply connector).

5-1-2. Make sure that the board is set to use USB power (via the Power Select jumper JP3 on the Nexys4)
 Department of Electronics and Communication Engineering
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Figure 30. Board connection for the Nexys4

5-1-3. Power ON the board.

5-1-4. Click on the Generate Bitstream entry under the Program and Debug tasks of the Flow Navigator pane.

The bitstream generation process will be run on the implemented design. When the process is
completed a Bitstream Generation Completed dialog box with two options will be displayed.

Figure 31. Bitstream generation

This process will have generated a lab1.bit file under impl_1 directory in the lab1.runs directory.

5-1-5. Select the Open Hardware Manager option and click OK.

The Hardware Manager window will open indicating “unconnected” status.

5-1-6. Click on the Open a new hardware target link.

You can also click on the Open recent target link if the board was already targeted before.

Figure 32. Opening new hardware target

5-1-7. Click Next to see the Hardware Server Settings form.

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5-1-8. Click Next with the Hardware Target selected.

The JTAG cable which uses the Xilinx_tcf should be detected and identified as a hardware target. It will
also show the hardware devices detected in the chain.

Figure 33. New hardware target detection for the Nexys4

5-1-9. Click Next and then Finish.

The Hardware Session status changes from Unconnected to the server name and the device is
highlighted. Also notice that the Status indicates that it is not programmed.

Figure 34. Opened hardware session for the Nexys4

5-1-10. Select the device and verify that the lab1.bit is selected as the programming file in the General tab.

Figure 35. Programming file

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5-1-11. Click on the Program device > XC7A100T_0 or the XC7A35T_0 link in the green information bar to
program the target FPGA device.

Another way is to right click on the device and select Program Device…

Figure 36. Selecting to program the FPGA

5-1-12. Click Program to program the FPGA.

The DONE light will light when the device is programmed. You may see some other LEDs lit depending
on switch positions.

5-1-13. Verify the functionality by flipping switches and observing the output on the LEDs (Refer to the earlier
logic diagram).

5-1-14. When satisfied, power OFF the board.

5-1-15. Close the hardware session by selecting File > Close Hardware Manager.

5-1-16. Click OK to close the session.

5-1-17. Close the Vivado program by selecting File > Exit and click OK.

Conclusion
The Vivado software tool can be used to perform a complete design flow. The project was created using the
supplied source files (HDL model and user constraint file). A behavioral simulation using the provided testbench
was done to verify the model functionality. The model was then synthesized, implemented, and a bitstream was
generated. The timing simulation was run on the implemented design using the same testbench. The
functionality was verified in hardware using the generated bitstream.
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Verilog Model illustrating various Basic Gates

module gates(a, b, y1, y2, y3, y4 ,y5);

input a, b;
output y1, y2, y3, y4, y5;

assign y1 = a&b; // AND Gate

assign y21 = a|b; // OR Gate
assign y3 = a^b; // XOR Gate
assign y4 = ~(a&b); // NAND Gate
assign y5 = ~(a|b; // NOR Gate
endmodule

Testbench Verilog Model

`timescale 1ns/1ps
module gates_test;
reg a,b;
wire y1, y2, y3, y4, y5;

gates g1(a, b, y1, y2, y3, y4, y5);

initial
begin
a=1’b0; b=1’b0;
#10 a=1’b0; b=1’b1;
#10 a=1’b1; b=1’b0;
#10 a=1’b1; b=1’b1;
#10 $finish;
end

initial
begin
$monitor(“Time = %d a = %b b = %b y1=%b y2=%b y3=%b y4=%b y5=%b”,
$time, a,b,y1, y2, y3, y4, y5);
end
endmodule
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Verilog Model of a Half Adder (Dataflow)

`timescale 1ns/1ps
module hadder(a, b, s, c);
input a,b;
output s,c;

assign s = a^b;
assign c = a&b;
endmodule

Testbench Verilog Model for Halfadder

module haddertest;
reg a,b;
wire s, c;

hadder h1(a, b, s, c);

initial
begin
a=1’b0; b=1’b0;
#10 a=1’b0; b=1’b1;
#10 a=1’b1; b=1’b0;
#10 a=1’b1; b=1’b1;
#10 $finish;
end

initial
begin
$monitor(“Time = %d a = %b b = %b s=%b c=%b”, $time, a,b,s,c);
end
endmodule
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Verilog Model of a 2X4 Decoder (Behavioral)

module dec24(ip, op);

input [1:0] ip;
output [0:3] op;
reg [0:3] op;

always@(ip)
begin
case(ip)
2’b00 : op = 4’b1000;
2’b01 : op = 4’b0100;
2’b10 : op = 4’b0010;
2’b11 : op = 4’b0001;
default: op = 4’b0000;
endcase
end
endmodule
Verilog Model of a 2X4 Decoder (Dataflow)

`timescale 1ns/1ps
module dec24(ip, op);
input [1:0] ip;
output [0:3] op;
assign op[0] = ~ip[1] & ~ip[0];
assign op[1] = ~ip[1] & ip[0];
assign op[2] = ip[1] & ~ip[0];
assign op[3] = ip[1] & ip[0];
endmodule

Testbench Verilog Model of a 2 X 4 Decoder

`timescale 1ns/1ps
module test1_tb;
reg [1:0] ip;
wire [0:3] op;

dec24 d1(ip, op);

initial
begin
ip=2'b00;
#10 ip=2'b01;
#10 ip=2'b10;
#10 ip=2'b11;
#10 ip=2'b01;
end
endmodule
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Verilog Model of a Tristate Buffer

module tristate(a, en, y);

input [3:0] a;
input en;
output [3:0] y;
assign y = en ? a :4’bz;
endmodule

1) Student Exercise: Develop the Verilog model of a 1-bit full adder

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Lab -II
Modeling and Simulation of Combinational Logic in Verilog
Theory:
A combinational circuit consists of an interconnection of logic gates. Combinational logic gates react to the
values of the signals at their inputs and produce the value of the output signal, transforming binary information
from the given input data to a required output data. For n input variables, there are 2n possible combinations of
the binary inputs. For each possible input combination, there is one possible value for each output variable. Thus,
a combinational circuit can be specified with a truth table that lists the output values for each combination of
input variables.

Multiplexer:
A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs
it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally,
there are 2n input lines and n selection lines whose bit combinations determine which input is selected.

Full Adder:
Addition of n-bit binary numbers requires the use of a full adder, and the process of addition proceeds on a bit-
by-bit basis, right to left, beginning with the least significant bit. After the least significant bit, addition at each
position adds not only the respective bits of the words, but must also consider a possible carry bit from addition
at the previous position.

A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and
two outputs. Two of the input variables, denoted by x and y, represent the two significant bits to be added. The
third input, z , represents the carry from the previous lower significant position. Two outputs are necessary
because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary representation of 2 or 3
needs two bits.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Decoder: A binary code of n bits is capable of representing up to 2n distinct elements of coded

information. A decoder is a combinational circuit that converts binary information from n input lines to
a maximum of 2n unique output lines. If the n -bit coded information has unused combinations, the
decoder may have fewer than 2n outputs. Furthermore, decoders include one or more enable inputs to
control the circuit operation.

Encoder: An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary
code corresponding to the input value.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 4 X 1 Multiplexer (Dataflow)

module mux41(i0, i1, i2, i3, s1, s0, op);

input i0, i1, i2, i3, s1, s0;
output op;

assign op = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) |(s1 & s0
& i3);
endmodule
Testbench Verilog Model for a 4 X 1 Multiplexer

`timescale 1ns/1ps
module mux41test;
reg i0, i1, i2, i3;
reg s1, s0;
wire op;

mux41 m1(i0, i1, i2, i3, s1, s0, op);

initial
begin
{i0, i1, i2, i3} = 4’b1010;
{s1, s0} = 2’b00;
#10 {s1, s0} = 2’b01;
#10 {s1, s0} = 2’b10;
#10 {s1, s0} = 2’b11;
#10 $finish;
end

initial
$monitor(“Time = %d, ip=%b sel=%b op=%b”, $time, {i0, i1, i2, i3},
{s1, s0}, op);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 4 X 1 Multiplexer (Behavioral)

module mux41(ip, sel, op)

input [0:3] ip;
input [1:0] sel;
output op;
reg op;

always @(ip or sel)

begin
case(sel)
2’b00 : op = i[0];
2’b01 : op = i[1];
2’b10 : op = i[2];
2’b11 : op = i[3];
default: op = 1’b0;
endcase
end
endmodule

Testbench Verilog Model for 4 X 1 Multiplexer

`timescale 1ns/1ps
module mux41test;
reg [0:3] ip;
reg [1:0] sel;
wire op;

mux41 m1(ip, sel, op);

initial
begin
ip = 4’b1010;
sel = 2’d0;
#10 sel = 2’b01;
#10 sel = 2’b10;
#10 sel = 2’b11;
#10 $finish;
end

initial
$monitor(“Time = %d, ip=%b sel=%b op=%b”, $time, ip, sel, op);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model for a 1 X 4 Demultiplexer (Dataflow)

module demux14(ip , s1, s0, op0, op1, op2, op3);

input ip, s1, s0;
output op0, op1, op2, op3;

assign op0 = ~s1 & ~s0 & ip;

assign op1 = ~s1 & s0 & ip;
assign op2 = s1 & ~s0 & ip;
assign op3 = s1 & s0 & ip;
endmodule

Verilog Model of a 1 X 4 Demultiplexer (Behavioral)

module demux14(ip , sel, op);

input ip,
input [1:0] sel;
output [0:3] op;
reg [0:3] op;

always @(ip or sel)

begin
case(sel)
2’b00 : op = {ip, 1’b0, 1’b0, 1’b0};
2’b01 : op = {1’b0, ip, 1’b0, 1’b0};
2’b10 : op = {1’b0, 1’b0, ip, 1’b0};
2’b11 : op = {1’b0, 1’b0, 1’b0, ip};
default: op = {1’b0, 1’b0, 1’b0, 1’b0};
endcase
end
endmodule
Testbench Verilog Model for 1 X 4 Demultiplexer
`timescale 1ns/1ps
module demuxtest;
reg ip;
reg [1:0] sel;
wire [0:3] op;
demux14 d1(ip, sel, op);
initial
begin
ip=1’b0;
sel=2’d0;
#10 sel=2’d1;
#10 sel=2’d2;
#10 sel=2’d3;
#10 $finish;
end

initial
$monitor(“Time = %d, ip=%b sel=%b op=%b”, $time, ip, sel, op);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Verilog Model of a 4 X 2 Encoder (Dataflow)
module enc42(ip, op)
input [3:0] ip;
output [1:0] op;
assign op[0] = ip[1] | ip[3];
assign op[1] = ip[2] | ip[3];
endmodule
Verilog Model of a 4 X 2 Encoder (Behavioral) Verilog Model of a 4 X 2 Priority Encoder
(Dataflow)
module enc42(ip, op)
input [3:0] ip; module penc42(w, y, z)
output [1:0] op; input [3:0] w;
reg [1:0] op; output [1:0] y;
output zout;
always @(ip) wire i0, i1, i2, i3;
begin
case(ip) assign i0 = ~w[3]&~w[2]&~w[1]&w[0];
4’b0001: op = 2’b00; assign i1 = ~w[3]&~w[2]&w[1];
4’b0010: op = 2’b01; assign i2 = ~w[3]&w[2];
4’b0100: op = 2’b10; assign i3 = w3;
4’b1000: op = 2’b11; assign y[0] = i1 |i3;
default: op = 2’b00; assign y[1] = i2 | i3;
endcase assign zout = i1 | i2 | i3 | i4;
end endmodule
endmodule
Verilog Model of a 4 X 2 Priority encoder(Behavioral)
module penc42(w,y)
input [3:0] w;
output [1:0] y;
reg [1:0 y;

always @(w)
begin
if(w[3])
y = 2’b11;
else if(w[2])
y = 2’b10;
else if(w[1])
y = 2’b01;
else
y = 2’b00;
end
endmodule
Student Exercises
1. 2 X 4 Decoder (Dataflow & Behavioral Models)
2. BCD – to – 7 Segment Display Code Converter
3. 4-Bit Binary to Gray Code Converter
4. 4-Bit Gray to Binary Code Converter
5. BCD to Excess 3 Code Converter
6. 8 X 3 Encoder & Decoder (using Dataflow and Behavioral Models)
7. 8-Bit Parity Generator
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a Priority Encoder using casez statement

module penc42(w,y)
input [3:0] w;
output reg [1:0] y;

always @(w)
begin
casez(w)
4’b1???: y = 2’b11;
4’b01??: y = 2’b11;
4’b001?: y = 2’b11;
4’b0001: y = 2’b11;
default: y = 2’b00;
endcase
end
endmodule

Verilog Model of a 7-Segment Display Decoder

module sevenseg(input [3:0] data, output reg [6:0] segments);
parameter BLANK = 7’b000_0000;
parameter ZERO = 7’b111_1110;
parameter ONE = 7’b011_0000;
parameter TWO = 7’b110_1101;
parameter THREE = 7’b111_1001;
parameter FOUR = 7’b011_0011;
parameter FIVE = 7’b101_1011;
parameter SIX = 7’b101_1111;
parameter SEVEN = 7’b111_0000;
parameter EIGHT = 7’b111_1111;
parameter NINE = 7’b111_1011;
always @(*)
case(data)
0: segments = ZEROS;
1: segments = ONE;
2: segments = TWO;
3: segments = THREE;
4: segments = FOUR;
5: segments = FIVE;
6: segments = SIX;
7: segments = SEVEN;
8: segments = EIGHT;
9: segments = NINE;
default: segments = BLANK;
endcase
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab -III
Synthesis and FPGA Implementation of Combinational Logic in Verilog
`timescale 1ns / 1ps
module lab1(
input [7:0] swt,
output [7:0] led
);

assign led[0] = ~swt[0];

assign led[1] = swt[1] & ~swt[2];
assign led[3] = swt[2] & swt[3];
assign led[2] = led[1] | led[3];
assign led[7:4] = swt[7:4];

endmodule
`timescale 1ns / 1ps
module lab1_tb();
reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;
integer i;

lab1 dut(.led(leds),.swt(switches));

function [7:0] expected_led;

input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction

initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected:
%b, actual: %b", e_led, leds);
end
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

# Nexys4 DDR Pin Assignments

############################
# On-board Slide Switches #
############################
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { swt[0] }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { swt[1] }];
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { swt[2] }];
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { swt[3] }];
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { swt[4] }];
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { swt[5] }];
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { swt[6] }];
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { swt[7] }];

############################
# On-board led #
############################
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }];
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }];
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }];
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }];
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }];
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }];
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }];
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }];
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

module bcg2sseg(bcd, ca, an);

input [2:0] bcd;
output [7:0] SSEG_CA;
output [7:0] SSEG_AN;

assign SSEG_AN = 8'b11111110;

always @(bcd)
begin
case(bcd)
3'd0: SSEG_CA = 8'b11000000;
3'd1: SSEG_CA = 8'b11111001;
3'd2: SSEG_CA = 8'b10100100;
3'd3: SSEG_CA = 8'b10110000;
3'd4: SSEG_CA = 8'b10011001;
3'd5: SSEG_CA = 8'b10010010;
3'd6: SSEG_CA = 8'b10000010;
3'd7: SSEG_CA = 8'b11111000;
default: SSEG_CA = 8'b11111000;
endcase
end
endmodule

# Nexys4 DDR Pin Assignments

##Switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { bcd[0]
}]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { bcd[1]
}]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { bcd[2]
}]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

##7 segment display

set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[6] }]; #IO_L4P_T0_D04_14 Sch=cg

set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports {

SSEG_CA[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp

set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {

SSEG_AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab -IV
Modeling and Simulation of Combinational Logic in Verilog
(Structural Modeling)
Verilog Model of a 2 X 1 Multiplexer
module mux21(i0, i1, s, op);
input i0,i1,s;
output op;
assign op = s ? i1 : i0;
endmodule

Verilog Model of a 4 X 1 Multiplexer using 2 X 1 Multiplexers

module mux41(ip, sel, op);
input [0:3] ip;
input [1:0] sel;
output op;
wire i1, i2;
mux21 m1(ip[0], ip[1],sel[0], i1);
mux21 m2(ip[2], ip[3],sel[0], i2);
mux21 m3(i1, i2,sel[1], op);
endmodule

Verilog Model of a 16 X 1 Multiplexer using 4 X 1 Multiplexer

module mux161(ip, sel, op);
input [0:15] ip;
input [3:0] sel;
output op;
wire [0:3] s;
mux41 m11 (ip[0:3], sel[1:0], s[0]);
mux41 m12 (ip[4:7], sel[1:0], s[1]);
mux41 m13 (ip[8:11], sel[1:0], s[2]);
mux41 m14 (ip[12:15], sel[1:0], s[3]);
mux41 m15 (s, sel[3:2], op);
endmodule
Testbench Verilog Model of a 16 X 1 Multiplexer
module mux16test;
reg [0:5] ip;
reg [3:0] sel;
wire op; integer i;

mux161 m1(ip, sel, op);

initial
begin
ip = 16’b1010101010101010; sel=4’d0;
for(i=0;i<16;i=i+1) #10 sel=i;
#10 $finish;
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Verilog Model of a 1-bit Full Adder
module fadd1(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;

assign sum = a^b^cin;

assign cout = (a&b)|(b&cin)|(cin&a);
endmodule

Verilog Model of a 4-Bit Fulladder using 1-bit Fulladders

module fadd4(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire c1,c2,c3;

fadd1 f1(a[0], b[0], cin, sum[0], c1);

fadd1 f2(a[1], b[1], c1, sum[1], c2);
fadd1 f3(a[2], b[2], c2, sum[2], c3);
fadd1 f4(a[3], b[3], c3, sum[3], cout);
endmodule
Verilog Model of a 4-Bit Substractors using 1-bit Fulladders

module fadd4(a,b,m,sum,cout);
input [3:0] a,b;
input m;
output [3:0] sum;
output cout;
wire c1,c2,c3;
wire [3:0] bxor;

assign bxor = b ^ {m,m,m,m};

fadd1 f1(a[0], bxor[0], m, sum[0], c1);

fadd1 f2(a[1], bxor[1], c1, sum[1], c2);
fadd1 f3(a[2], bxor[2], c2, sum[2], c3);
fadd1 f4(a[3], bxor[3], c3, sum[3], cout);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Testbench Verilog Model for a 4-Bit Fulladder

`timescale 1ns/1ps
module fadd4test;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;

fadd4 f1(a, b, cin, sum, cout);

initial
begin
a=4’d8; b = 4’d3; cin=1’b0;
#10 a=4’d8; b = 4’d3; cin=1’b1;
#10 a=4’d5; b = 4’d7; cin=1’b0;
#10 a=4’d5; b = 4’d7; cin=1’b1;
#10 $finish;
end

initial
$monitor(“Time=%d a=%b b=%b cin=%b sum=%b cout=%b”, $time, a,
b,cin, sum, cout);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 2 X 4 Decoder

module dec24(w,y,en);
input [1:0] w;
input en;
output [0:3] y;
reg [0:3] y;

always @(w or en)

begin
case({en,w})
3’b100 : y = 4’b1000;
3’b101 : y = 4’b0100;
3’b110 : y = 4’b0010;
3’b111 : y = 4’b0001;
default : y = 4’b0000;
endcase
end
endmodule

Verilog Model of a 4 X 16 Decoder

module dec416(w,y,en)
input [3:0] w;
input en;
output [0:15] y;
wire [0:3] m;

dec24 dec1 (w[3:2], m[0:3], en);

dec24 dec2 (w[1:0], y[0:3], m[0]);
dec24 dec3 (w[1:0], y[4:7], m[1]);
dec24 dec4 (w[1:0], m[8:11], m[2]);
dec24 dec5 (w[1:0], m[12:15], m[3]);
endmodule

Testbench Verilog Model of a 4 X 16 Decoder

module dectest;
reg [3:0] w;
reg en;
wire [0:15] y;
integer i;

dec416 d1(w, y, en);

initial
begin
en = 1’b0; w = 4’b 5;
#10 en = 1’b0; w = 4’b 8;
#10 for(i=0; i<16; i=i+1) #10 w=i;
#10 $finish;
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
% Testbench Verilog Model of a 4 X 16 Decoder
`timescale 1ns/1ps
module dectest;
reg [3:0] w;
reg en;
wire [0:15] y;

dec416(w, y, en);

initial
begin
en=1’b1;
w=4’d0;
#10 w=4’d1;
#10 w=4’d2;
#10 w=4’d3;
#10 w=4’d4;
#10 w=4’d5;
#10 w=4’d6;
#10 w=4’d7;
#10 w=4’d8;
#10 w=4’d9;
#10 w=4’d10;
#10 w=4’d11;
#10 w=4’d12;
#10 w=4’d13;
#10 w=4’d14;
#10 w=4’d15;
#10 en=1’b0;
#10 $finish;
end

initial
$monitor(“Time=%b en=%b w=%b y=%b”, $time, en, w, y);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 1-bit comparator

module comp1(ai, bi, apgt, bpgt, agt, bgt);

input ai, bi, apgt, bpgt;
output agt, bgt;
reg agt, bgt;

always @(*)
begin
if(apgt!=bpgt)
begin agt = apgt; bgt = bpgt; end
else
begin agt = ai; bgt = bi; end
end
endmodule
Verilog Model of a 5-bit Comparator using 1-bit Comparators

module comp5(a,b,agt,bgt);
input [4:0] a,b;
output agt,bgt;
wire [4:1] acarry, bcarry;

comp1 c1(a[4], b[4], 1’b1, 1’b1, acarry[4], bcarry[4]);

comp1 c2(a[3], b[3], acarry[4], bcarry[4], acarry[3], bcarry[3]);
comp1 c3(a[2], b[2], acarry[3], bcarry[3], acarry[2], bcarry[2]);
comp1 c4(a[1], b[1], acarry[2], bcarry[2], acarry[1], bcarry[1]);
comp1 c5(a[0], b[0], acarry[1], bcarry[1], agt, bgt);
endmodule
Testbench Verilog Model of a 5-Bit Comparator

`timescale 1ns/1ps
module comptest;
reg [4:0] a, b;
wire agt, bgt;

comp5 c1(a, b, agt, bgt);

initial
begin
a=5’d10; b=5’d2;
#10 a=5’d5; b=5’d5;
#10 a=5’d3; b=5’d7;
#10 a=5’d12; b=5’d4;
#10 a=5’d6; b=5’d6;
#10 a=5’d4; b=5’d8;
#10 $finish;
end

initial $monitor(“Time=%d a=%d b=%d agt=%d bgt=%d”, $time,

a,b,agt,bgt);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Student Exercise

1. Model a 4 X 16 decoder using two 3 X 8 Decoders (each with enable input)

2. Realize a 4-bit X 4-bit Array multiplier with 1-bit HAs and 1-bit FAs using
Structural Modeling
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab -V
Modeling and Simulation of Sequential Logic Elements in
Verilog
Theory:
A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states. The major differences among
various types of storage elements are in the number of inputs they possess and in the manner in which
the inputs affect the binary state.

Latches and Flipflops:

Storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops. Latches are said to be level sensitive
devices; flip-flops are edge-sensitive devices. The two types of storage elements are related because
latches are the basic circuits from which all flip-flops are constructed. Although latches are useful for
storing binary information and for the design of asynchronous sequential circuits, they are not practical
for use as storage elements in synchronous sequential circuits.
The characteristic tables of the flipflops are given below

D-Latch
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Register: A register is a group of flip‐flops, each one of which shares a common clock and is capable
of storing one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of storing
n bits of binary information.

Counters: A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter. The input pulses may be clock pulses, or they may originate from some
external source and may occur at a fixed interval of time or at random. The sequence of states may
follow the binary number sequence or any other sequence of states. A counter that follows the binary
number sequence is called a binary counter. An n ‐bit binary counter consists of n flip‐flops and can
count in binary from 0 through 2n - 1.

Counters are available in two categories: ripple counters and synchronous counters. In a ripple counter,
a flip‐flop output transition serves as a source for triggering other flip‐flops. In other words, the C input
of some or all flip‐flops are triggered, not by the common clock pulses, but rather by the transition that
occurs in other flip‐flop outputs. In a synchronous counter, the C inputs of all flip‐flops receive the
common clock.

Shift Registers: A register capable of shifting the binary information held in each cell to its
neighboring cell, in a selected direction, is called a shift register. The logical configuration of a shift
register consists of a chain of flip‐flops in cascade, with the output of one flip‐flop connected to the
input of the next flip‐flop. All flip‐flops receive common clock pulses, which activate the shift of data
from one stage to the next.

Universal Shift Register: A register having both shifts and parallel‐load capabilities, is referred to as a
universal shift register If the flip‐flop outputs of a shift register are accessible, then information entered
serially by shifting can be taken out in parallel from the outputs of the flip‐flops. If a parallel load
capability is added to a shift register, then data entered in parallel can be taken out
in serial fashion by shifting the data stored in the register.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Verilog Model of a Gated D-Latch
module dlatch(d, clk, q);
input d, clk;
output q;
reg q;

always@(d or clk)
begin
if(clk)
q = d;
end
endmodule
Verilog Model of a D Flip-Flop
module dff(d, clk, q);
input d, clk;
output q;
reg q;

always@(posedge clk)
q = d;
endmodule
Testbench Verilog Model of a Gated –D Latch
module dtest;
reg d, clk;
wire q1, q2;

dlatch d1(d, clk, q1);

dff d2(d, clk, q2);

always
begin
#3 d=1’b0;
#3 d=1’b1;
end

always
begin
#16 clk=1’b0;
#16 clk=1’b1;
end

initial
begin
#200 $finish;
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a D Flip-Flop with asynchronous reset

module dff(d, clk, rst, q);
input d, clk, rst;
output q; reg q;

always@(posedge clk or negedge rst)

begin
if(!rst)
q=0;
else
q = d;
end
endmodule
Verilog Model of a D Flip-Flop with asynchronous reset and load input
module dff(d, clk, rst, ld, q);
input d, clk, rst, ld;
output q; reg q;

always@(posedge clk or negedge rst)

begin
if(!rst)
q=0;
else if(ld) q = d;
end
endmodule
Verilog Model of a D Flip-Flop with Synchronous Reset
module dff(d, clk, rst, q);
input d, clk, rst;
output q; reg q;

always@(posedge clk)
begin
if(!rst)
q=0;
else
q = d;
end
endmodule
Verilog Model of an 8-Bit Register with asynchronous reset
module regn(d, load, rst, clk, q);
input [7:0] d;
input load, rst, clk;
output [7:0] q;
reg [7:0] q;
always @(negedge rst or posedge clk)
begin
if(!rst)
q = 8’d0;
else if(load)
q = d;
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a JK Flip flop

module jkff(j, k, rst, clk, q);
input j, k, rst, clk;
output q;
reg state;
assign q = state;
always @(negedge rst or posedge clk)
begin
if(!rst)
state = 1’b0;
else if(j=1’b1 & k=1’b0)
state = 1’b1;
else if(j=1’b0& k=1’b1)
state = 1’b0;
else if(j=1’b1 & k=1’b1)
state = ~state;
end
endmodule

Verilog Model of a 4-Bit Ripple Counter (Structural Model) using JK Flip Flop
module ripcount(rst, clk, q);
input rst, clk;
inout [3:0] q;

jkff f1(1’b1, 1’b1, rst, clk, q[0]);

jkff f2(1’b1, 1’b1, rst, q[0], q[1]);
jkff f3(1’b1, 1’b1, rst, q[1], q[2]);
jkff f4(1’b1, 1’b1, rst, q[2], q[3]);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 4-bit Synchronous Counter with synchronous reset (Behavioral Model)

module syncount(rst, cen, clk, q);

input rst, cen, clk;
output reg [3:0] q;

always @(posedge clk)

begin
if(rst)
q =4’b000;
else if(cen)
q = q+4’d1;
end
endmodule

Verilog Model of a 4-bit Synchronous Counter using DFFs (Structural Model)

module syncount(rst, cen, clk, q);

input rst, cen, clk;
output reg [3:0] q;
wire d[3:0];

assign d[3] = q[3] ^ (q[2] & q[1] & q[0]);

assign d[2] = q[2] ^ (q[1] & q[0]);
assign d[1] = q[1] ^ q[0];
assign d[0] = ~q[0];

dff d1 (d[3], clk, rst, q[3]);

dff d2 (d[2], clk, rst, q[2]);
dff d3 (d[1], clk, rst, q[1]);
dff d4 (d[0], clk, rst, q[0]);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model a 4-bit Universal Shift Register (Behavioral Modeling)

module univsh(d, clk, sel, rst, serin, serout);
input [3:0] d;
input [1:0] sel;
input clk, serin, ;
output serout;
output reg [3:0] q;

always @(posedge clk or negedge rst)

begin
if(!rst)
q = 5’b00000;
else if(sel == 2’b00)
q = d;
else if(sel == 2’b01)
q = {serin, q[3:1]};
else if(sel == 2’b10)
q = {q[2:0], serin};
else
q = q;
end
assign serout = q[0];
endmodule
Verilog Model of a 4-bit Universal Shift Register using D-Flip Flops(Structural Model)
module univsh(d, clk, sel, rst, serin, serout);
input [3:0] d;
input [1:0] sel;
input clk, serin, ;
output serout;
inout [3:0] q;
wire [3:0] ff;

mux41 m3 (d[3], serin, q[2], q[3], sel[1], sel[0], ff[3]);

mux41 m2 (d[2], q[3], q[1], q[2], sel[1], sel[0], ff[2]);
mux41 m1 (d[1], q[2], q[0], q[1], sel[1], sel[0], ff[1]);
mux41 m0 (d[0], q[1], serin, q[0], sel[1], sel[0], ff[0]);

dff d1 (ff[3], clk, rst, q[3]);

dff d2 (ff[2], clk, rst, q[2]);
dff d3 (ff[1], clk, rst, q[1]);
dff d4 (ff[0], clk, rst, q[0]);
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Student Exercises
1. Develop the Verilog Model of a MOD-12 Synchronous Counter using D Flip Flops and
appropriate dataflow statements
2. Develop the Verilog Model of a MOD-12 Synchronous Counter using JK Flip Flops and
appropriate dataflow statements
3. Develop the Behavioral Verilog Model of a MOD-12 Synchronous Counter using always
statements
4. Model a Ring Counter and Johnson Counter using Behvavioral & Structural Modeling (using
DFFs)
5. Model a 4-Bit Up counter with parallel load
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Model a 64-Word, 16-Bit RAM using Verilog

module ram(clk, addr, wrb, din, dout);

input clk;
input [5:0] addr;
input wrb;
input [16:0] din;
output [15:0] dout;
reg [15:0] men[63:0];

always @(posedge clk)

if(~wrb) mem[addr] = din;

assign din = mem[addr];

endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab -VI
Synthesis and Implementation of Sequential Logic Circuits in
Verilog

Tutorial for Generation and Instantiation of Clock Generator Module

5-2. Launch the clocking wizard from the IP Catalog of Vivado and generate the clock
core with input frequency of 100.00 MHz and two output clocks of 100.000 MHZ
each.

5-2-1. Click on IP Catalog in the Flow Navigator pane.

The IP Catalog will open in the auxiliary pane.

5-2-2. Expand the FPGA Features and Design > Clocking sub-folders and double-click on the Clocking
Wizard entry.

Figure 2. Accessing the clocking wizard

The clocking wizard will open.

5-2-3. Change the core name to clk_core. Make sure that the Primary input clock frequency is 100.000 MHz
and the primitive used is MMCM.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Figure 3. The clocking wizard

5-2-4. Select the Output Clocks tab. Click on the check box to enable the second clock output. Make sure that
the requested output frequency is 100 MHz for both clocks.

Figure 4. Setting output clocks

5-2-5. Click on the Summary tab and check the information.

 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Figure 5. Summary page of the clock core being generated

5-2-6. Click OK to see the Generate Output Products form.

Figure 6. Generate output products form

5-2-7. Click on Generate to generate the output products including the instantiation template. Click OK to
proceed.

5-3. Instantiate the generated clock core.

5-3-1. Select the IP Sources tab in the Sources pane.

5-3-2. Expand the IP (2) branch. Notice the two IP entries. The char_fifo IP is the core that was included while
creating project. The second core clk_core is the one that you have generated.

5-3-3. Expand clk_core > Instantiation Template and double-click on clk_core.veo to see the instantiation
template.

5-3-4. Copy lines 71 through 80 and paste them at or around line 79 of the clk_gen.v file.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
5-3-5. Change the instance name and net names to as shown in the figure below to match the names of
existing signals in the design.

Figure 7. Assigning instance name and net conenctions

5-3-6. Select File > Save File to save clk_gen.v

5-3-7. Select the Hierarchy tab and expand the wave_gen > clk_gen_i0 hierarchy and verify that clk_core.xci
is in the hierarchy. The IP has a bordered yellow square icon next to it.

Figure 8. The clk_core instantiated and shown in the hierarchy

 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a 4-Bit Counter

`timescale 1ns / 1ps

module count4(input clk, output [3:0] q);

wire tempclk, tempclk1;
reg [21:0] temp1;
reg [3:0] temp2;

clk_wiz_0 (clk, tempclk, locked);

always @(posedge tempclk) temp1 = temp1 + 22'd1;
assign tempclk1 = temp1[21];
always @(posedge tempclk1) temp2 = temp2 + 4'd1;
assign q = temp2;
endmodule
Nexys4 DDR Pin Assignments
## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {
clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5}
[get_ports {clk}];

## LEDs
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {
q[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports {
q[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports {
q[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {
q[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

`timescale 1ns / 1ps

module count4_sseg(input clk, output [7:0] SSEG_CA, output [7:0] SSEG_AN);
wire tempclk, tempclk1;
reg [21:0] temp1;
reg [2:0] temp2;
reg [7:0] SSEG_CA;

clk_wiz_0 (clk, tempclk, locked);

always @(posedge tempclk) temp1 = temp1 + 22'd1;
assign tempclk1 = temp1[21];
always @(posedge tempclk1) temp2 = temp2 + 3'd1;

assign SSEG_AN = 8'b11111110;

always @(temp2)
begin
case(temp2)
3'd0: SSEG_CA = 8'b11000000;
3'd1: SSEG_CA = 8'b11111001;
3'd2: SSEG_CA = 8'b10100100;
3'd3: SSEG_CA = 8'b10110000;
3'd4: SSEG_CA = 8'b10011001;
3'd5: SSEG_CA = 8'b10010010;
3'd6: SSEG_CA = 8'b10000010;
3'd7: SSEG_CA = 8'b11111000;
default: SSEG_CA = 8'b11111000;
endcase
end

endmodule

Nexys 4 DDR Pin Assignments

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];
#IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports
{clk}];

##7 segment display

set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[6] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {

SSEG_AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a Minute-Second Clock

`timescale 1ns / 1ps
module minsec(input clk, output [7:0] SSEG_CA, output [7:0] SSEG_AN);
wire tempclk, tempclk1, tempclk4h;
reg [21:0] temp1;
reg [2:0] temp2;
reg [7:0] SSEG_CA;
reg [7:0] SSEG_AN;

reg [3:0] d0, d1, d2, d3, outdig;

reg [1:0] cnt2;

clk_wiz_0 (clk, tempclk, locked);

always @(posedge tempclk) temp1 = temp1 + 22'd1;
assign tempclk1 = temp1[21];
assign tempclk4h = temp1[13];

always @(posedge tempclk1)

begin
if(d0==4'd9) d0 = 4'd0;
else d0 = d0 + 4'd1;
end

always @(posedge tempclk1)

begin
if(d0==4'd9)
if(d1==4'd5) d1 = 4'd0;
else d1 = d1 + 4'd1;
end
always @(posedge tempclk1)
begin
if(d1==4'd5 && d0==4'd9)
if(d2==4'd9) d2 = 4'd0;
else d2 = d2 + 4'd1;
end
always @(posedge tempclk1)
begin
if(d2==4'd9 && d1==4'd5 && d0==4'd9)
if(d3==4'd5) d3 = 4'd0;
else d3 = d3 + 4'd1;
end

always @(posedge tempclk4h) cnt2 = cnt2 + 2'd1;

always @(cnt2, d0, d1, d2, d3)
begin
case(cnt2)
2'd0: begin outdig=d0; SSEG_AN=8'b11111110; end
2'd1: begin outdig=d1; SSEG_AN=8'b11111101; end
2'd2: begin outdig=d2; SSEG_AN=8'b11111011; end
2'd3: begin outdig=d3; SSEG_AN=8'b11110111; end
default: begin outdig=d0; SSEG_AN=8'b11111110; end
endcase
end
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

always @(outdig)
begin
case(outdig)
4'd0: SSEG_CA = 8'b11000000;
4'd1: SSEG_CA = 8'b11111001;
4'd2: SSEG_CA = 8'b10100100;
4'd3: SSEG_CA = 8'b10110000;
4'd4: SSEG_CA = 8'b10011001;
4'd5: SSEG_CA = 8'b10010010;
4'd6: SSEG_CA = 8'b10000010;
4'd7: SSEG_CA = 8'b11111000;
4'd8: SSEG_CA = 8'b10000000;
4'd9: SSEG_CA = 8'b10010000;
default: SSEG_CA = 8'b11111000;
endcase
end

endmodule

Nexys 4 DDR Pin Assignments

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {
clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5}
[get_ports {clk}];

##7 segment display

set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[6] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_CA[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp

set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {

SSEG_AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports {
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
SSEG_AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports {
SSEG_AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab-VII
Modeling and Simulation of Finite State Machines
Theory:
Every sequential logic circuit consists of combinational logic circuit along with flip flops. The set of all the flip
flops can be thought of as a register and the various set of values taken by all the flip flops taken together
(register) can be named as states. We see that a sequential logic circuit essentially has two parts. First, a
combinational logic circuit that takes inputs and current state and generates the output and next state. Second, a
state register that accepts the nextstate and produces it at the output (as the current state) after the positive edge
of clock pulse. The behavior of the combinational logic circuit can be modeled using an always block along with
case statement (wherein the outputs for various input combinations are mentioned). The behavior of the state
register can be modeling as an n-bit register (if number of states <=2N) using always block

The most general model of a sequential circuit has inputs, outputs, and internal states. It is customary to
distinguish between two models of sequential circuits: the Mealy model and the Moore model.

In the Mealy model, the output is a function of both the present state and the input. In the Moore model, the
output is a function of only the present state. A circuit may have both types of outputs. The two models of a
sequential circuit are commonly referred to as a finite state machine, abbreviated FSM. The Mealy model of a
sequential circuit is referred to as a Mealy FSM or Mealy machine. The Moore model is referred to as a Moore
FSM or Moore machine.

In a Moore model, the outputs of the sequential circuit are synchronized with the clock, because they depend
only on flip-flop outputs that are synchronized with the clock. In a Mealy model, the outputs may change if the
inputs change during the clock cycle. Moreover, the outputs may have momentary false values because of the
delay encountered from the time that the inputs change and the time that the flip-flop outputs change. In order to
synchronize a Mealy-type circuit, the inputs of the sequential circuit must be synchronized with the clock and the
outputs must be sampled immediately before the clock edge. The inputs are changed at the inactive edge of the
clock to ensure that the inputs to the flip-flops stabilize before the active edge of the clock occurs. Thus, the
output of the Mealy machine is the value that is present immediately before the active edge of the clock.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of a Three 1’s Sequence Detector using a Moore State Machine
module moore(ip, clk, op, rst);
input ip, clk, rst;
output op;
reg op;

parameter S0=0, S1=1, S2=2, S3=3;

reg [0:1] cs, ns;

always @(posedge clk or posedge rst) // State Register

begin
if(rst)
cs = S0;
else
cs = ns;
end

always @(cs) //Combinational Logic that implements state logic

case(cs)
S0: begin op =0;
if(ip) ns = S1; else ns = S0; end
S1: begin op =0;
if(ip) ns = S2; else ns = S0; end
S2: begin op =0;
if(ip) ns = S3; else ns = S0; end
S3: begin op =1;
if(ip) ns = S3; else ns = S0; end
default: op = 0; ns = S0;
endcase
end
endmodule
Alternate Verilog Description of the above Moore State Machine

module moore(ip, clk, op);

input ip, clk;
output op;
reg op;

parameter S0=0, S1=1, S2=2, S3=3;

reg [0:1] cs;
always @(posedge clk) //Combinational Logic that implements state logic
case(cs)
S0: if(ip) cs = S1; else cs = S0;
S1: if(ip) cs = S2; else cs = S0;
S2: if(ip) cs = S3; else cs = S0;
S3: if(ip) cs = S3; else cs = S0;
default: cs = S0;
endcase
end
assign op = (cs==S0) ? 1 : 0;
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Verilog Model of a 4-Bit Ring Counter implemented as a Moore State Machine
module(clk, rst, q);
input clk, rst;
output [3:0] q;
reg [3:0] cs, ns;

always @(posedge clk or negedge rst) // State register that hold cs

begin
if(!rst) cs = 4’b1000; else cs = ns;
end

always @(cs) // Combinational logic that generates ns from cs

begin
case(cs)
4’b1000: ns = 4’b0100;
4’b0100: ns = 4’b0010;
4’b0010: ns = 4’b0001;
4’b0001: ns = 4’b1000;
default: ns = 4’b1000;
endcase
end
assign q = cs;
endmodule

Student Exercises:
1. Model a 3-Bit Counter as per the FSM Below

2. Model a sequence generator for generating the sequence 3, 7, 4, 6, 5, 1

3. Model a 3-bit Johnson Counter as a Moore State Machine
4. Derive the sequence detector for the sequence “101” and model it as a Moore State Machine
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

5. Model the rate ½ convolutional encoder as a Mealy State machine

 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Lab-VIII
Design and Modeling of Synchronous Digital Systems in Verilog
Design Project – I: 4 X 4 Bit Multiplier Design

Figure 1: Block Diagram for Binary Multiplier

Figure 2: State Graph for Binary Multiplier Control

 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model for Control Unit

module control(clk,st,ld,sh,m,done );
input clk, m, st;
output ld, sh, done;
reg [3:0] cs,ns;
reg ld, sh, done;

always@(posedge clk)
cs = ns;
always@(cs or st or m)
begin
case(cs)
4'd0 : if(st)
begin ns = 4'd1; ld = 1'b1; sh = 1'b0; done =1'b0;
end
else
begin ns = 4'd0; ld = 1'b0; sh = 1'b0; done =1'b0;end
4'd1 : if(m)
begin ns = 4'd2; ld = 1'b1; sh = 1'b0; done =1'b0;end
else
begin ns = 4'd3; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd2 : begin ns = 4'd3; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd3 : if(m)
begin ns = 4'd4; ld = 1'b1; sh = 1'b0; done =1'b0;end
else
begin ns = 4'd5; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd4 : begin ns = 4'd5; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd5 : if(m)
begin ns = 4'd6; ld = 1'b1; sh = 1'b0; done =1'b0;end
else
begin ns = 4'd7; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd6 : begin ns = 4'd7; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd7 : if(m)
begin ns = 4'd8; ld = 1'b1; sh = 1'b0; done =1'b0;end
else
begin ns = 4'd9; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd8 : begin ns = 4'd9; ld = 1'b0; sh = 1'b1; done =1'b0;end

4'd9 : begin ns = 4'd0; ld = 1'b0; sh = 1'b0; done =1'b1;end
default: begin ns = 4'd0; ld = 1'b0; sh = 1'b0; end
endcase
end
endmodule
Verilog Model for 1-Bit Full Adder

module fa1(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
assign sum = a ^ b ^ cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule
Verilog Model for 4-bit Full Adder
module fa4(a,b,sum,cout);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
output cout;
wire c1, c2, c3;

fa1 f1(a[0], b[0], 1'b0, sum[0], c1);

fa1 f2(a[1], b[1], c1, sum[1], c2);
fa1 f3(a[2], b[2], c2, sum[2], c3);
fa1 f4(a[3], b[3], c3, sum[3], cout);
endmodule
Verilog Model for Shift Register
module shireg(d,q,ld,sh,clk);
input [8:0] d;
output [8:0] q;
input ld;
input sh;
input clk;
reg [8:0]q;
always @(posedge clk)
begin
if(ld)
q = d;
else if(sh)
q = {1'b0,q[8:1]};
end
endmodule
Verilog Model for Final Multiplier
module mul(x,y,prod,st,clk,done);
input [3:0] x;
input [3:0] y;
output [8:0] prod;
output done;
input st;
input clk;
wire [8:0] tempd;
wire [8:0] q;
wire [3:0] sum;
wire cout;
wire ld, sh, m;

assign m = q[0];
assign tempd = st ? {5'b00000,y} : {cout,sum, q[3:0]};
shireg s1 (tempd, q,ld,sh,clk);
fa4 f1 (x,q[7:4] ,sum, cout);
control c1 (clk,st,ld,sh,m,done);
assign prod = q;
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Design Project – II: Greatest Common Divisor (GCD) calculator
The black box view and algorithmic description of the GCD processor is shown below
int x, y;
while (1)
{
while (!st);
x = xi;
y = yi;
while(x != y) st xi yi
{
if (x < y) GCD
y = y - x;
else zout
x = x - y;
}
zout = x;
}

Datapath and Controlpath Design:

The steps for designing the datapath and control path are listed below
 Create a register for any declared variable
 Create a functional unit for each arithmetic operation
 Connect the ports, registers and functional units
 Based on reads and writes
 Use multiplexors for multiple sources
 Create unique identifier
 for each datapath component control input and output
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model for a 4-Bit Register

module reg4(d, clk, rst, ld, q);
input [3:0] d;
input clk, rst, ld;
output reg [3:0] q;

always @(posedge clk or negedge rst)

begin
if(!rst) q = 4'd0;
else if (ld) q = d;
end
endmodule

Verilog Model for the Control Unit

module control(clk, rst, st, xneqy, xgty, xld, yld, zld, xsel, ysel, done);
input clk, rst, st, xneqy, xgty;
output reg xld, yld, zld, xsel, ysel, done;

reg [2:0] cst, nst;

always @(posedge clk or negedge rst)

begin
if (!rst) cst = 3'd0;
else cst = nst;
end

always @(cst or xneqy or xgty or st)

begin
nst=3'd0; xsel=1'b0; ysel=1'b0; xld=1'b0; yld=1'b0; zld=1'b0;
done=1'b0;
case(cst)
3'd0: if(st) nst=3'd1; else nst=3'd0;
3'd1: begin nst=3'd2; xsel=1'b0; ysel=1'b0; xld=1'b1; yld=1'b1;
end
3'd2: begin if(xneqy) nst=3'd3; else nst=3'd6; end
3'd3: begin if(xgty) nst=3'd4; else nst=3'd5; end
3'd4: begin nst=3'd2; xsel=1'b1; xld =1'b1; end
3'd5: begin nst=3'd2; ysel=1'b1; yld =1'b1; end
3'd6: begin nst=3'd0; zld=1'b1; done = 1'b1; end
default: nst=3'd0;
endcase
end
endmodule
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam

Verilog Model of the Final GCD Processor

module gcd(xi, yi, st, mclk, rst, zout, done);
input [3:0] xi, yi;
input st, mclk, rst;
output [3:0] zout;
output done;
wire clk, locked;

wire xld, yld, zld, xsel, ysel, xneqy, xgty;

wire [3:0] x, y, xmuxout, ymuxout, xmy, ymx;

clk_wiz_0 c2(mclk, clk, locked);

reg4 xreg(xmuxout, clk, rst, xld, x);
reg4 yreg(ymuxout, clk, rst, yld, y);
reg4 zreg(x, clk, rst, zld, zout);

assign xmy = x-y;

assign ymx = y-x;
assign xneqy = (x!=y);
assign xgty = (x>y);
assign xmuxout = xsel ? xmy : xi;
assign ymuxout = ysel ? ymx : yi;

control c1 (clk, rst, st, xneqy, xgty, xld, yld, zld, xsel, ysel, done);
endmodule

Nexys 4 DDR Pin Assignments

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {
mclk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5}
[get_ports {mclk}];

##Switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports {
xi[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports {
xi[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports {
xi[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports {
xi[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]

set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports {

yi[0] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {
yi[1] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports {
yi[2] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports {
yi[3] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports {
st }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports {
rst }]; #IO_L21P_T3_DQS_14 Sch=sw[15]

## LEDs
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {
zout[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports {
zout[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports {
zout[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {
zout[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports {
done] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Design Project-III: VGA Controller
VGA (video graphics array) is a video display standard introduced in the late 1980s in IBM PCs and is widely
supported by PC graphics hardware and monitors. We discuss the design of a basic eight-color 640-by-480
resolution interface for CRT (cathode ray tube) monitors.

The conceptual sketch of a monochrome CRT monitor is shown in figure below. The electron gun (cathode)
generates a focused electron beam, which traverses a vacuum tube and eventually hits the phosphorescent screen,
Light is emitted at the instant that electrons hit a phosphor dot on the screen. The intensity of the electron beam
and the brightness of the dot are determined by the voltage level of the external video input signal, labeled mono
in figure below. The mono signal is an analog signal whose voltage level is between 0 and 0.7 V.

A vertical deflection coil and a horizontal deflection coil outside the tube produce magnetic fields to control how
the electron beam travels and to determine where on the screen the electrons hit. In today’s monitors, the electron
beam traverses (i.e., scans) the screen systematically in a fixed pattern, from left to right and from top to bottom,
as shown in figure below.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
The monitor's internal oscillators and amplifiers generate sawtooth waveforms to control the two deflection coils.
For example, the electron beam moves from the left edge to the right edge as the voltage applied to the horizontal
deflection coil gradually increases. After reaching the right edge, the beam returns rapidly to the left edge (i.e.,
retraces) when the voltage changes to 0. The relationship between the sawtooth waveform and the scan is shown
in Figure 12.4. Two external synchronization signals, hsync and vsync, control generation of the sawtooth
waveforms. These signals are digital signals. The relationship between the hsync signal and the horizontal
sawtooth is also shown in Figure 12.4. Note that the I' 1 and "0" periods of the hsync signal correspond to the
rising and falling ramps of the sawtooth waveform. The basic operation of a color CRT is similar except that it
has three electron beams, which are projected to the red, green, and blue phosphor dots on the screen. The three
dots are combined to form a pixel. We can adjust the voltage levels of the three video input signals to obtain the
desired pixel color.

Video Controller:
A video controller generates the synchronization signals and outputs data pixels serially. A simplified block diagram of a
VGA controller is shown in figure below. It contains a synchronization circuit, labeled vga-sync, and a pixel generation
circuit. The vga-sync circuit generates the timing and synchronization signals. The hsync and vsync signals are connected to
the VGA port to control the horizontal and vertical scans of the monitor. The two signals are decoded from the internal
counters, whose outputs are the pixel-x and pixel-y signals. The p i x e l x and pixel-y signals indicate the relative positions
of the scans and essentially specify the location of the current pixel. The vga-sync circuit also generates the video-on signal
to indicate whether to enable or disable the display. The pixel generation circuit generates the three video signals, which are
collectively referred to as the rgb signal. A color value is obtained according to the current coordinates of the pixel (the
pixel-x and pixel-y signals) and the external control and data signals.

VGA Controller:
The video synchronization circuit generates the hsync signal, which specifies the required time to
traverse (scan) a row, and the vsync signal, which specifies the required time to traverse (scan) the
entire screen. Subsequent discussions are based on a 640-by-480 VGA screen with a 25-MHz pixel
rate, which means that 25M pixels are processed in a second. Note that this resolution is also know as
the VGA mode. The screen of a CRT monitor usually includes a small black border, as shown at the
top of figure below. The middle rectangle is the visible portion. Note that the coordinate of the vertical
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
axis increases downward. The coordinates of the top-left and bottom-right corners are (0,O) and
(639,479), respectively.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Horizontal Synchronization:
A detailed timing diagram of one horizontal scan is shown in Figure 12.4. A period of the hsync signal
contains 800 pixels and can be divided into four regions
 Display: region where the pixels are actually displayed on the screen. The length of this region
is 640 pixels.
 Retrace: region in which the electron beams return to the left edge. The video signal should be
disabled (i.e., black), and the length of this region is 96 pixels.
 Right border: region that forms the right border of the display region. It is also known as the
front porch (i.e., porch before retrace). The video signal should be disabled, and the length of
this region is 16 pixels.
 Left border: region that forms the left border of the display region. It is also known as the
backporch (i.e., porch after retrace). The video signal should be disabled, and the length of this
region is 48 pixels.
The hsync signal can be obtained by a special mod-800 counter and a decoding circuit. The counts are
marked on the top of the hsync signal in Figure 12.4. We intentionally start the counting from the
beginning of the display region. This allows us to use the counter output as the horizontal (x-axis)
coordinate. This output constitutes the pixel-x signal. The hsync signal goes low when the counter’s
output is between 656 and 75 1. Note that the CRT monitor should be black in the right and left borders
and during retrace. We use the h-video-on signal to indicate whether the current horizontal coordinate
is in the displayable region. It is asserted only when the pixel count is smaller than 640.

Vertical Synchronization:
During the vertical scan, the electron beams move gradually from top to bottom and then return to the
top. This corresponds to the time required to refresh the entire screen. The format of the vsync signal is
similar to that of the hsync signal, as shown in Figure 12.5. The time unit of the movement is
represented in terms of horizontal scan lines. A period of the vsync signal is 525 lines and can be
divided into four regions:
 Display: region where the horizontal lines are actually displayed on the screen. The length of
this region is 480 lines.
 Retrace: region that the electron beams return to the top of the screen. The video signal should
be disabled, and the length of this region is 2 lines.
 Bottom border: region that forms the bottom border of the display region. It is also known as
thefrontporch (i.e., porch before retrace). The video signal should be disabled, and the length of
this region is 10 lines.
 Top border: region that forms the top border of the display region. It is also known as the
backporch (i,e,, porch after retrace). The video signal should be disabled, and the length of this
region is 33 lines.

As in the horizontal scan, the lengths of the top and bottom borders may vary for different
brands of monitors. The vsync signal can be obtained by a special mod-525 counter and a decoding
circuit. Again, we intentionally start counting from the beginning of the display region. This allows us
to use the counter output as the vertical (y-axis) coordinate. This output constitutes the pixel-y signal.
The vsync signal goes low when the line count is 490 or 491. As in the horizontal scan, we use the v-
video-on signal to indicate whether the current vertical coordinate is in the displayable region. It is
asserted only when the line count is smaller than 480.
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
Description of HDL Implementation of VGA Synchronizer
The function of the vga-sync circuit is discussed above. If the frequency of the system clock is 25 MHz,
the circuit can be implemented by two special counters: a mod-800 counter to keep track of the
horizontal scan and a mod-525 counter to keep track of the vertical scan.

Since our designs generally use the 50-MHz oscillator of the prototyping board, the system clock rate is
twice the pixel rate. Instead of creating a separate 25-MHz clock domain and violating the synchronous
design methodology, we can generate a 25-MHz enable tick to enable or pause the counting. The tick is
also routed to the p-tick port as an output signal to coordinate operation of the pixel generation circuit.
The HDL code is shown below. It consists of a mod-2 counter to generate the 25-MHz enable tick and
two counters for the horizontal and vertical scans. We use two status signals, h-end and v-end, to
indicate completion of the horizontal and vertical scans. The values of various regions of the horizontal
and vertical scans are defined as constants. They can be easily modified if a different resolution or
refresh rate is used. To remove potential glitches, output buffers are inserted for the hsync and vsync
signals. This leads to a one-clock-cycle delay. We should add a similar buffer for the rgb signal in the
pixel generation circuit to compensate for the delay.

Description of HDL Implementation of the VGA Testing Circuit

To verify operation of the synchronization circuit, we can connect the rgb signal to three switches. The
entire visible region should be turned on with a single color. We can go through the eight possible
combinations and check the colors defined in Table below. The HDL code is shown below. As
mentioned previously, an output buffer is added for the rgb signal
Three-bit VGA color combinations

Verilog Model of the VGA Synchronizer

module vga_sync
(
input wire clk, reset,
output wire hsync, vsync, video_on, p_tick,
output wire [9:0] pixel_x, pixel_y
);

// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48 ; // h. front (left) border
localparam HB = 16 ; // h. back (right) border
localparam HR = 96 ; // h. retrace
localparam VD = 480; // vertical display area
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
localparam VF = 10; // v. front (top) border
localparam VB = 33; // v. back (bottom) border
localparam VR = 2; // v. retrace

// mod-2 counter
reg mod2_reg;
wire mod2_next;
// sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
// output buffer
reg v_sync_reg, h_sync_reg;
wire v_sync_next, h_sync_next;
// status signal
wire h_end, v_end, pixel_tick;

// body
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
mod2_reg <= 1'b0;
v_count_reg <= 0;
h_count_reg <= 0;
v_sync_reg <= 1'b0;
h_sync_reg <= 1'b0;
end
else
begin
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end

// mod-2 circuit to generate 25 MHz enable tick

assign mod2_next = ~mod2_reg;
assign pixel_tick = mod2_reg;

// status signals
// end of horizontal counter (799)
assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
// end of vertical counter (524)
assign v_end = (v_count_reg==(VD+VF+VB+VR-1));

// next-state logic of mod-800 horizontal sync counter

always @*
if (pixel_tick) // 25 MHz pulse
if (h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1;
else
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
h_count_next = h_count_reg;

// next-state logic of mod-525 vertical sync counter

always @*
if (pixel_tick & h_end)
if (v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1;
else
v_count_next = v_count_reg;

// horizontal and vertical sync, buffered to avoid glitch

// h_sync_next asserted between 656 and 751
assign h_sync_next = (h_count_reg>=(HD+HB) &&
h_count_reg<=(HD+HB+HR-1));
// vh_sync_next asserted between 490 and 491
assign v_sync_next = (v_count_reg>=(VD+VB) &&
v_count_reg<=(VD+VB+VR-1));

// video on/off
assign video_on = (h_count_reg<HD) && (v_count_reg<VD);

// output
assign hsync = h_sync_reg;
assign vsync = v_sync_reg;
assign pixel_x = h_count_reg;
assign pixel_y = v_count_reg;
assign p_tick = pixel_tick;

endmodule

Verilog Model of the Top Level VGA Tester

module vga_test
(
input wire mclk, reset,
input wire [11:0] sw,
output wire hsync, vsync,
output wire [3:0] red,
output wire [3:0] green,
output wire [3:0] blue
);

//signal declaration
reg [11:0] rgb_reg;
wire video_on;
wire clk, locked;
// instantiate vga sync circuit
clk_wiz_0 c1(mclk, clk, locked);
vga_sync vsync_unit
(.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
.video_on(video_on), .p_tick(), .pixel_x(), .pixel_y());
// rgb buffer
always @(posedge clk, posedge reset)
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
if (reset)
rgb_reg <= 0;
else
rgb_reg <= sw;
// output
assign {red, green, blue} = (video_on) ? rgb_reg : 12'd0;

endmodule

#Nexys 4 DDR Pin Assignmets

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { mclk }];
#IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { mclk
}];

##Switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }];
#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }];
#IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }];
#IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }];
#IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }];
#IO_L5N_T0_D07_14 Sch=sw[7]
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }];
#IO_L24N_T3_34 Sch=sw[8]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }];
#IO_25_34 Sch=sw[9]
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10]
}]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11]
}]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { reset }];
#IO_L21P_T3_DQS_14 Sch=sw[15]

##VGA Connector
set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { red[0]
}]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { red[1]
}]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { red[2]
}]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { red[3]
}]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]

set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { green[0]

}]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { green[1]
 Department of Electronics and Communication Engineering
GITAM Institute of Technology, GITAM University, Visakhapatnam
}]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { green[2]
}]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { green[3]
}]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]

set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { blue[0]

}]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { blue[1]
}]; #IO_L4N_T0_35 Sch=vga_b[1]
set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { blue[2]
}]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { blue[3]
}]; #IO_L4P_T0_35 Sch=vga_b[3]

set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { hsync }];

#IO_L4P_T0_15 Sch=vga_hs
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsync }];
#IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs