FPGA & SoC System Development Course

From Basics to Embedded Systems

Description
This course is designed to equip you with the skills needed for an FPGA engineering role. It covers
a range of topics, from understanding the internal architecture of FPGAs to creating embedded
systems.
In this course, you will explore:
- The Xilinx FPGA workflow using the Zybo-Z7-10 development kit with its ZYNQ-7 FPGA
and the Vivado Design Suite.
- Spartan 6 FPGA with ISE Design Suite
- The Altera FPGA workflow using the DE10-Lite development kit with its MAX-10 FPGA and
the Quartus Prime Design Suite.

Teaching Style
All sessions and labs are recorded, allowing you to progress at your own pace and revisit the
content as many times as needed, anytime and anywhere. Additionally, there will be an online
live session whenever needed to address your questions and facilitate discussions about the
material, along with a WhatsApp group for following up with students and forming a community
where students can share knowledge and engage with one another.

Prerequisites
• Verilog.
• Basic C programming.

Instructor: Yousef Sherif

● Digital Verification Engineer @ ICpedia, Synopsys Constructor
● Former FPGA Design and Verification Engineer @ PyramidTech LLC
● Teaching Assistant @ The American University in Cairo
● LinkedIn Profile: https://www.linkedin.com/in/yousef-sherif-6343b219b/

Fees
3500 LE.

Registration Link:
https://forms.gle/tCWegKGKURQWbVbk9

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 1: ASIC Introduction (3.1 Hours)
Session Link: https://youtu.be/H2CnMzrnQv8?si=zPR04dIgvy5mqz_d

Content:
• Electronics History
• Moore’s Law
• Analog vs Digital Signals
• Implementation Approaches
o Custom
o Semicustom
▪ Cell-Based
• Standard Cells
• Macro Cells
▪ Array-Based
• Pre-Diffused Arrays
• Pre-Wired Arrays (FPGAs)
o Implementation Approaches Comparison
• ASIC Design Flow
o RTL Design
o Functional Verification
o Logic Synthesis
o Gate-Level Simulation (GLS)
o Static Timing Analysis (STA)
o Design for Testability (DFT)
o Formal Verification
o Place and Route (PnR) Flow
▪ Floor Planning
▪ Power Planning
▪ Placement
▪ Clock Tree Synthesis (CTS)
▪ Routing
▪ Sign-off
▪ Design Rule Check (DRC)
▪ Layout Versus Schematic (LVS)
▪ Electrical Rule Check (ERC)
▪ Electromigration and IR Drop (EMIR)
▪ Tapeout
• FPGA Design Flow
• Companies Classifications

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 2: FPGA Introduction (3 Hours)
Content (2 Hours):
• FPGA internal architecture.
• FPGA design flow.
• JTAG.
• FPGA vs. ASIC.
• FPGA vs. microcontroller.
• Vendors & tools.

Xilinx Labs (30 Minutes):

• Exploring the tool’s features through an AND gate.
o Project creation.
o Exploring the Zybo-Z7-10 development kit user manual.
o RTL simulation.
o Find design cells in elaboration / synthesis / implementation schematic views.
o Editing LUTs Boolean equations.
o Writing pin assignments using XDC constraints.
o Exploring Vivado’s language templates.
o Programming the FPGA.

Altera Labs (30 Minutes):

• Exploring the tool’s features through an AND gate.
o Project creation.
o Exploring the DE10-Lite development kit user manual.
o Understanding Quartus FPGA flow terms:
▪ Analysis & Synthesis.
▪ Atom netlist.
▪ Fitting.
o Editing compiler settings to change optimization goals.
o Analyzing reports.
o RTL / post-mapping / post-fitting schematic views.
o Making pin assignments using pin planner.
o Programming the FPGA.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 3: Clock Domain Crossing (2.5 Hours)
Content (1.7 Hours):
• Understanding System-on-Chips (SoC).
• Understanding Clock Domain Crossing (CDC).
• Synchronous vs asynchronous clock domains.
• CDC problems.
o Metastability.
▪ Understanding metastability.
▪ Problems due to metastability.
• Increasing 𝑇𝑐2𝑞 delay.
• Increasing short circuit current.
• Propagation of different values in the design.
▪ Solving metastability using synchronizers.
o Data incoherency.
▪ Understanding data incoherency.
▪ Data incoherency solutions.
• Gray encoding.
• Enable-based synchronizer.
• Mux-based synchronizer.
• Handshake synchronizer.
o Data loss.
▪ One bit data loss.
• Slow to fast domain.
• Fast to slow domain.
• Understanding Pulse to pulse synchronizers.
▪ Data bus loss.
• Fast to slow crossing.
• Understanding asynchronous FIFO.
• FIFO depth calculations.
• Mean time between failures (MTBF).

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Xilinx Labs (30 Minutes):
• Use a FIFO IP to make a synchronous FIFO, and verify it’s working correctly through
simulation.
o Understanding FIFOs.
o Using the FIFO Generator IP for making a synchronous FIFO.
o Understanding a little bit about AXI.
o Running simulation to verify the design.

Altera Labs (15 Minutes):

• Use a FIFO IP to make a synchronous FIFO, and verify it’s working correctly through
FPGA programming.
o Using the FIFO IP for making a synchronous FIFO.
o Making a top wrapper that has a debouncer with the FIFO to debounce the
signal input from a push button pressed by hand to act as a clock.
o Programming the FPGA to verify the design.

Assignments:
• Write the Verilog code of an Asynchronous FIFO, and verify it’s working correctly through
simulation.
• Write the Verilog code for these CDC circuits and verify they are working correctly
through simulation:
o Double FF synchronizer.
o Enable-based synchronizer.
o Fast to slow pulse to pulse synchronizer.
o Slow to fast pulse to pulse synchronizer.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 4: Hands-on FPGA (6.7 Hours)
Xilinx Labs (2 Hours):
• 1 Hz up/down counter, with its output connected to LEDs on the FPGA.
o Configuring the PLL using the Clocking Wizard IP.
o Understanding the general clock divider RTL code.
o Understanding the counter RTL code.
o Analyzing elaboration / synthesis view.
o Writing XDC physical constraints.
• 1Hz / 7MHz up/down counter, with its output connected to LEDs on the FPGA.
o Understanding clock tree inside the FPGA.
o Understanding clock muxing using BUFGCTRL IP.
o Editing the previous lab by adding a clock mux IP to choose the counter clock 1Hz
or 7MHz.
o Analyzing synthesis view.
o Programming the FPGA.
• Arithmetic operations using DSP blocks.
o Understanding DSP blocks.
o Using the Adder/Subtracter and Multiplier IPs to build the system.
o Analyzing elaboration / synthesis view.
o Writing XDC constraints.
o Programming the FPGA.
• Pulse width modulation.
o Designing hardware to control the average voltage to a led, motor, etc.
o Writing XDC constraints.
o Programming the FPGA.

Altera Labs (2.7 Hours):

• Seven-segment display decoder.
o Understanding the seven segment displays concept.
o Understanding the seven segment displays common anode/cathode RTL.
o Making pin assignment using the pin planner tool.
o Programming the FPGA.
• 3-bit adder with a seven-segment display decoder.
• 4-bit multiplier with a seven-segment display decoder.
o Understanding binary to BCD conversion.
o Building a system to display the multiplication result in BCD format on 3 seven-
segment displays.
o Programming the FPGA.
• Linear feedback shift register (LFSR).
o Understanding the working idea of LFSR.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
 o Understanding how to get the max period for an n-bit LFSR.
o Understanding the characteristic polynomial of the LFSR.
o Connecting a push button to the clock of the LFSR to control the results shown
on the LEDs by hand.
• Linear feedback shift register (LFSR) with a debouncer.
o Understanding bouncing in mechanical push buttons.
o Understanding debouncer RTL code.
o Verifying the correct behavior of the LFSR after adding the debouncer and
programming the FPGA.
• Counter IP with a PLL, clock divider, and a general clock mux RTL.
o Understanding glitchless mux circuit and waveform.
o Configuring the PLL IP.
o Configuring the LPM_COUNTER IP.
o Building the system using the counter IP, PLL IP, clock divider RTL, and a clock
mux RTL to choose the frequency of the counter (1Hz or 1MHz).
o Making pin assignment using the pin planner tool.
o Programming the FPGA.
• Building a digital time in the format HH:MM:SS.
o Understanding the digital timer RTL.
o Converting the timer values to BCD.
o Displaying the timer values on seven-segment displays.
o Making pin assignment using the pin planner tool.
o Programming the FPGA.

Extra (2 Hours):
• Quartus PLL IP - FPGA Programming on Cyclone V FPGA & Simulation on QuestaSim
https://youtu.be/EwqKOu_KoVQ?si=7fsghJjuA4tZ867L
• Automate Compilation & Simulation on QuestaSim
https://youtu.be/Y0koRf6_ugM?si=95Vw9c7dsIlE9v8L
• Command-Line Scripting
https://youtu.be/FTCELYVLNDQ?si=Mar4CDywxTIZnbHB
• Clock Dividers
https://youtu.be/So7Y57KCDcA?si=rg4msCrCht-3DoFD

Assignments:
• Develop the RTL of an elevator controller, and verify it is working correctly through
simulation and FPGA programming.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 5: Static Timing Analysis (7 Hours)
Content (1.5 Hours):
• STA motivation
• Understanding static vs dynamic timing analysis.
o RTL functional simulation.
o Gate-level simulation.
o Static timing analysis.
• Timing paths.
o Data path / clock path / asynchronous path.
o Multicycle path / false path.
o Cell / net delays.
• Understanding important STA terms:
o Setup time / hold time / 𝑇𝑐2𝑞 .
o Arrival time / required time.
o Recovery time / removal time.
o Slack / skew.
• Understanding setup and hold equations through detailed examples.
• Understanding 7 techniques to solve setup violations in the FPGA.
• Understanding 2 techniques to solve hold violations in the FPGA.
• Understanding setup time and hold time in the flipflop internal architecture.
• Understanding SDC netlist terminology and constraints

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Xilinx Labs (3 Hours):
• Combinational full adder STA analysis.
o Performing STA with detailed analysis of the timing reports 3 times:
▪ Once without using any constraints.
▪ Once using timing constraints.
▪ Once using timing and physical constraints.
o Understanding synthesis / implementation strategies (optimization goals).
o Understanding the reason for setting input/output delays.
▪ Simple input/output delay constraints.
▪ More advanced input/output delay constraints using external board
timing parameters and board clock skew.
o Understanding virtual clock.
o Understanding constraints sets.
o Controlling timing report generation.
• Sequential full adder STA analysis.
o Performing STA with detailed analysis of the timing reports 3 times:
▪ Once using TCL XDC constraints
▪ Once using the constraints wizard GUI
▪ Once using the timing constraints window GUI
o Annotating the schematic with the delays values we got from the report
o Understanding clock / input / output / false path constraints.
o Solving timing violations

Xilinx Assignments:
Perform STA for a VERY LARGE combinational circuit, and solve the timing violations.

Altera Labs (2 Hours):

• Sequential circuit static timing analysis
o Understanding the Timing Analyzer tool features
o Applying various SDC timing constraints using the GUI and understanding their
equivalent TCL commands
o Analyzing various timing reports
o Detailed explanation of setup and hold reports using waveforms
o Annotating the technology map schematics with the timing report delays
• Performing static timing analysis for multi-clock sequential circuit
o Understanding SDC constraints for:
▪ PLL
▪ Clock divider
▪ Clock domain crossing designs
o Detailed explanation of setup and hold reports using waveforms

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 6: Hardware Software Codesign (4.7 Hours)
Content (1.1 Hours):
• HW vs SW.
• HW/SW codesign.
• HW/SW partitioning.
• HW/SW codesign gained benefits.
• HW/SW codesign space.
• Explaining the internal structure of the ZYNQ hard core processor.
• Explaining AXI.
• Explaining different AXI ports inside the ZYNQ processor.
o HP / MGP / SGP / ACP
• Microblaze vs ZYNQ vs PCB comparison.
• Explaining the MicroBlaze soft core processor.
o Explaining the 3 MicroBlaze different configurations.
▪ MicroBlaze microcontroller.
▪ MicroBlaze real-time processor.
▪ MicroBlaze application processor.
o Explaining types of OS:
▪ Bare metal code.
▪ General purpose OS.
▪ Real-time OS (RTOS).
o Explaining the difference between FPGAs and adaptive SoCs.
o Explaining the MicroBlaze internal architecture.
o MicroBlaze vs MicroBlaze MCS.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Xilinx Labs (2.3 Hours):
• NAND gate embedded system.
o Designing the hardware part, which is the AND gate.
o Building the embedded system that consists of.
▪ The ZYNQ processor.
▪ The AND gate RTL.
▪ The processing system reset IP.
▪ The Interconnect IP.
▪ Two AXI GPIO IPs.
o Validating the design.
o Writing XDC physical constraints.
o Analyzing the synthesis / implementation schematic views.
o Writing the Inverter as a C code using the SDK tool.
o Understanding the required libraries and macros.
o Verifying the design is working correctly through FPGA programming.
• Prime number checker using the MicroBlaze softcore processor.
o Building the HW part.
▪ PLL.
▪ Counter.
▪ Clock Divider.
o Building the system by adding.
▪ The HW Part.
▪ The MicroBlaze processor.
▪ The processing system reset IP.
▪ The MicroBlaze debug module.
▪ The clocking wizard.
▪ The MicroBlaze local memory IP.
▪ The Interconnect IP.
▪ Two AXI GPIO IPs.
▪ The AXI UART lite IP.
o Writing XDC physical constraints for the BASYS 3 development board.
o Writing the prime number checker as a C code using the SDK tool.
o Understanding the required libraries and macros.
o Developing a testbench for the system.
o Verifying the design is working correctly through simulation in Vivado.
o HW/SW debugging tips.
• Store your design in QSPI Flash on ZYNQ so that the FPGA is programmed automatically
after the power is turned off then on.
o Designing the Hardware part.
o Integrating the HW with the Zynq processor and programming the flash memory.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Altera Labs (1.3 Hours):
• NAND gate embedded system.
o Designing the hardware part, which is the AND gate.
o Building the Qsys system using the Platform Designer tool.
▪ The Nios II soft core processor.
▪ The on-chip memory.
▪ Two PIO IPs.
▪ The JTAG UART IP.
o Solving Qsys errors.
o Generating HDL code for the Qsys system.
o Instantiating the Qsys system with the AND gate in a top wrapper.
o Making pin assignments using the pin planner tool.
o Analyzing the RTL schematic.
o Developing the inverter C code using the Eclipse tool.
o Understanding the required libraries and macros.
o Verifying the design is working correctly through FPGA programming.
• Prime number checker using the Nios II softcore processor.
o Building the HW part.
▪ PLL.
▪ LPM_Counter IP.
▪ Clock Divider.
▪ Seven segment display decoder.
o Building the Qsys system by adding.
▪ The Nios II processor.
▪ The on-chip memory.
▪ Two PIO IPs.
▪ The JTAG UART IP.
o Solving Qsys errors.
o Generating HDL code for the Qsys system.
o Instantiating the Qsys system with the HW part in a top wrapper.
o Making pin assignments using the pin planner tool.
o Developing the prime number checker C code using the Eclipse tool.
o Understanding the required libraries and macros.
o Verifying the design is working correctly through FPGA programming.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Session 7: FPGA Flow Using ISE Design Suite (2.3 Hours)
Session Link: https://youtu.be/OlnCrKdLwW8?si=LJllv9OvcjSh3Qmu

Content (3 Labs):
• Navigating the Spartan 6 FPGA manual pdf file
• Understanding physical UCF constraints
• Design entry using schematic capture
• Viewing RTL/Technology schematics
• Running simulation using ISim simulator
• Changing design optimization goals and strategies.
• Analyzing reports
o Summary report
o Synthesis report
o Map report
o Place and route report
• Converting the RTL code into a symbol to be used in schematic capture
• Using IPs to build your system

Eng. Yousef Sherif FPGA & SoC System Development Course 2025
Final Project
• Develop and implement the RSA encryption algorithm using the C programming
language on a Zynq processor, and verify it is working correctly through simulation and
FPGA programming.

Eng. Yousef Sherif FPGA & SoC System Development Course 2025