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Decoder

The document describes the implementation of a 2-to-4 decoder and a 3-to-8 decoder using VHDL. The 2-to-4 decoder outputs a 4-bit signal based on a 2-bit input and an enable signal, while the 3-to-8 decoder utilizes two instances of the 2-to-4 decoder to expand the output to 8 bits based on a 3-bit input. The architecture details and component mappings are provided for both decoders.

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14 views5 pages

Decoder

The document describes the implementation of a 2-to-4 decoder and a 3-to-8 decoder using VHDL. The 2-to-4 decoder outputs a 4-bit signal based on a 2-bit input and an enable signal, while the 3-to-8 decoder utilizes two instances of the 2-to-4 decoder to expand the output to 8 bits based on a 3-bit input. The architecture details and component mappings are provided for both decoders.

Uploaded by

suneel3812
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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2 to 4 decoder

entity dec2to4 is

Port ( enable : in STD_LOGIC;

sw : in STD_LOGIC_VECTOR (1 downto 0);

led : out STD_LOGIC_VECTOR (3 downto 0));

end dec2to4;

architecture Behavioral of dec2to4 is

begin

led <= "0000" when enable='0' else

"0001" when sw="00" else

"0010" when sw="01" else

"0100" when sw="10" else

"1000";

end Behavioral;

3 to 8 dcoder using 2 to 4

ibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity DEC_38 is

Port ( w : in STD_LOGIC_VECTOR (2 downto 0);

EN : in STD_LOGIC;

Y : out STD_LOGIC_VECTOR (7 downto 0));

end DEC_38;

architecture Behavioral of DEC_38 is

component dec2to4 is

Port ( enable : in STD_LOGIC;

sw : in STD_LOGIC_VECTOR (1 downto 0);

led : out STD_LOGIC_VECTOR(3 downto 0));

end component;

signal m0: STD_LOGIC;

signal m1: STD_LOGIC;

begin

U1: dec2to4 Port map(m1,w(1 downto 0),Y(7 downto 4));

U2: dec2to4 Port map(m0,w(1 downto 0),Y(3 downto 0));


m0 <= NOT w(2) AND EN;

m1 <= w(2) AND EN;

end behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;
--use UNISIM.VComponents.all;

entity dec2 is

Port ( i : in STD_LOGIC_VECTOR (1 downto 0);

en : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (7 downto 0));

end dec2;

architecture Behavioral of dec2 is

component decoder1

Port ( a : in STD_LOGIC_VECTOR (1 downto 0);

e: in STD_LOGIC;

b : out STD_LOGIC_VECTOR (3 downto 0));

end component;

signal ebar: std_logic;

begin
U1: decoder1 Port map(i(1 downto 0),EN,y(7 downto 4));

U2: decoder1 Port map(i(1 downto 0), ebar,y(3 downto 0));

ebar <= not en;

end Behavioral;

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