Microprocessor and Microcontroller

8086 MICROPROCESSOR

2.1 Introduction
The 8086 is a 16-bit microprocessor intended to be used as the CPU in a
microcomputer. The term “16-bit” means that its arithmetic logic unit, internal
registers, and most of its instructions are designed to work 16-bit binary words.
It has 16-bit data bus and 20-bit address bus.
Words will be stored in two consecutive memory locations. If the first byte
of a word is at an even address, the 8086 can read the entire word in one
operation. If the first byte of the word is at an odd address, the 8086 will read
the first byte in one operation, and the second byte in another operation.

Features
● 8086 is a 40 pin IC.
● It is a 16-bit processor.
● Its operating voltage is 5 volts.
● Its operating frequency is 5 MHz
● The total memory addressing capacity is 1MB (external).
● It has 16-bit data bus and 20-bit address bus.
● It has fourteen 16-bit registers.
● It has around 20000 transistors in its circuitry and it is made in
HMOS technology.
● Pipelining improves the performance of the processor so that
operation is faster.8086 uses two stage of pipelining.
● First is Fetch Stage and the second is Execute Stage.
● Fetch stage that prefetch upto 6 bytes of instructions stores them in
the queue.
● Execute stage that executes these instructions.
● Operates in two modes: 8086 operates in two modes:

Minimum Mode: A system with only one microprocessor.

Maximum Mode: A system with multiprocessor.
 ● 8086 uses memory banks:The 8086 uses a memory banking system. It
means entire data is not stored sequentially in a single memory of 1 MB
but memory is divided into two banks of 512KB.
● Interrupts:8086 has 256 vectored interrupts.
● Multiplication and Division:8086 has a powerful instruction set. So
that it supports Multiply and Divide operation.

2.2 Pin Diagram

The 8086 signals can be categorized in three groups. The first are the
signals having common functions in minimum as well as maximum mode, the
second are the signals which have special functions in minimum mode and
third are the signals having special functions for maximum mode
The following signal description are common for both the minimum and
maximum modes.

AD15-AD0
These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the
data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock
states of a machine cycle. TW is a wait state. These lines are active high and
float to a tristate during interrupt acknowledge and local bus hold acknowledge
cycles.
A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed
address and status lines. During T1, these are the most significant address lines
or memory operations. During I/O operations, these lines are low. During
memory or I/O operations, status information is available on those lines for T2,
T3, TW and T4.The status of the interrupt enable flag bit(displayed on S5) is
updated at the beginning of each clock cycle. The S4 and S3 combined, indicate
which segment register is presently being used for memory accesses as shown
in the following table.These lines float to tri-state off during the local bus hold
acknowledge. The status line S6 is always low(logical). The address bits are
separated from the status bits using latches controlled by the ALE signal.
Table 2.1 Segment Register Indication
S S Indication
4 3
0 0 Alternate
data
0 1 Stack
1 0 Code or none
 Microprocessor and Microcontroller

1 1 Data

Fig. 2.1Pin Diagram

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to

indicate the transfer of data over the higher order (D15-D8) data bus as shown
in the following table. It goes low for the data transfers over D15-D8 and is used
to derive chip selects of odd address memory bank or peripherals. BHE is low
during T1 for read, write and interrupt acknowledge cycles, when- ever a byte
is to be transferred on the higher byte of the data bus. The status information is
available during T2, T3 and T4. The signal is active low and is high-impedance
state during 'hold'. It is low during T1 for the first pulse of the interrupt
acknowledge cycle.
 Microprocessor and Microcontroller

Table 2.2 Bus High Enable Indication

BH A Indication
E 0
0 0 Whole word
0 1 Upper byte from or to odd
address
1 0 Upper byte from or to even
address
1 1 None

RD-Read: Read signal, when low, indicates the peripherals that the
processor is performing a memory or I/O read operation. RD is active low and
shows the state for T2, T3, TW of any read cycle. The signal remains in high-
impedance during the 'hold acknowledge'.

Ready: This is the acknowledgement from the slow devices or memory that
they have completed the data transfer. The signal made available by the devices
is synchronized by the 8284A clock generator to provide ready input to the
8086. The signal is active high.

INTR-lnterrupt Request: This is a level triggered input. This is sampled

during the last clock cycle of each instruction to determine the availability of
the request. If any interrupt request is pending, the processor enters the
interrupt acknowledge cycle. This can be internally masked by resetting the
interrupt enable flag. This signal is active high and internally synchronized.

TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes
low, execution will continue, else, the processor remains in an idle state. The
input is synchronized internally during each clock cycle on leading edge of
clock.

NMI-Non-maskable Interrupt: This is an edge-triggered input which

causes a Type2 interrupt. The NMI is not maskable internally by software. A
transition from low to high initiates the interrupt response at the end of the
current instruction. This input is internally synchronized.

Reset: This input causes the processor to terminate the current activity and
start execution from FFFF0H. The signal is active high and must be active for at
least four clock cycles. It restarts execution when the RESET returns low. RESET
is also internally synchronized.

CLK-Clock Input: The clock input provides the basic timing for processor
operation and bus control activity. It’s an asymmetric square wave with 33%
duty cycle. The range of frequency for different 8086 versions is from 5MHz to
10MHz.

VCC : +5V power supply for the operation of the internal circuit. GND
ground for the internal circuit.
MN/MX: The logic level at this pin decides whether the processor is to
operate in either minimum (single processor) or maximum (multiprocessor)
mode.
The following pin functions are for the minimum mode operation of 8086.

M/IO -Memory/IO: This is a status line logically equivalent to S2 in

maximum mode. When it is low, it indicates the CPU is having an I/O operation,
and when it is high, it indicates that the CPU is having a memory operation. This
line becomes active in the previous T4 and remains active till final T4 of the
current cycle. It is in high-impedance state during local bus "hold acknowledge".

INTA -Interrupt Acknowledge: This signal is used as a read strobe for

interrupt acknowledge cycles. In other words, when it goes low, it means that
the processor has accepted the interrupt. It is active low during T2, T3 and TW
of each interrupt acknowledge cycle.

ALE-Address latch Enable: This output signal indicates the availability of

the valid address on the address/data lines, and is connected to latch enable
input of latches. This signal is active high and is never in high-impedance state.

DT /R -Data Transmit/Receive: This output is used to decide the direction

of data flow through the transceivers (bidirectional buffers). When the
processor sends out data, this signal is high and when the processor is receiving
data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its
timing is the same as M/I/O.

DEN-Data Enable This signal indicates the availability of valid data over
the address/data lines. It is used to enable the transceivers (bidirectional
 Microprocessor and Microcontroller

buffers) to separate the data from the multiplexed address/data signal. It is

active from the middle of T2 until the middle of T4 DEN is in high-impedance
state during 'hold acknowledge' cycle.

HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it

indicates to the processor that another master is requesting the bus access. The
processor, after receiving the HOLD request, issues the hold acknowledge signal
on HLDA pin, in the middle of the next clock cycle after completing the current
bus (instruction) cycle. At the same time, the processor floats the local bus and
control lines. When the processor detects the HOLD line low, it lowers the
HLDA signal. HOLD is an asynchronous input, and it should be externally
synchronized. If the DMA request is made while the CPU is performing a
memory or I/O cycle, it will release the local bus during T 4 provided:
1. The request occurs on or before T 2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or
operating on an odd address).
3. The current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin functions are applicable for maximum mode operation of
8086.

S2, S1, S0 -Status Lines: These are the status lines which reflect the type of
operation, being carried out by the processor. These become active during T4 of
the previous cycle and remain active during T1 and T2 of the current bus cycle.
The status lines return to passive state during T3 of the current bus cycle so
that they may again become active for the next bus cycle during T4. Any change
in these lines during T3 indicates the starting of a new cycle, and return to
passive state indicates end of the bus cycle. These status lines are encoded in
the following table.
Table 2.3 Status Lines Indication
S S S Indication
2 1 0
0 0 0 Interrupt
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
 1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

Lock
This output pin indicates that other system bus masters will be prevented
from gaining the system bus, while the LOCK signal is low. The LOCK signal is
activated by the 'LOCK' prefix instruction and remains active until the
completion of the next instruction. This floats to tri-state off during "hold
acknowledge". When the CPU is executing a critical instruction, which requires
the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus. The 8086, while
executing the prefixed instruction, asserts the bus lock signal output, which
may be connected to an external bus controller.

QS1, QS0-Queue Status

These lines give information about the status of the code prefetch queue.
These are active during the CLK cycle after which the queue operation is
performed. These are encoded as shown in the following table.

Table 2.4 Queue Status Indication

Qs Qs Indication
1 0
0 0 No operation
0 1 First byte of opcode from the
queue
1 0 Empty queue
1 1 Subsequent byte from the queue

RQ/GT0, RQ/GT1-ReQuest/Grant: These pins are used by other local bus

masters, in maximum mode, to force the processor to release the local bus at
the end of the processor's current bus cycle. Each of the pins is bidirectional
with RQ/GT0 having higher priority than RQ/ GT1, RQ/GT pins have internal
pull-up resistors and may be left unconnected. The request! grant sequence is
as follows:
1. A pulse one clock wide from another bus master requests the bus
access to 8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide
 Microprocessor and Microcontroller

from 8086 to the requesting master, indicates that the 8086 has
allowed the local bus to float and that it will enter the "hold
acknowledge" state at next clock cycle. The CPU's bus interface unit
is likely to be disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to 8086 that
the 'hold' request is about to end and the 8086 may regain control
of the local bus at the next clock cycle. Thus, each master to master
exchange of the local bus is a sequence of 3 pulses. There must be at
least one dead clock cycle after each bus exchange. The request and
grant pulses are active low. For the bus requests those are received
while 8086 is performing memory or I/O cycle, the granting of the
bus is governed by the rules of HOLD, and HLDA in minimum mode.

2.3 Internal Block Diagram

The 8086 CPU is divided into two independent functional parts, the bus
interface unit or BIU, and the execution unit or EU.

The Bus Interface Unit

The BIU handles all data and addresses on the buses for the execution unit
such as it sends out addresses, fetches instructions from memory, reads data
from ports and memory as well as writes data to ports and memory. In BIU
there are so many functional groups or parts these are as follows.

Instruction Queue
To increase the execution speed, BIU fetches as many as six instruction
bytes ahead to time from memory. The prefetched instruction bytes are held for
the EU in a first in first out group of registers called an instruction queue. When
the EU is ready for its next instruction, it simply reads the instruction from this
instruction queue. This is much faster than sending out an address to the
system memory and to send back the next instruction byte. Fetching the next
instruction while the current instruction executes is called pipelining.
Fig 2.2 Block Diagram
 Microprocessor and Microcontroller

Segment Registers
The BIU contains four 16-bit segment registers. They are: the extra segment
(ES) register, the code segment (CS) registers, the data segment (DS) registers,
and the stack segment (SS) registers. These segment registers are used to hold
the upper 16 bits of the starting address for each of the segments. The part of a
segment starting address stored in a segment register is often called the
segment base.
1. Code Segment (CS): The CS register is used for addressing a memory
location in the Code Segment of the memory, where the executable
program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data
are accessed in the
Data Segment by an offset address or the content of other register that
holds the offset address.
3. Stack Segment (SS): SS defined a section of memory to store addresses
and data while a subprogram executes.
4. Extra Segment (ES): ES is additional data segment that is used by some
of the string to hold the extra destination data.

Fig 2.3 Segment Register

Instruction Pointer (IP)
In the BIU, the next register, below the segment register is instruction
pointer. The instruction pointer (IP) holds the 16-bit address of the next code
byte within this code segment.
 The Execution Unit
The execution unit (EU) tells the BIU where to fetch instructions or data
from, decodes instructions, and executes instructions. The functional parts of
the execution unit are control circuitry or system, instruction decoder, and
Arithmetic logic unit (ALU).Control circuitry to perform various internal
operations. A decoder in the EU translates instructions fetched from memory to
generate different internal or external control signals that required performing
the operation. The EU has a 16-bit ALU, which can perform arithmetic
operations such as add, subtract etc. and logical operations such as AND, OR,
XOR, increment, decrement etc.

Flag Register
A 16-bit flag register is a flip-flop which indicates some condition produced
by the execution of an instruction or controls certain operations of the EU. They
are modified automatically by CPU after mathematical operations. It has 9 flags
and they are divided into two categories:
1. Conditional Flags
2. Control Flags

Conditional Flags
Conditional flags represent result of last arithmetic or logical instructions.
● Carry Flag (CF): This flag will be set to one if the arithmetic
operation produces the carry in MSB position. It is also used in
multiple-precision arithmetic.
● Auxiliary Flag (AF): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e.
D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag.
This is not a general-purpose flag; it is used internally by the
processor to perform Binary to BCD conversion.
● Parity Flag (PF): This flag is used to indicate the parity of result. If
lower order 8-bits of the result contains even number of 1’s, the
Parity Flag is set to one and for odd number of 1’s, the Parity Flag is
reset i.e. zero.
● Zero Flag (ZF): It is set to one; if the result of arithmetic or logical
operation is zero else it is reset.
● Sign Flag (SF): In sign magnitude format the sign of number is
indicated by MSB bit. If the result of operation is negative, sign flag
is set to one.
 Microprocessor and Microcontroller

● Overflow Flag (OF): It occurs when signed numbers are added or

subtracted. An OF indicates that the result has exceeded the
capacity of machine.

Control Flags
Control flags are intentionally set or reset to control certain operations of
the processor with specific instructions put in the program from the user.
Control flags are as follows:
1. Trap Flag (TF): It is used for single step control. It allows user to
execute one instruction of a program at a time for debugging. When
trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used
to allow/prohibit the interruption of a program. If it is set, the
maskable interrupt is enabled and if it is reset, the interrupt is
disabled.
3. Direction Flag (DF): It is used in string operation. If it is set, string
bytes are accessed from higher memory address to lower memory
address. When it is reset, the string bytes are accessed from lower
memory address to higher memory address.

Fig 2.4 Flag Register

2.4 General Purpose Registers

The EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL,
DH, and DL. These registers can be used individually for temporary storage of
8-bit data. The AL register is also called the accumulator. Certain pairs of these
general-purpose registers can be used together to store 16-bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL and DH and DL. These
register pairs are referred to the AX, BX, CX, and DX resp.
 1. AX Register: For 16-bit operations, AX is called the accumulator
register that stores operands for arithmetic operations.
2. BX Register: This register is mainly used as a base register. It holds
the starting base location of a memory region within a data
segment.
3. CX Register: It is defined as a counter. It is primarily used in loop
instruction to store loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O
instruction.

Stack Pointer Register

The stack pointer (SP) register contains the 16-bit offset from the start of
the segment to the memory location where a word was most recently stored on
the stack. The memory location where a word was most recently stored is
called the top of stack.

Other Pointer and Index Registers

The EU also contains a 16-bit source index (SI) register, base pointer (BP)
registers, and Destination Index (DI) registers. These three registers can be
mainly used for temporary storage of 16-bit data just like a general-purpose
register.

2.5 Addressing Modes of 8086

When 8086 executes an instruction, it performs the specified function on
data. These data are called its operands and may be part of the instruction,
reside in one of the internal registers of the microprocessor, stored at an
address in memory or held at an I/O port, to access these different types of
operands, the 8086 is provided with various addressing modes (Data
Addressing Modes).
The 8086 has 12 addressing modes. The various 8086 addressing modes
can be classified into five groups.
A. Addressing modes for accessing immediate and register data (register
and immediate modes).
B. Addressing modes for accessing data in memory (memory modes)
C. Addressing modes for accessing I/O ports (I/O modes)
D. Relative addressing mode
E. Implied addressing mode
 Microprocessor and Microcontroller

Immediate addressing mode

In this mode, 8- or 16-bit data can be specified as part of the instruction.

Example 1
MOV CL, 03 H
Moves the 8-bit data 03 H into CL

Example 2
MOV DX, 0525 H
Moves the 16-bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and
the destination operand is in register mode.
A constant such as “VALUE” can be defined by the assembler EQUATE
directive such as VALUE EQU 35H

Example
MOV BH, VALUE
Used to load 35 H into BH

Register addressing mode

The operand to be accessed is specified as residing in an internal register of
8086. The table below shows internal registers, one can be used as a source or
destination operand, however only the data registers can be accessed as either
a byte or word.

Table 2.5 Register with Operand Sizes

Example 1
MOV DX (Destination Register), CX (Source Register)
Which moves 16-bit content of CS into DX.

Example 2
MOV CL, DL
Moves 8-bit contents of DL into CL
MOV BX, CH is an illegal instruction.
* The register sizes must be the same.

Direct addressing mode

The instruction Opcode is followed by an affective address, this effective
address is directly used as the 16-bit offset of the storage location of the
operand from the location specified by the current value in the selected
segment register.

The default segment is always DS.

The 20-bit physical address of the operand in memory is normally obtained
as PA = DS: EA
But by using a segment override prefix (SOP) in the instruction, any of the four
segment registers can be referenced,

The Execution Unit (EU) has direct access to all registers and data for
register and immediate operands. However, the EU cannot directly access the
memory operands. It must use the BIU, in order to access memory operands. In
the direct addressing mode, the 16-bit effective address (EA) is taken directly
from the displacement field of the instruction.
Example 1
MOV CX, START
If the 16-bit value assigned to the offset START by the programmer using an
assembler pseudo instruction such as DW is 0040 and [DS] = 3050.
Then BIU generates the 20-bit physical address 30540 H.
The content of 30540 is moved to CL
The content of 30541 is moved to CH
 Microprocessor and Microcontroller

Example 2
MOV CH, START
If [DS] = 3050 and START = 0040
8-bit content of memory location 30540 is moved to CH.

Example 3
MOV START, BX
With [DS] = 3050, the value of START is 0040.
Physical address: 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541
respectively.

Register indirect addressing mode

The EA is specified in either pointer (BX) register or an index (SI or DI)
register. The 20-bit physical address is computed using DS and EA.

Example
MOV [DI], BX
register indirect
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX (2456) is moved to memory locations 50060 H and
50061 H.

Based addressing mode

when memory is accessed PA is computed from BX and DS when the stack

is accessed PA is computed from BP and SS.
Example
MOV AL, START [BX]
or
MOV AL, [START + BX]
 based mode
EA: [START] + [BX]
PA: [DS] + [EA]
The 8-bit content of this memory location is moved to AL.

Indexed addressing mode

Example
MOV BH, START [SI]
PA: [SART] + [SI] + [DS]
The content of this memory is moved into BH.

Based Indexed addressing mode

Example
MOV ALPHA [SI] [BX], CL
If [BX] = 0200, ALPHA – 08, [SI] = 1000 H and [DS] = 3000
Physical address (PA) = 31208
8-bit content of CL is moved to 31208 memory address.

String addressing mode

The string instructions automatically assume SI to point to the first byte or
word of the source operand and DI to point to the first byte or word of the
destination operand. The contents of SI and DI are automatically incremented
(by clearing DF to 0 by CLD instruction) to point to the next byte or word.

Example
MOV S BYTE
If [DF] = 0, [DS] = 2000 H, [SI] = 0500,
[ES] = 4000, [DI] = 0300
Source address: 20500, assume it contains 38
 Microprocessor and Microcontroller

PA: [DS] + [SI]

Destination address: [ES] + [DI] = 40300, assume it contains 45
After executing MOV S BYTE,

I/O mode
Direct Mode
Port number is an 8-bit immediate operand.
Example: OUT 05H, AL
Outputs [AL] to 8-bit port 05 H

Indirect Mode
The port number is taken from DX.

Example 1
INAL, DX
If [DX] = 5040
8-bit content by port 5040 is moved into AL.

Example 2
IN AX, DX
Inputs 8-bit content of ports 5040 and 5041 into AL and AH respectively.

Relative addressing mode

Example: JNC START
If CY=O, then PC is loaded with current PC contents plus 8-bit signed value
of START, otherwise the next instruction is executed.

Implied addressing mode

Instruction using this mode have no operands.
Example: CLC which clears carry flag to zero.
2.2 Instruction Set
Data Transfer Instructions

Logical Instructions
 Microprocessor and Microcontroller

Shift and Rotate Instructions

Arithmetic Instructions
Call and Return Instructions
 Microprocessor and Microcontroller

Jump and Loop Instructions

 Dr. N. Karuppiah & Dr. S. Ravivarman

String Instructions

Processor and Flag Control Instructions

3.2 Min/Max Mode of Operation

The microprocessors 8086 and 8088 can be configured to work in two
modes: The Minimum mode and the Maximum mode.
The Minimum mode is used for single processor system, where 8086/8088
directly generates all the necessary control signals.
 Microprocessor and Microcontroller

The Maximum mode is designed for multiprocessor systems, where an

additional “Bus-controller” IC is required to generate the control signals. The
processors control the Bus controller using status-codes.

Fig 2.5 Min/Max mode signals