VLSI Design

CHAPTER 1

INDUSTRIAL INTERNSHIP

WIINNR is an unique future skill training program where industry, academia and
government comes together to offer training by experts from industry and academia. In the
rapidly evolving job market, having the right set of skills is more crucial than ever. WIINNR
is designed to equip you with the industry-relevant knowledge and hands-on experience
necessary to excel in your chosen career. This program is a rare opportunity where leading
industry giants and esteemed academic institutions have come together to create a pathway
that transforms students into highly employable graduates.

Fig. 1.1: VTU Internship Program

Duration: The WIINNR internship training spans around 400 hours in the Final Year,
allowing you to effectively manage your academic coursework alongside skill development.

Mode of Delivery: The training will be delivered through a blend of online and in-person
sessions, utilizing state-of-the-art audio-visual facilities at your respective colleges.

Assessment and Certification: Students progress will be monitored through continuous

assessments, assignments, project work, and a final examination, culminating in globally
recognized certifications.

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CHAPTER 2

ORGANISATION

I. Rooman Technologies

As a leader in IT certifications and future skills, Rooman Technologies will provide 165 hours of core subject
training. This intensive training is led by industry experts who bring real-world insights and practical knowledge
to the classroom. The focus is on ensuring that you not only grasp theoretical concepts but also learn how to
apply them effectively in professional settings.

II. IBM

IBM, a global leader in technology and innovation, will offer 90 hours of project-based learning. This hands-on
approach will allow you to work on real projects, giving you the opportunity to apply your skills in a practical
environment. Upon completion, you will receive a certificate of project completion from IBM, a credential that
will significantly enhance your resume.

III. IIT Guwahati

One of India’s premier institutions, IIT Guwahati, will provide 30 hours of advanced training on cutting-edge
topics. In addition to this, IIT Guwahati will offer a one-month research internship at their campus to 2-3
selected candidates from each college. This prestigious opportunity will allow you to engage in high-level
research and development, further honing your skills and expanding your academic and professional horizons.

IV. Wadhwani Foundation

Understanding the importance of soft skills in today’s job market, the Wadhwani Foundation will offer 75 hours
of soft skills training. This course is designed to improve your communication, teamwork, leadership, and
problem-solving abilities, making you a well-rounded candidate who is ready to thrive in any work
environment.

V. NASSCOM and NSDC

In a bid to ensure that your transition from academia to industry is smooth, NASSCOM and NSDC will actively
engage with industries to facilitate internships and placement opportunities. This direct connection with
employers will give you a significant advantage in securing a position in the competitive job market

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CHAPTER 3

INDUSTRIAL TRAINING

Rooman Technologies offers VLSI (Very Large Scale Integration) training, covering digital design,
VHDL/Verilog, and circuit simulation to help students gain practical expertise in chip design. VLSI
projects typically focus on designing and simulating integrated circuits, such as microprocessors or
custom ICs, using tools like FPGA or ASIC. The Wadhwani Foundation focuses on enhancing soft
skills such as communication, leadership, and time management through various training programs.

Objectives of the internship

1. Gain hands-on experience in designing and simulating digital circuits using tools like
VHDL/Verilog.
2. Learn to work with FPGA or ASIC design platforms for practical implementation of VLSI
projects.
3. Understand the process of timing analysis, power optimization, and synthesis in VLSI design.
4. Develop problem-solving skills by working on real-world circuit design challenges.
5. Collaborate with teams to improve communication and teamwork skills in a technical
environment.
6. Enhance communication skills for presenting technical concepts clearly and effectively.
7. Develop leadership qualities to take initiative and manage small teams in projects.
8. Learn time management skills to handle multiple tasks efficiently in a fast-paced
environment.
9. Improve interpersonal skills for better collaboration with peers and mentors.
10. Build critical thinking abilities to approach complex design problems and find creative
solutions.

3.1 Learnings with Wadhwani Foundations

1. Communication Skills

 Greetings and Introductions: Learning proper ways to introduce oneself and others.
 Phone Conversations: Techniques for effective phone communication.

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 Articulation in Reading: Reading English texts with correct pronunciation and clarity.
 Saying No Politely: How to refuse requests without sounding rude.

2. Writing Skills

 Constructing Meaningful Sentences: Building grammatically correct and coherent

sentences.
 Writing Notes and Reports: Creating concise, clear, and effective notes, resumes, and
reports.

3. Personal Development

 First Impressions: Tips to create a positive impression during interviews.

 Non-verbal Communication: Understanding body language and gestures.
 Emotional Intelligence: Managing emotions effectively.
 Positive Attitude and Ethics: Developing an optimistic mindset and ethical decision-
making.

4. Time and Conflict Management

 Task Planning: Prioritizing and managing tasks within deadlines.

 Conflict Resolution: Strategies to resolve conflicts while maintaining relationships.
 Negotiation Skills: Techniques to reach agreements.

5. Teamwork and Innovation

 Team Collaboration: Working effectively with different teams.

 Critical Thinking and Decision Making: Developing problem-solving skills.
 Design Thinking: Applying design thinking principles to solve problems.

6. Workplace Readiness

 Customer Focus: Understanding customer needs and types of customers.

 CRM Systems: Basics of Customer Relationship Management tools.

7. Technical Skills

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 MS Office Tools: Proficiency in Word, Excel, and PowerPoint.

 Email Communication: Writing professional emails.
 Online Communication Tools: Using digital collaboration tools like Zoom or Teams.

8. Diversity and Ethics

 Cultural Diversity: Respecting different cultures and values.

 Ethical Decisions: Making value-based decisions.
 POSH Act: Understanding the Prevention of Sexual Harassment Act.
 Disability Etiquette: Behaving appropriately towards people with disabilities.

3.2 Learnings with IIT Guwahati

Evolution of Computer-Aided Digital Design (CAD) and Digital Circuits:

The evolution of Computer-Aided Digital Design (CAD) and digital circuits has dramatically
transformed the way electronic systems are designed, especially in the realm of VLSI (Very-Large-
Scale Integration) and modern computing. Here’s an overview:

Early Beginnings (Pre-1960s):

 Manual Design: Digital circuits were initially designed manually on paper. Engineers used
logic gates and Boolean algebra to design and simulate circuits.
 Limited Complexity: Due to manual design, only simple digital circuits with a limited
number of components could be realized.

Rise of VLSI and EDA Tools (1980s-1990s):

 VLSI Revolution: With the ability to integrate millions of transistors into a single chip, the
complexity of digital circuit design grew. EDA tools evolved to help handle the increasing
complexity.
 Automated Design Flow: Tools were developed for logic synthesis, timing analysis, and
simulation. This era also saw the introduction of HDLs (Hardware Description Languages)
like Verilog and VHDL for higher-level abstraction in design.

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Modern Digital Design and AI Integration (2000s-Present):

 SoC Design & High-Level Synthesis: With the integration of entire systems on a chip (SoC),
modern digital design tools like Verilog and SystemVerilog enable high-level synthesis and
automation.
 Machine Learning in Design: AI and machine learning are starting to optimize the design
and verification processes, improving power efficiency, performance, and design time.

Digital Circuit Explanation:

Digital Circuits process data using discrete signals (0s and 1s), relying on logic gates and memory
elements. Here’s a brief overview:

1. Basic Components:
o Logic Gates: The primary building blocks of digital circuits. They perform logical
operations (AND, OR, NOT, etc.) on binary inputs. Examples:
 AND Gate: Outputs 1 only when both inputs are 1.
 OR Gate: Outputs 1 if at least one input is 1.
o Flip-Flops: Memory elements that store binary data. They are used in sequential
circuits to remember past input states.

2. Types of Digital Circuits:

o Combinational Circuits: The output depends only on the current input. Examples
include adders, multiplexers, and encoders.
o Sequential Circuits: The output depends on both the current and previous inputs.
Examples include counters, registers, and memory devices.

3. Binary Representation: Digital circuits use binary numbers (0s and 1s) to represent and
process data, making them ideal for computer systems and digital devices.

Verification with System Verilog, Test benches, and Design Examples:

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1. SystemVerilog:

 SystemVerilog is an extension of Verilog that provides capabilities for both hardware

description and verification. It is widely used for writing testbenches to verify digital
designs.
 Testbenches are used to simulate and verify the functionality of a digital design by providing
inputs and observing outputs. They are essential for ensuring the correctness of designs before
implementation.

2. Designing AND Gate in Verilog:

module AND_gate (
input A, B,
output Y
);
assign Y = A & B;
endmodule

 This simple Verilog code describes a 2-input AND gate, where A and B are inputs, and Y is
the output.

3. Designing a 4:1 Multiplexer (MUX) in Verilog:

module mux4to1 (
input [3:0] D, // 4 data inputs
input [1:0] S, // 2-bit selector
output Y // Output
);
assign Y = (S == 2'b00) ? D[0] :
(S == 2'b01) ? D[1] :
(S == 2'b10) ? D[2] : D[3];
Endmodule

History Facts:

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1. Transistor Revolution:

 The invention of the transistor in 1947 replaced vacuum tubes, leading to smaller, faster, and
more reliable electronic devices.
 This revolution allowed for the rapid advancement of digital electronics, including computers,
communication systems, and other consumer electronics.

2. Moore's Law and Microprocessors:

 Moore's Law (proposed by Gordon Moore in 1965) predicted that the number of transistors
on a chip would double approximately every two years, leading to exponential growth in
computing power and the miniaturization of electronics.
 The impact of Moore's Law has been profound, enabling the rapid evolution of
microprocessors and VLSI technology that power modern computing systems.

Overview of Digital Design Using Verilog:

1. Verilog is a Hardware Description Language (HDL) used for modeling digital circuits at
various levels of abstraction, from high-level algorithmic descriptions to low-level gate-level
designs.
2. HDL Importance:
o Abstraction: Verilog allows for high-level abstraction, making it easier to model
complex circuits.
o Synthesis: HDL designs can be synthesized into gate-level implementations.
o Simulation: Verilog provides tools for simulating the behavior of digital systems to
verify correctness before hardware implementation.

Basics of Digital Hardware Modelling:

1. HDLs (Hardware Description Languages): Verilog and VHDL are used to describe the
behavior and structure of digital hardware. They enable simulation, synthesis, and verification
of designs.
2. Levels of Abstraction:
o Behavioral Level: Describes the functionality of a circuit (e.g., if-else statements).

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o Register-Transfer Level (RTL): Describes how data moves between registers in the
system.
o Gate-Level: Describes circuits in terms of logic gates (AND, OR, NOT, etc.).

VLSI Design Methodology:

1. Specification: Define the functionality of the system.

2. Design Entry: Create the digital design using HDLs (Verilog or VHDL).
3. Synthesis: Convert high-level design into gate-level logic.
4. Simulation: Verify the functionality of the design through simulation.
5. Layout Design: Place and route the logic on a chip.
6. Fabrication: Manufacture the chip.
7. Testing: Ensure that the chip functions correctly in real-world conditions.

Modeling in VLSI Design:

 Functional Modeling: At the higher abstraction level, describing the behavior of the system.
 Structural Modeling: Describing the interconnection of components.
 Timing and Power Modeling: Focus on optimizing the timing and power efficiency of the
design.

In summary, SystemVerilog and other HDLs play a crucial role in the digital design process,
allowing for efficient design, simulation, and verification of VLSI circuits. The development of
CAD tools and the ongoing evolution of transistor technology have made possible the powerful,
compact, and high-performance systems we use today.

1. Syntax and Semantics of Verilog:

 Syntax refers to the set of rules that define the structure of valid Verilog statements (how the
code should be written).
 Semantics refers to the meaning of those statements (what the code actually does or how it
behaves when executed).

2. Comments in Verilog:

 Single-line comments start with //, and the comment ends at the end of the line.

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 // This is a single-line comment

 Multi-line comments are enclosed between /* and */.
 /* This is a
 multi-line comment */

3. Strings in Verilog:

 Verilog supports string literals enclosed in double quotes.

 reg [31:0] str = "Hello, World!";

4. Identifiers:

 Identifiers are names given to variables, modules, and other design elements in Verilog.
 They must start with a letter or underscore (_), followed by letters, digits, or underscores.
 wire clk;
 reg [7:0] data;

5. Numbers and Systems:

 Binary: 4'b1010
 Octal: 3'o7
 Decimal: 5'd10
 Hexadecimal: 8'hFF

Verilog supports different number systems for representing constants.

6. Physical Data Types:

 These represent physical values used in simulation, like real values or time.
o Real: Used for floating-point numbers.
o Time: Used to represent simulation time.
 real temperature;
 time clk_time;

7. Net Data Types:

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 Nets represent connections between hardware elements, typically used for wires, buses, or
outputs.
o Wire: Default net type used to connect components.
o Reg: A variable that holds a value (used in procedural blocks).

Example:

wire clk;
reg [7:0] data;

8. Strength Levels:

 Verilog allows specifying strengths for net variables. These are used to simulate physical
driving strengths.
o strong0, strong1, pull0, pull1, weak0, weak1, highz0, highz1

Example:

wire strong1 data;

9. Advanced Net Types:

 Advanced net types include tri, tri0, tri1, wand, wor, etc.
o Tri-state: A net type that can be driven to three states: logic 0, logic 1, and high
impedance (Z).
o tri type: A bidirectional net, often used for buses.

10. Gate Level Modeling:

 Gate-level modeling is the lowest level of abstraction, describing circuits in terms of logic
gates.
 and (output, input1, input2); // AND gate
 or (output, input1, input2); // OR gate
 not (output, input); // NOT gate

11. Pull Gates and Tri-state Gates:

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Pull-up/pull-down gates are used to drive a signal to a defined value when no other signal is
driving it (used to resolve undefined states).

pullup (net); // Pull-up resistor

pulldown (net); // Pull-down resistor

Tri-state gates allow multiple drivers to drive a net, but only one can drive it at a time (used in
buses).

assign data = enable ? value : 1'bz; // Tri-state logic

12. Gate Delays:

 Delays in gate-level modeling can be specified to simulate real-world gate behavior.

 and #(5) (out, a, b); // AND gate with a 5-time unit delay

13. Concept of Wire:

 A wire is a net data type used to connect hardware components.

 wire clk;

14. Continuous Assignment:

 A continuous assignment is used to continuously drive a value to a net or wire.

 assign out = a & b; // Continuous assignment

15. Delayed Continuous Assignments:

 A continuous assignment with a delay.

 assign #5 out = a & b; // Assign after a delay of 5 time units

16. Verilog Data Types:

 Wire: Represents continuous signals (used for connections).

 Reg: Represents a variable that stores data and is used in procedural blocks.

17. Initial and Always Blocks:

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Initial Block: Used for initializing values at the start of the simulation.

initial begin
data = 8'b00000000;
end

Always Block: Defines processes that continuously execute during simulation.

always @(clk or reset) begin

if (reset)
data = 8'b00000000;
else
data = data + 1;

18. Procedural Assignment (Sequential and Parallel):

Sequential assignment (within always or initial blocks) happens step by step.

always @(posedge clk) begin

a = b;
end

Parallel assignment (outside always or initial blocks) happens immediately and simultaneously.

assign a = b & c;

19. Timing Controls:

# Delay Control: Delays execution by a specific number of time units.

#5 a = 1;

@ Event Control: Executes the block whenever a signal changes.

always @(posedge clk) begin

data = data + 1;
end

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20. Level Sensitive Controls:

Used in always or initial blocks to trigger actions based on the level of signals.

always @(posedge clk) begin

data = data + 1;
end

21. Conditional Statements:

If-else:

if (a == 1) begin
data = 1;
end else begin
data = 0;
end

Case Statement:

case (a)
2'b00: data = 1;
2'b01: data = 2;
default: data = 0;
endcase

22. Loop Statements:

For Loop:

for (i = 0; i < 8; i = i + 1) begin

data[i] = 1;
end

While Loop:

while (a == 1) begin

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data = data + 1;
end

Break Statement:

if (a == 1) break; // Exit loop early

23. Generate Block:

Used for creating repetitive structures based on parameters or conditions.

generate
for (i = 0; i < N; i = i + 1) begin
// logic here
end
endgenerate

24. Procedural Continuous:

 A procedural continuous assignment combines the advantages of procedural blocks and

continuous assignments.
 always @(posedge clk) begin
 assign out = a & b;
 end

25. Tasks and Functions:

Task: A procedure that can have time delays and multiple input/output parameters.

task increment;
input [7:0] data;
begin
data = data + 1;
end
endtask

Function: A procedure that returns a value and cannot have time delays.
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function [7:0] add;

input [7:0] a, b;
add = a + b;
endfunction

26. User Defined Primitives (UDP):

Verilog allows the creation of custom logic functions using User Defined Primitives (UDP),
which are essentially user-defined gate-level models.

27. Compiler Directives:

 timescale defines the time unit and precision.

 `timescale 1ns/1ps
 include directive includes files.
 `include "file.v"

28. Switch Level Modeling:

 Describes behavior at the switch level, often used for modeling MOSFETs and other
transistors.
 switch (a) begin
 // logic based on transistor behavior
 end

29. System Tasks and Functions:

 These tasks and functions allow interaction with the simulation environment. For example,
$display prints to the simulation log:
 $display("Value of data: %b", data);

30. VCD Files (Value Change Dump):

 VCD files are used to store simulation waveforms. They record the value changes of signals
over time.
 $dumpfile("wave.vcd");

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 $dumpvars(0, top);

31. Specifying Delays and Timing Regions:

 Delays can be specified for different operations in Verilog to simulate real-world gate delays
and timing.
 #5 a = 1;

System Verilog Introduction and Features

System Verilog is an extension of Verilog, which provides advanced features for hardware design,
verification, and modeling. It combines the capabilities of hardware description languages (HDLs)
with features typically found in high-level programming languages, making it suitable for both design
and verification.

Convenience and Synthesis Features:

 Convenience Features: SystemVerilog adds constructs to Verilog that improve code

readability, maintainability, and ease of use, such as more powerful data types, procedural
blocks, randomization, and object-oriented programming (OOP) capabilities.
 Synthesis Features: It also includes features that enhance hardware synthesis, allowing for
easy transition from simulation to physical implementation. SystemVerilog supports
synthesizable constructs, including parameters, enumerations, and more.

Data Types in System Verilog:

System Verilog provides richer data types compared to Verilog:

 Primitive Data Types:

logic: Represents a 4-state value (0, 1, X, Z), often used in place of reg or wire.

bit: Represents a 2-state value (0 or 1).

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reg: A data type used for storing values, similar to logic but primarily used in procedural
blocks.

int: A 32-bit signed integer.

byte, shortint, longint: 8, 16, and 64-bit signed integers.

real: Represents floating-point numbers.

 Enumerated Data Types:

Enum: Used for defining a set of named values (typically for state machines).

typedef enum logic [1:0] {

IDLE = 2'b00,
RUN = 2'b01,
STOP = 2'b10
} state_t;
state_t current_state;

 Arrays and Queues:

Arrays: SystemVerilog supports packed and unpacked arrays. Packed arrays store data in
a single contiguous block.

logic [7:0] data[4]; // Array of 4 elements, each 8 bits

Queues: A dynamic data structure for storing elements of any size.

logic [7:0] queue[$]; // Dynamic queue of 8-bit logic values

 Structures and Unions:

Struct: A composite data type that groups related variables together.

typedef struct {
logic [7:0] byte1;

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logic [7:0] byte2;

} byte_pair_t;
byte_pair_t pair;

Parameters and Constants:

Parameters: Constants used to define hardware configurations that are set at compile time.

parameter WIDTH = 8;
logic [WIDTH-1:0] data;

Constants: Use const to declare compile-time constants.

const int MAX_VALUE = 255;

Pre/Post, Inc/Dec Operators:

Pre/Post Increment/Decrement:

Pre-increment: ++a increases a before using it.

Post-increment: a++ increases a after using it.

int a = 5;
int b = ++a; // b=6, a=6

Looping Statements:

System Verilog provides several looping constructs:

For loop:

for (int i = 0; i < 10; i++) begin

// Loop body
end

While loop:

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while (condition) begin

// Loop body
end

For each loop: Useful for iterating over arrays and queues.

For each (array[i]) begin

// Loop body
Wildcard Operators:

Wildcard Operators: Used in case statements to represent unspecified bits or ranges.

case (signal)
2'b10: // Matches only 2'b10
2'b1?: // Matches 2'b10, 2'b11
endcase

Interface, Modport, and Clocking Block:

Interface: A way to group signals together for better modularity and encapsulation.

interface simple_interface(input logic clk);

logic [7:0] data;
endinterface

Modport: Specifies which directions a port in an interface can have.

modport slave (input clk, input data);

Clocking Block: Used to define timing constraints for interfaces.

clocking cb @(posedge clk);

input data;
endclocking

Program Block:

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 Program Block: Used in verification to contain all simulation-related statements. It allows

for better code separation in testbenches.
 program my_program;
initial begin
// simulation code
end
endprogram

Casting:

 Casting: Allows conversion of one data type to another.

 int a = 5;
 logic [3:0] b = $cast(logic[3:0], a); // Cast int to 4-bit logic

Mailbox, Events, and Semaphore:

Mailbox: A communication mechanism for passing data between threads.

mailbox m;
m = new;

Events: Used for synchronization between processes.

event my_event;

Semaphore: Used to manage shared resources by controlling access between processes.

semaphore sem = new(1); // Initialize semaphore with 1 permit

Object-Oriented Programming (OOP) Concepts in SystemVerilog:

Class: A user-defined type that encapsulates data and methods.

class MyClass;
int data;
function void setData(int val);
data = val;

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endfunction
endclass

Handle:

A reference to an object, similar to a pointer in C.

MyClass obj = new;

Methods:

Functions defined within a class that operate on the object's data.

function int getData();

return data;
endfunction

Properties:

Special variables that can have automatic getter and setter methods.

class MyClass;
property int value;
get { return data; }
set { data = value; }
endproperty
endclass

Polymorphism:

The ability to define methods in a base class and override them in subclasses.

class BaseClass;
virtual function void display();
$display("Base Class");
endfunction
endclass

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class DerivedClass extends BaseClass;

function void display();
$display("Derived Class");
endfunction
endclass
Parameterized Classes:

Classes that can take parameters for flexibility.

class MyClass #(int WIDTH = 8);

logic [WIDTH-1:0] data;
endclass

Data Encapsulation and Hiding:

Hiding implementation details inside classes.

class MyClass;
private logic [7:0] data;
public function void setData(logic [7:0] val);
data = val;
endfunction
endclass

Randomization in SystemVerilog:

Randomization: Used to generate random values within constraints.

class MyClass;
int a;
constraint c { a > 0 && a < 10; }
endclass
MyClass obj = new;
obj.randomize();

If-Else in Constraints:

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constraint c {
if (a == 5) a == 10;
else a != 5;

 Static Constraints: Constraints that are known at compile time.

 constraint c { a == 5; }
 Unique Constraints: Ensures that random values satisfy the condition uniquely.

Coverage in System Verilog:

 Functional Coverage: Ensures that all functionalities of the design are exercised.
 covergroup cg;
 coverpoint state;
 endgroup
 Code Coverage: Measures how much of the code has been executed during simulation.
 coverpoint a: bin[4] {0, 1, 2, 3, 4};

Assertions in Programming:

Assertions are used to validate assumptions made by the programmer during the development phase.
They check if a condition is true; if it's false, the program will typically throw an error or crash.

Types of Assertions:

 Static Assertions: Evaluated at compile time.

 Dynamic Assertions: Evaluated during runtime.

Virtual Interface in OOPS:

A virtual interface is typically used in SystemVerilog, a hardware description language. It provides a

way to define and connect interfaces to different modules or classes. It's crucial for creating reusable
and modular code.

Mailbox (in OOPS/Verilog):

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A mailbox is a synchronization primitive in SystemVerilog (used for communication between

different processes or threads) or OOP-based designs, enabling safe data exchange between
components or threads.

Class Packet:

In the context of OOPS and hardware description languages, a class packet would refer to an object or
data structure containing relevant fields (like header, payload) to represent data packets transmitted
over a network or hardware bus.

ARM (Architecture):

ARM is a family of Reduced Instruction Set Computing (RISC) architectures, widely used in
embedded systems, mobile devices, and increasingly in server systems.

AMBA AXI (Advanced Microcontroller Bus Architecture - Advanced Extensible Interface):

AXI is a high-performance, high-bandwidth interface standard for connecting different components in

a system-on-chip (SoC). It is used for interconnecting CPUs, memory controllers, and peripherals in
ARM-based systems.

AXI Lab Session:

Typically, an AXI lab session would involve learning how to implement and test AXI interfaces,
understand various AXI transaction types (like read, write, burst transactions), and use tools like
simulation environments to verify AXI-based designs.

Block chain Mining Architecture:

Block chain mining refers to the process of validating and adding new transactions to the block chain
ledger. It involves solving complex cryptographic puzzles using computational resources.

ASIC (Application-Specific Integrated Circuit) Implementation:

ASIC is a custom-designed chip optimized for a particular application or task. ASIC implementation
typically involves the design of the hardware (using HDL like Verilog or VHDL), followed by
synthesis, placement, routing, and finally fabrication.

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VLSI (Very-Large-Scale Integration) Architecture for Wearable Devices:

VLSI involves integrating a large number of transistors on a single chip. In the context of wearable
devices, VLSI design focuses on creating energy-efficient, small-sized chips for fitness trackers,
smartwatches, and health monitoring systems, often using Machine Learning (ML) techniques for
optimizing performance.

Overview of IC Design Procedure:

The IC design procedure involves:

 Specification: Define the functionality.

 Architectural Design: Define the high-level design.
 Schematic Design: Detailed component-level design.
 Layout Design: Physical design of the chip.
 Verification: Functional and timing verification.
 Fabrication: Manufacturing the chip.

Device Model:

Device models describe how electronic devices behave under various conditions (e.g., current,
voltage). In VLSI, device models are used for simulation and validation of the IC before
manufacturing.

EOA (End of Life) Impact on Semiconductors:

EOA refers to when a product or technology reaches its end-of-life, and it's no longer supported or
manufactured. For semiconductor companies, this can affect the availability of components and
impact the supply chain, requiring migration to newer technologies.

Open Road:

OpenROAD is an open-source physical design tool that supports the entire design flow from RTL
(register-transfer level) to GDSII (graphical data stream) for tape-out. It includes modules for
placement, routing, and optimization of chip designs.

Understanding Basics of ASIC Design Flow:

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ASIC design involves multiple stages:

 RTL Design: Writing the functional description of the chip.

 Synthesis: Converting RTL into gate-level logic.
 Floorplanning: Determining the chip's physical layout.
 Placement & Routing: Positioning the components and connecting them.
 Verification: Ensuring the design meets specifications.

Complete Installation of ORFS (OpenROAD Flow Script):

OpenROAD Flow Script (ORFS) is used to automate the design process in OpenROAD. It is
important to install and configure OpenROAD along with the ORFS to run the full ASIC design flow.

Logical Synthesis Overview:

Logical synthesis is the process of transforming a high-level RTL design into a gate-level netlist. This
process involves optimization for area, speed, and power.

Introduction to YOSYS:

YOSYS is an open-source synthesis tool that converts RTL descriptions (e.g., Verilog) into gate-level
representations. It integrates with other tools in the ASIC design flow, and it's often used for open-
source ASIC projects.

Installation of YOSYS in OR (OpenROAD):

YOSYS can be installed within the OpenROAD framework to support synthesis tasks. It usually
involves setting up dependencies, configuring paths, and integrating YOSYS into the OpenROAD
tool chain.

Timing Analysis in OpenROAD:

Timing analysis is crucial to ensure that the design meets the required speed. OpenROAD provides
tools to analyze and optimize timing, ensuring the design will function at the expected clock speeds.

Introduction to Physical Design:

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Physical design in VLSI involves the steps required to translate a logical design into a physical layout
(such as placement of cells and routing). It includes tasks like floorplanning, placement, routing,
power distribution, and final verification.

Power Distribution and IR Drop Analysis:

Power distribution involves ensuring that the design can efficiently deliver power to all components.
IR drop analysis checks if there is a significant voltage drop in the power grid that could affect circuit
performance.

Placement Using Open ROAD:

Placement refers to the process of positioning the standard cells or components on the chip. Open
ROAD supports placement as part of the physical design flow, ensuring the design meets timing and
power requirements.

These topics represent a wide range of knowledge in digital design, semiconductor technology, and
ASIC/VLSI design, as well as the tools used in the industry for these tasks.

Clock Tree Synthesis in OpenROAD Flow Scripts:

Clock Tree Synthesis (CTS) is the process of designing and optimizing the clock distribution network
of an ASIC or FPGA. In OpenROAD, CTS ensures that clock signals reach all parts of the chip with
minimal skew and balanced latency.

Steps involved in CTS using OpenROAD Flow Scripts:

 Clock Definition: Set up the clock nets and constraints (frequency, period).
 Buffer Insertion: Insert buffers to balance the clock network.
 Skew Optimization: Minimize clock skew across the design.
 CTS Execution: Run the CTS tool in the OpenROAD flow to generate the clock tree.

Routing and Optimization Using OpenROAD:

Routing is the process of connecting the components in the layout with metal layers. OpenROAD
helps optimize routing by considering timing, area, and power constraints. It also minimizes wire
length and ensures the design meets all required specifications.

Routing Steps:

 Initial Routing: Set up routing resources and initial routes.

 Global Routing: Determine the global paths for routing.
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 Detailed Routing: Optimize routes for exact placement and timing.

 Optimization: Refine the routes to meet constraints like congestion, timing, and power.

Chip Finishing Using OpenROAD:

Chip finishing involves the final steps in the physical design flow. This includes ensuring that the
placement, routing, and clock tree are complete and meet design specifications. It also involves DRC
(Design Rule Check) and LVS (Layout vs. Schematic) verification.

Introduction to Linux and Basic Commands:

Linux is a powerful open-source operating system used in many engineering and development
environments. Basic Linux commands are essential for navigating the file system, managing files, and
running processes.

Basic Commands:

 ls — List files in a directory.

 cd — Change directory.
 cp — Copy files.
 mv — Move or rename files.
 rm — Remove files.
 pwd — Print current directory.
 man — Manual page for commands.
 echo — Print text to the console.

Process Management and Shell Scripting Basics in Linux:

Process Management in Linux involves managing the processes running on the system. You can
monitor, pause, or kill processes using commands like ps, top, kill, and bg.

Shell Scripting Basics:

 Variables: Store data in variables (e.g., name="John").

 Conditionals: Use if, elif, else to create decision structures.
 Loops: Use for, while loops for repeating tasks.
 Functions: Create reusable blocks of code with functions.
 File I/O: Read from and write to files.

Ripple Carry Adder Design and Testbench:

A Ripple Carry Adder (RCA) is a type of binary adder that calculates the sum of two binary
numbers. It propagates the carry bit through each bit in the addition.

Design:

 A series of full adders connected in a chain.

 The output of one adder is used as the carry for the next adder.

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Testbench:

 Apply various input combinations and check the sum and carry-out.

8-Bit Shifter Design and Testbench:

A Shifter performs bitwise shifting (left or right) on an 8-bit number.

Design:

 An 8-bit register and logic to shift bits left or right based on control signals.

Testbench:

 Apply different shift amounts and verify the shifted output.

Comparator Design and Testbench:

A Comparator compares two binary numbers and outputs whether they are equal, or if one is greater
than the other.

Design:

 Use basic logic gates (XOR, AND) to compare each bit and output results (greater, equal,
less).

Testbench:

 Apply equal and unequal inputs and verify the comparison results.

3-State Decoder Design and Testbench:

A 3-State Decoder takes in a 2-bit input and decodes it into one of three states, often used for
enabling different outputs.

Design:

 Implement a logic circuit that decodes 2-bit input to control three outputs.

Testbench:

 Apply all possible 2-bit inputs and verify the corresponding outputs.

Sequence Detector (110) Design and Testbench:

A Sequence Detector detects a specific sequence (like "110") in a stream of bits.

Design:
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 Use state machines to detect the sequence "110".

Testbench:

Apply various bit sequences and verify if the detector detects "110".

8-to-1 Multiplexer 8-bit Design and Testbench:

A Multiplexer (MUX) selects one of eight 8-bit inputs based on a 3-bit control signal.

Design:

 Use a combination of logic gates or a case statement to select one of the eight inputs.

Testbench:

 Apply all possible 3-bit control values and check the selected 8-bit input.

1-to-8 Demultiplexer 8-bit Design and Testbench:

A Demultiplexer (DEMUX) takes a single 8-bit input and directs it to one of eight outputs based on a
3-bit control signal.

Design:

 Use logic to route the 8-bit input to the appropriate output based on control signals.

Testbench:

 Apply various control signals and verify that the input is routed to the correct output.

4-Bit Adder and Subtractor Design and Testbench:

A 4-Bit Adder/Subtractor performs addition or subtraction on two 4-bit numbers. You can use an
XOR gate to implement subtraction (by taking two's complement).

Design:

 Adder: Use a full adder circuit.

 Subtractor: Use XOR gates for the subtraction and add logic for carry handling.

Testbench:

 Apply all combinations of 4-bit numbers and check the sum or difference.

Full Adder Design and Testbench:

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A Full Adder adds three input bits (two data bits and a carry-in) and produces a sum and carry-out.

Design:

 Use XOR, AND, and OR gates to produce sum and carry-out.

Testbench:

 Apply all combinations of the inputs and verify the sum and carry outputs.

Binary to Gray Code Design and Testbench:

Binary to Gray Code conversion involves converting a binary number to its equivalent Gray code.

Design:

 The MSB (Most Significant Bit) remains the same, and subsequent bits are obtained by
XORing the current bit with the previous bit in binary.

Testbench:

 Apply binary inputs and verify the corresponding Gray code outputs.

Arithmetic Logic Unit (ALU) Design (with if-enum Logic):

An ALU performs arithmetic and logical operations like addition, subtraction, AND, OR, and XOR.

Design:

 Use if-enum logic to select different operations based on control signals.

Testbench:

 Apply various operations (add, subtract, AND, etc.) and verify the results.

Priority Encoder Design and Testbench:

A Priority Encoder encodes the highest-priority input bit into a binary code.

Design:

 Encode input bits with priority based on the position of the 1 bit.

Testbench:

 Apply different input combinations and verify the priority encoding.

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CHAPTER 4

PROJECT HANDLED

Project: Design of an 4-bit up/down counter using Verilog/SystemVerilog/VHDL

Introduction

This report presents the RTL design and functional verification of an 4-bit up/down counter using
Verilog. The Up-Down Counter is a parameterized digital circuit that counts up or down based on a
control signal (i_up_down). It supports a configurable bit-width (WIDTH) and includes a reset signal
(i_rst) to initialize the counter. This module is widely used in applications like frequency division,
event counting, and timing control. Its flexibility and simplicity make it a fundamental component in
digital systems. The implementation was verified using EDA Playground with Aldec Riviera-PRO
simulator.

Truth table of 4-bit up/down counter

Design Architecture

The architecture consists of a clock (i_clk), reset (i_rst), and control signal (i_up_down). The counter
output (o_count) is parameterized to support any bit-width (WIDTH). On each clock edge, the counter
increments if i_up_down is 1 or decrements if i_up_down is 0. The reset signal initializes the counter
to 0. The design is synchronous, ensuring reliable operation in clock-driven systems.

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Block Diagram

RTL Code

`timescale 1ns / 1ps

module up_down_counter #(

parameter WIDTH = 4 // Parameter for counter bit-width (default: 4-bit)

input wire

input wire

input wire

i_clk,

i_rst,

// Clock signal

// Active-high reset

i_up_down, // Control signal: 1 for UP, 0 for DOWN

output reg [WIDTH-1:0] o_count // Parameterized width counter output

);

always @(posedge i_clk) begin

if (i_rst)

o_count <= {WIDTH{1'b0}}; // Reset counter to 0

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else if (i_up_down)

o_count <= o_count + 1; // Count up

else

o_count <= o_count - 1; // Count down

end

endmodule

Testbench Code

`timescale 1ns / 1ps

module tb_up_down_counter;

// Parameters

parameter WIDTH = 4; // Counter bit-width

// Inputs

reg i_clk;

reg i_rst;

reg i_up_down;

// Outputs

wire [WIDTH-1:0] o_count;

// Instantiate the Unit Under Test (UUT)

up_down_counter #(WIDTH) uut (

.i_clk(i_clk),

.i_rst(i_rst),

.i_up_down(i_up_down),

.o_count(o_count)

);

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// Clock generation

initial begin

i_clk = 0;

forever #5 i_clk = ~i_clk; // Toggle clock every 5 time units

end

// Testbench logic

initial begin

// Initialize inputs

i_rst = 1;

i_up_down = 0;

// Wait for global reset

#10;

i_rst = 0;

// Test case 1: Count up

i_up_down = 1; // Set to count up

#10; // Wait for one clock cycle

$display("Test Case 1: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 1: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 1: i_up_down = %b, o_count = %b", i_up_down, o_count);

// Test case 2: Count down

i_up_down = 0; // Set to count down

#10; // Wait for one clock cycle

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$display("Test Case 2: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 2: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 2: i_up_down = %b, o_count = %b", i_up_down, o_count);

// Test case 3: Reset

i_rst = 1; // Reset the counter

#10;

$display("Test Case 3: i_rst = %b, o_count = %b", i_rst, o_count);

// Test case 4: Count up after reset

i_rst = 0; // Disable reset

i_up_down = 1; // Set to count up

#10; // Wait for one clock cycle

$display("Test Case 4: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 4: i_up_down = %b, o_count = %b", i_up_down, o_count);

// Test case 5: Count down after reset

i_up_down = 0; // Set to count down

#10; // Wait for one clock cycle

$display("Test Case 5: i_up_down = %b, o_count = %b", i_up_down, o_count);

#10; // Wait for another clock cycle

$display("Test Case 5: i_up_down = %b, o_count = %b", i_up_down, o_count);

// End simulation

$finish;

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end

endmodule

Simulation & Verification

Testbench Setup:

Inputs and Outputs:

i_clk is the clock signal.

i_rst is the active-high reset signal.

i_up_down is the control signal:

1: Count up.

0: Count down.

o_count is the counter output.

Simulation Results

Expected Output:

Test Case 1: i_up_down = 1, o_count = 0001

Test Case 1: i_up_down = 1, o_count = 0010

Test Case 1: i_up_down = 1, o_count = 0011

Test Case 2: i_up_down = 0, o_count = 0010

Test Case 2: i_up_down = 0, o_count = 0001

Test Case 2: i_up_down = 0, o_count = 0000

Test Case 3: i_rst = 1, o_count = 0000

Test Case 4: i_up_down = 1, o_count = 0001

Test Case 4: i_up_down = 1, o_count = 0010

Test Case 5: i_up_down = 0, o_count = 0001

Test Case 5: i_up_down = 0, o_count = 0000

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Simulated Input-Output Waveforms

Results and Discussion

The 4-bit Up/Down Counter was successfully implemented and verified. The simulation
results matched the expected behavior, confirming the correctness of the design.

EDA Link : https://edaplayground.com/x/ajDb

Functional Verification of the design using UVM.

Testbench Architecture (50%)

- Proper use of UVM components

- Adherence to the UVM factory and configuration mechanism.

- Proper use of virtual sequences and sequence layering if applicable.

Driver

class up_down_counter_driver extends uvm_driver #(up_down_counter_sequence_item);

`uvm_component_utils(up_down_counter_driver)

virtual up_down_counter_if vif;

up_down_counter_sequence_item item;

function new(string name = "up_down_counter_driver", uvm_component parent);

super.new(name, parent);

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`uvm_info("up_down_counter_driver", "Inside constructor of up_down_counter_driver",

UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

if (!(uvm_config_db #(virtual up_down_counter_if)::get(this, "*", "up_down_counter_vif",

vif)))

`uvm_error(get_name(), "Failed to get Virtual IF from database")

endfunction: build_phase

task run_phase(uvm_phase phase);

super.run_phase(phase);

`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

forever begin

this.item = uvm_object_registry#(up_down_counter_sequence_item,

"up_down_counter_sequence_item")::create("item");

seq_item_port.get_next_item(item);

drive(item);

seq_item_port.item_done();

end

endtask

task drive(up_down_counter_sequence_item item);

`uvm_info(get_name(), "Drive...", UVM_HIGH)

@(posedge vif.i_clk);

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vif.i_up_down = item.i_up_down;

endtask

endclass: up_down_counter_driver

Monitor

class up_down_counter_monitor extends uvm_monitor;

`uvm_component_utils(up_down_counter_monitor)

virtual up_down_counter_if vif;

up_down_counter_sequence_item item;

uvm_analysis_port #(up_down_counter_sequence_item) mon_port;

function new(string name = "up_down_counter_monitor", uvm_component parent);

super.new(name, parent);

`uvm_info("up_down_counter_monitor", "Inside constructor of

up_down_counter_monitor", UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

mon_port = new("mon_port", this);

if (!(uvm_config_db #(virtual up_down_counter_if)::get(this, "*", "up_down_counter_vif",

vif)))

`uvm_error(get_name(), "Failed to get Virtual IF from database")

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

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`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);

`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

forever begin

this.item = uvm_object_registry#(up_down_counter_sequence_item,

"up_down_counter_sequence_item")::create("item");

// Use the encoded string here if needed

string encoded_item_name = $cast(string, encoded_string);

sample(item);

`uvm_info(get_name(), "Item received!!", UVM_HIGH)

mon_port.write(item);

end

endtask

task sample(up_down_counter_sequence_item item);

@(posedge vif.i_clk);

item.i_up_down = vif.i_up_down;

item.o_count = vif.o_count;

endtask

endclass: up_down_counter_monitor

Agent

class up_down_counter_agent extends uvm_agent;

`uvm_component_utils(up_down_counter_agent)

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up_down_counter_driver drv;

up_down_counter_monitor mon;

up_down_counter_sequencer seqr;

function new(string name="up_down_counter_agent",uvm_component parent);

super.new(name,parent);

`uvm_info("up_down_counter_agent", "Inside constructor of up_down_counter_agent",

UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

drv=up_down_counter_driver::type_id::create("drv",this);

mon=up_down_counter_monitor::type_id::create("mon",this);

seqr=up_down_counter_sequencer::type_id::create("seqr",this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

drv.seq_item_port.connect(seqr.seq_item_export);

endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);

`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

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endtask

endclass: up_down_counter_agent

Environment

class up_down_counter_env extends uvm_env;

`uvm_component_utils(up_down_counter_env)

up_down_counter_agent agent;

up_down_counter_scoreboard scb;

function new(string name = "up_down_counter_env", uvm_component parent = null);

super.new(name, parent);

`uvm_info("up_down_counter_env", "Inside constructor of up_down_counter_env",

UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

agent = up_down_counter_agent::type_id::create("agent", this);

scb = up_down_counter_scoreboard::type_id::create("scb", this);

endfunction : build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

agent.mon.mon_port.connect(scb.scb_port);

endfunction : connect_phase

endclass : up_down_counter_env

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Test

class up_down_counter_test extends uvm_test;

`uvm_component_utils(up_down_counter_test)

up_down_counter_env env;

function new(string name="up_down_counter_test",uvm_component parent);

super.new(name,parent);

`uvm_info("up_down_counter_test", "Inside constructor of up_down_counter_test",

UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

env=up_down_counter_env::type_id::create("env",this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

endfunction

endclass: up_down_counter_test

class up_down_counter_mul_test extends up_down_counter_test;

`uvm_component_utils(up_down_counter_mul_test)

up_down_counter_mul_seq mul_seq;

function new(string name="up_down_counter_mul_test",uvm_component parent);

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super.new(name,parent);

`uvm_info("up_down_counter_mul_test", "Inside constructor of

up_down_counter_mul_test", UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);

`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);

repeat(`TEST_COUNT) begin

mul_seq=up_down_counter_mul_seq::type_id::create("mul_seq");

mul_seq.start(env.agent.seqr);

end

wait(env.scb.test_cnt==`TEST_COUNT);

phase.drop_objection(this);

endtask

endclass: up_down_counter_mul_test

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Testbench

`include "uvm_macros.svh"

import uvm_pkg::*;

`define TEST_COUNT 200

`include "interface.sv"

`include "sequence_items.sv"

`include "sequencer.sv"

`include "sequence.sv"

`include "driver.sv"

`include "monitor.sv"

`include "scoreboard.sv"

`include "agent.sv"

`include "environment.sv"

`include "test.sv"

`timescale 1ns/1ns

`include "uvm_macros.svh"

//`include "reference.c"

import "DPI-C" function int floatOperations(int op1, int op2);

import "DPI-C" function int errors(int op1, int op2 );

import "DPI-C" function void print_hello() ;

//print_hello()

module top;

bit i_clk=0;

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bit i_rst;

up_down_counter_if top_if(i_clk , i_rst);

up_down_counter dut(

. i_clk (top_if. i_clk),

.i_rst (top_if.i_rst),

.i_up_down (top_if.i_up_down),

.o_count (top_if.o_count)

);

initial forever #0.5 i_clk =~i_clk;

initial begin

i_rst = 1;

#2 i_rst =0;

end

initial begin

uvm_config_db #(virtual up_down_counter_if) ::

set(null,"*","up_down_counter_vif",top_if);

`uvm_info("TOP","Configured database for interface...",UVM_LOW)

end

initial begin

run_test("up_down_counter_test");

end

initial begin

$dumpfile("waveform.vcd");

$dumpvars;

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end

initial begin

#10000000;

$finish();

end

endmodule

Stimulus Generation

- Development of constrained-random and directed test sequences.

- Use of UVM sequences and transaction-based stimulus generation.

- Ability to generate different corner cases and invalid scenarios.

- Parameterization and reuse of sequences.

Sequence Item

class up_down_counter_sequence_item extends uvm_sequence_item;

randc logic i_up_down; // Control signal: 1 for UP, 0 for DOWN

logic [3:0] o_count ; // Parameterized width counter output

function new(string name="up_down_counter_sequence_item");

super.new(name);

endfunction

endclass

Sequence

class up_down_counter_sequencer extends uvm_sequencer

#(up_down_counter_sequence_item);

`uvm_component_utils(up_down_counter_sequencer)

function new(string name="up_down_counter_sequencer",uvm_component parent);

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super.new(name,parent);

`uvm_info("up_down_counter_sequencer", "Inside constructor of

up_down_counter_sequencer", UVM_HIGH)

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)

endfunction

endclass: up_down_counter_sequencer

Scoreboarding and Checking

- Implementation of functional and self-checking scoreboard.

- Use of predictive models and golden reference comparison.

- Effective use of UVM phases for checking.

Scoreboard

class up_down_counter_scoreboard extends uvm_scoreboard;

`uvm_component_utils(up_down_counter_scoreboard)

uvm_analysis_imp #(up_down_counter_sequence_item, up_down_counter_scoreboard)

scb_port;

up_down_counter_sequence_item item[$];

up_down_counter_sequence_item s_item;

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int test_cnt = 0;

int test_valid = 0;

int test_invalid = 0;

virtual up_down_counter_if vif;

function new(string name = "up_down_counter_scoreboard", uvm_component parent);

super.new(name, parent);

`uvm_info("SCB_CLASS", "Inside Constructor!", UVM_HIGH)

if (!(uvm_config_db #(virtual up_down_counter_if)::get(this, "*", "up_down_counter_vif",

vif)))

`uvm_error(get_name(), "Failed to get Virtual IF from database")

endfunction: new

function void build_phase(uvm_phase phase);

super.build_phase(phase);

`uvm_info("SCB_CLASS", "Build Phase!", UVM_HIGH)

scb_port = new("scb_port", this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

`uvm_info("SCB_CLASS", "Connect Phase!", UVM_HIGH)

endfunction: connect_phase

function void write(up_down_counter_sequence_item rx_item);

item.push_front(rx_item);

endfunction

task run_phase(uvm_phase phase);

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super.run_phase(phase);

forever begin

this.s_item = uvm_object_registry#(up_down_counter_sequence_item,

"up_down_counter_sequence_item")::create("s_item");

wait((item.size() != 0));

s_item = item.pop_front();

// s_item.print();

compare(s_item);

test_cnt++;

end

endtask

function void compare(up_down_counter_sequence_item item);

logic [7:0] ex_res;

ex_res = get_expected_count(item.o_count, vif.i_rst, item.i_up_down);

if (ex_res == item.o_count) begin

`uvm_info(get_name, $sformatf("[%0d/%0d] Test Passed", test_cnt, `TEST_COUNT),

UVM_HIGH);

test_analysis(item, ex_res, 1);

test_valid++;

end else begin

`uvm_error(get_name, $sformatf("[%0d/%0d] Test failed", test_cnt, `TEST_COUNT));

test_analysis(item, ex_res, 1);

test_invalid++;

end

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endfunction

function void test_analysis(up_down_counter_sequence_item item, logic [31:0] ex_res, bit

flag);

if (flag) begin

$display("--------------------------------------------------------------------------------");

$display("i_up_down= %0b,

o_count= %0b, expected= %0b,", item.i_up_down, item.o_count, ex_res);

end

endfunction

function automatic bit [3:0] get_expected_count(bit [3:0] current_count, bit i_rst, bit

i_up_down);

if (i_rst)

return 4'b0000; // Reset counter to 0

else if (i_up_down)

return current_count; // Count up

else

return current_count; // Count down

endfunction

function void report_phase(uvm_phase phase);

super.report_phase(phase);

`uvm_info(get_name, $sformatf("Total tests: %0d", test_cnt), UVM_LOW)

`uvm_info(get_name, $sformatf("Passed tests: %0d", test_valid), UVM_LOW)

`uvm_info(get_name, $sformatf("Failed tests: %0d", (test_invalid / test_cnt) * 100),

UVM_LOW)

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endfunction

endclass

Debugging and Logs

- Effective use of UVM messaging and verbosity levels.

- Debugging skills and ability to interpret waveforms and logs.

- Error detection.

- Documentation of issues and resolutions.

Reference

#include <stdio.h>

#include <math.h>

#include <stdint.h>

// Define the threshold for error checking: 2^-22 (approximately 2.38e-7)

#define THRESHOLD (1.0f / (1 << 23)) // 'f' ensures single-precision floating point

// Function to perform floating-point multiplication on integer representations

int floatOperations(int op1, int op2) {

float floatOp1 = *(float*)&op1; // Convert integer representation to float

float floatOp2 = *(float*)&op2; // Convert integer representation to float

float floatResult;

// Perform multiplication

floatResult = floatOp1 + floatOp2;

// Convert float result back to integer representation and return

return *(int*)&floatResult;

// Function to compute and check relative error between two floating-point values

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int errors(int op1, int op2) {

float ideal = *(float*)&op1; // Convert integer representation to float

float actual = *(float*)&op2; // Convert integer representation to float

float relative_error;

// Calculate relative error

relative_error = fabs((ideal - actual) / ideal);

// Check if the relative error exceeds the defined threshold

if (relative_error > THRESHOLD) {

printf("Relative error (%.10f) exceeds threshold (%.10f).

", relative_error, THRESHOLD);

return 1; // Error exceeds threshold

} else {

// printf("Relative error (%.10f) is within threshold (%.10f).

", relative_error, THRESHOLD);

return 0; // Error is within acceptable range

void print_hello() {

printf("Hello, World!

");

Waveform (In Testbench)

initial begin

$dumpfile("dump.vcd");

$dumpvars();

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end

UVM Report

Code Quality and Best Practices

- Consistency in naming conventions and coding style.

- Use of parameterized and reusable components.

- Proper comments and documentation within the code.

- Efficient and optimized coding practices.

EDA LInk : https://edaplayground.com/x/9JY2

Generate GDS-II layout of the design using OpenROAD-flowscripts tool.

In this section, the layout of the RTL code has been generated using the OpenROAD
software tool.

Technology/Platform utilized: sky130hd

Instructions of the config.mk

export DESIGN_NAME = ud_counter

export PLATFORM = sky130hd

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ud_counter.v

export SDC_FILE =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

# Adders degrade GCD

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export ADDER_MAP_FILE :=

export CORE_UTILIZATION = 10

export TNS_END_PERCENT = 100

export EQUIVALENCE_CHECK ?= 1

export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd__tapvpwrvgnd*

Instructions of the constraint.sdc

current_design ud_counter

set clk_name core_clock

set clk_port_name clk

set clk_period 2.5

set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs

set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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Performance Analysis

Power Measurement:

=============================================================

finish report_power

------------------------------------------------------------------

Group Internal Switching Leakage Total

Power Power Power Power (Watts)

------------------------------------------------------------------

Sequential 1.40e-04 1.27e-05 6.61e-11 1.53e-04 53.9%

Combinational 1.90e-05 1.47e-05 7.09e-11 3.37e-05 11.9%

Clock 5.48e-05 4.24e-05 1.38e-11 9.72e-05 34.3%

Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%

Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%

------------------------------------------------------------------

Total 2.14e-04 6.97e-05 1.51e-10 2.84e-04 100.0%

75.4% 24.6% 0.0%

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=============================================================

Area Measurement:

Design area 398 u^2 14% utilization

Slack Information:

Fanout Cap Slew Delay Time Description

-------------------------------------------------------------------

1 0.00 0.00 0.00 0.00 clock core_clock (rise edge)

clock network delay (propagated)

clock external delay

1 0.00 0.00 0.00 0.00 rst (in)

rst (net)

8 0.03 0.16 0.07 0.07 input2/A (sky130_fd_sc_hd__clkbuf_2)

1 0.03 0.16 0.07 0.14 input2/X (sky130_fd_sc_hd__clkbuf_2)

1 0.03 0.16 0.07 0.21 net2 (net)

4 0.08 0.17 0.09 0.30 _27_/B (sky130_fd_sc_hd__nor2_1)

1 0.08 0.17 0.09 0.39 _27_/X (sky130_fd_sc_hd__nor2_1)

1 0.08 0.17 0.09 0.48 _24_ (net)

1 0.08 0.17 0.09 0.57 count_value[0]$SDFF_PP0/D (sky130_fd_sc_hd__dffxtp_1)

data arrival time

-------------------------------------------------------------------

1 0.00 0.00 0.00 0.00 clock core_clock (rise edge)

clock source latency

1 0.00 0.00 0.00 0.00 clk (in)

clk (net)

1 0.80 0.08 0.11 0.11 clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.11 0.22 clkbuf_0_clk/Y (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.11 0.33 clkbuf_1_clk/A (sky130_fd_sc_hd__clkbuf_4)

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1 0.80 0.08 0.11 0.44 clkbuf_1_clk/Y (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.11 0.55 count_value[0]$SDFF_PP0/CLK (sky130_fd_sc_hd__dffxtp_1)

clock reconvergence pessimism

library hold time

0.20 data required time

0.72 data arrival time

0.52 slack (MET)

Fanout Cap Slew Delay Time Description

-------------------------------------------------------------------

1 0.01 0.00 0.00 0.00 clock core_clock (rise edge)

clock source latency

1 0.01 0.00 0.00 0.00 clk (in)

clk (net)

1 0.80 0.08 0.04 0.04 clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.04 0.08 clkbuf_0_clk/Y (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.04 0.12 clk (net)

1 0.80 0.08 0.04 0.16 clkbuf_1_clk/A (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.04 0.20 clkbuf_1_clk/Y (sky130_fd_sc_hd__clkbuf_4)

1 0.80 0.08 0.04 0.24 clk (net)

1 0.80 0.08 0.04 0.28 count_value[0]$SDFF_PP0/CLK

(sky130_fd_sc_hd__dffxtp_1)

1 0.80 0.08 0.04 0.32 count_value[0]$SDFF_PP0/Q (sky130_fd_sc_hd__dffxtp_1)

3 - - 0.03 0.35 _39_/A (sky130_fd_sc_hd__or3_1)

2 - - 0.03 0.38 _39_/X (sky130_fd_sc_hd__or3_1)

2 - - 0.03 0.41 _45_/A (sky130_fd_sc_hd__or3_1)

2 - - 0.03 0.44 _45_/X (sky130_fd_sc_hd__or3_1)

2 - - 1.49 1.49 _46_/A (sky130_fd_sc_hd__o21a_0)

2 - - 1.49 1.49 _46_/X (sky130_fd_sc_hd__o21a_0)

1 0.80 0.08 0.04 1.53 output7/A (sky130_fd_sc_hd__clkbuf_1)

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1 0.80 0.08 0.04 1.57 output7/Y (sky130_fd_sc_hd__clkbuf_1)

1 0.80 0.08 0.04 1.59 wrapped (out)

data arrival time

-------------------------------------------------------------------

1 2.50 2.50 2.50 2.50 clock core_clock (rise edge)

clock network delay (propagated)

clock reconvergence pessimism

2.00 data required time

1.59 data arrival time

0.41 slack (MET)

Generated GDS

Github link

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https://github.com/preetisutar/4-bit-updown-counter-

Conclusions

In this report, the RTL code of 4-bit Up/down counter has been designed in verilog. The code is
successfully verified with the UVM with 100% test case pass. The design code is further processed in
the openROAD tool to generate its GDS using the sky130hd platform. It has shown that the generated
layout consumes 0.284 mW power which occupies 398 sq. um area. There is no setup and hold
violations

Advantages

Verilog for Design

 Hardware Modeling: Accurately describes digital circuits.

 Synthesizable: Can be directly implemented in hardware.

 Reusable & Scalable: Easily extended for larger designs.

UVM for Verification

 Automated Testbenches: Reduces manual effort.

 Randomized Testing: Enhances test coverage.

 Modular & Scalable: Reusable test environments.

OpenROAD for Physical Design

 Open-source: No licensing costs.

 Optimization: Improves area, timing, and power.

 Scalability: Suitable for complex digital designs.

Applications
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Applications of 4-bit up/down counter

1. Digital Electronics & Microcontrollers – Used for event counting, frequency division, and
state tracking in embedded systems.
2. Timers & Clocks – Helps in timekeeping and delay generation in digital circuits.
3. Digital Speedometers – Counts pulses from sensors to measure speed in vehicles.
4. Elevator Control Systems – Tracks floor levels in both upward and downward directions.
5. Rotary Encoder Interface – Determines the position of rotating objects like motors or volume
knobs.

CHAPTER 5

CONCLUSION ON INTERNSHIP

In conclusion, my internship at ROOMAN provided valuable hands-on experience in the full

VLSI design flow, from Verilog HDL design of an 8-bit magnitude comparator to functional
verification using UVM and physical layout generation with OpenROAD. I gained insights
into optimizing designs for area, power, and timing, along with exposure to industry-standard
tools and techniques. The internship enhanced my technical skills in digital design,
verification, and physical implementation, preparing me for future roles in electronics and
semiconductor design. Overall, it was an enriching experience that strengthened my problem-
solving abilities and practical knowledge in the field.

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