Design, Synthesis, Verification

RTL to GDS Flow

ECE 425 – Intro to VLSI System Design

Dong Kai Wang

Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Overall Flow

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General RTL Practices (I)

• Design and Synthesize Concurrently

• Do NOT wait until you’re done w/ RTL design to start synthesis.
• Discover issues early!
• Document your Designs
• /*Comment your code*/
• Label all blocks (e.g., always_comb begin : BlockName … end : BlockName)
• Create block diagrams, module functionality descriptions, specs.
• Isolate Code Blocks for Synthesis and Verification
• Use compiler Macros to isolate non-synthesizable code.
• Bottom-up Approach
• Start with base modules first.

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RTL Bad Practices

• What’s wrong here?

Will infer latches!

(cover all conditions)
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RTL Bad Practices

• What’s wrong here? (Verilog)

Sensitivity list

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General RTL Practices (II)

• Avoid Ambiguity / Unintended Inferences

• Cover all conditions (e.g., case statements should always have default).
• Always statements should specify outputs under all conditions.
• Avoid hi-Z outputs, use multiplexers when possible.
• Design Synchronous Logic
• Avoid unexpected synthesis of latches.
• Avoid asynchronous logic.
• Variable Naming
• Suffix all Module Inputs/Outputs with “_i” and “_o” respectively (e.g., input logic clk_i).
• Prefix all Enum names with “k” (e.g., kopLUI).
• Give meaningful (easy to identify) names to nets, easy to track down in EDA tools.
• Reference Online Material

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General Naming Conventions

Adapted from Design Compiler User Guide.

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Designing with SystemVerilog

• More complex and powerful than you think!

• Most advanced features used for verification.
• You will likely use a small subset of features.
• Synthesize as you design
• What will each block synthesize to?
• Recommend bottom-up compile strategy.
• Consult the DC user guide.
• Verify as you design Verilog to SystemVerilog feature growth chart.
Adapted from Sutherland and Mills.
• Unit test your modules.
• Document as you design
• Draft a specifications document.

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Packages and Macros

• Packages allows different modules to access shared types

• Declare structs and enums in the package.
• Macros are useful to isolate Code Blocks
• Also useful for setting hard constants.
• Parametrize nets and modules where applicable

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Packages and Macros

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 Some Examples

A specifications check on parameters

Printing verbose messages in module

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Per-Module Logging Example

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Other Useful Features

• Tasks and Functions

• Common / shared subroutines.
• Synthesizable if you avoid things like time delays.
• Classes
• Similar to object-oriented programming.
• Member variables and functions.
• Consult references online.
• Assertions
• Property checking.

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Designing for DC: Combinational Paths

• Avoid unnecessary module hierarchy.

• Avoid module-crossing “glue logic” on combinational paths.

Adapted from Design Compiler User Guide.

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Designing for DC: Sharing Resources

// A Bad Idea (Why?)

assign Z = CTL ? (A + B) : (C + D);

Adapted from Design Compiler User Guide.

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Verification Basics

• Architecture Specifications
• Expected behavior / functionality of design.
• RTL-level Design Verification (DV)
• Checks RTL design against specifications.
• Design engineers vs. verification engineers.
• Verification before synthesis.
• Testbench (TB)
• Assertions (SVA)
• Design under Test (DUT)

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Testbench Structure

1. Generate Stimulus (Input Vectors)

• Directed or random tests.
• Catch bugs you expect or didn’t think of.

• Constrained random tests.

2. Apply stimulus to DUT

3. Capture the Response
4. Check for Correctness
▪ Comparison with expected results.
▪ Scoreboard / reference “golden” model.

5. Measure Overall Progress

▪ Functional coverage.

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Testbench Structure

1. Generate Stimulus (Input Vectors)

• Directed or random tests.
• Catch bugs you expect or didn’t think of.

• Constrained random tests.

2. Apply stimulus to DUT

3. Capture the Response
4. Check for Correctness
▪ Comparison with expected results.
▪ Scoreboard / reference “golden” model.

5. Measure Overall Progress

▪ Functional coverage.

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Useful SystemVerilog Types (I)

• Multidimensional Arrays
• C-style declaration: int array [16][8];
• SV-style declaration: int myarray [15:0][7:0];
• Packed vs unpacked: logic [31:0] myarray [15:0][7:0];
• Printing contents (see example testbench).
• Dynamic Arrays (non-Synthesizable)
• Declare without index range and use the new operator.
• Queues
• Similar to C++ standard library queues, declare with dollar sign: q[$]
• q.insert(); q.delete(); q.pop_front(); q.push_back();

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2D Array Example

• This example creates a

4-by-4 array and prints its
contents.

• Output:

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Dynamic Array Example

• This example creates a

dynamic array of size 5
and copies its content to
another dynamic array.

• Output:

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Useful SystemVerilog Types (II)

• Associative Arrays
• Implements a lookup table (dictionary).
• Good for large arrays range where few elements are accessed.
• Declare using datatype in brackets: int assocarray [int];
• Linked Lists
• Avoid, use queues instead.
• Custom Types
• Declare custom types for your design.
• Example: typedef struct {logic [7:0] r, g, b;} pixel_type;
• pixel_type my_pixel // Declare my_pixel as type pixel_type
• my_pixel.r = 8’b00000000; // Assigning individual member of my_pixel

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Useful SystemVerilog Types (III)

• Unions
• Different ways to interpret data (e.g., 32-bit logic could be integer or floating-point).
• Useful when you write data in different formats.
• typedef union { int i, logic [31:0] raw, real f } single_numtype;
• single_numtype my_number;
• my_number.f = 0.0; // Interpret my_number in float format and assign 0;

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Union Example

• Union Example.

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Routines: Tasks and Functions

• SystemVerilog provides tasks and functions similar in C-style synthax.

• Tasks can have time delays.
• Useful for code reuse, encapsulate common routines in tasks or functions.
• C-style task / function synthax:
• task mytask (input logic [31:0] x, output logic y); … endtask
• Example for resetting the ALU:

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General Tips

• You can write verification code directly in design modules.

• Use compiler macros to isolate simulation-only code.
• Use the %m format to print current instance.
• Direct access to local signals.
• Make use of File I/O.
• Reading from files $readmemh.
• Logging files (see example).
• Verify as you design.
• Don’t wait until design is done to start writing your testbench.
• Unit testing is very useful.
• Write individual testbenches for each unit if necessary.

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File Logging in Module Example

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Input Randomization

• It is best to randomize inputs to your DUT in addition to directed tests.

• e.g., testing a new type of ALU.
• SystemVerilog provides useful features for randomization.
• Which inputs to randomize?
• Device configuration
• Environment configuration
• Input data
• Protocol exceptions
• Errors and violations
• Delays (when uncertain)

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SystemVerilog Randomization

• Easiest method: use $random or $urandom to generate a random number.

• my_input = $random(optional_seed)
• Specify a range.
• urandom_range(int unsigned maxval, int unsigned minval = 0);
• To learn more about constraints, distributions, etc. check Canvas resources.

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Why Assertions?

• An assertion is a check
against specifications
• Improved Observability
• Check design locally.
• Bugs may not propagate.
• Early Bug Detection
• Write assertions during design.
• Assists Documentation
• Improved Reuse
• Formal Verification

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Immediate Assertions

• Think of assert like an if-statement.

• Instead of if-else, we use assert-else.
• Report errors by severity: $warn, $error, $fatal.
• Synthax is simple:
• optional_label: assert (condition) begin {code_if_pass} end
• else begin {code_if_fail} end

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Example ALU Circuit

• Check correctness of adder.

• Use an immediate assertion when an add
instruction is encountered.

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Immediate Assertions Example

• Example that checks addition result is correct.

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Concurrent Assertion

• Immediate assertions can’t express complex properties of design.

• E.g., ALU must output valid output 1 cycle after receiving instruction enable.
• Explicitly declare the expected behavior as a Sequence:
• sequence mySeq; alu_en ##1 valid; endsequence
• Declare a Property that triggers the sequence:
• property myProp; @(posedge clk) instr_en |-> mySeq; endproperty
• Assert the property:
• The property itself isn’t evaluated, needs to be asserted for simulator to check.
• myAssertion: assert property (myProp) $display(“assertion passed at
$stime”); else $error(“assertion failed at …”);

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Concurrent Assertion Example

• Concurrent assertion checks

that adder produces a valid
output after a valid (enable)
instruction is seen.

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Concurrent Assertion Example

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RTL Synthesis

TECH
Design Plan GTECH LIB Gate
High-level diagrams HDL Bool
and schematics NL

Architecture
Functional arch/uarch
description, simulator Synthesis Software
(e.g., Synopsys DC)

Physical Post-Silicon
RTL
Gate Level Implementation Bringup, signal
Structural and
Netlist Floorplan, layout, integrity, functional
behavioral HDL
CTS, PnR validation, perf.

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Launching Synopsys DC

• Load the Synopsys module

• module load Synopsys_x86-64/2021
• Launch from your project directory
• Reminder that default initialization scripts are hidden (.synopsys_dc.setup).
• Run: dc_shell or design_vision
• Use script: dc_shell –f my_script.tcl
• Make sure you have X11 forwarding enabled to use GUI.
• Specify libraries
• Target library: library used for technology mapping (NAND gates, NOT gates).
• Symbol library: library used for displaying circuit schematics in DC GUI.
• Link library: library used to reference cells (custom memories, etc.).

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Directory Structure

• Bottom-up Synthesis Strategy

Adapted from Design Compiler User Guide

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Constraint-driven Synthesis

• Synthesis is constraints-driven.
• You specify design targets via constraints.
• DC performs static timing analysis (STA).
• Checks all timing paths for best/worst-case.

Adapted from Design Compiler User Guide

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Synthesis Flow

• What to provide:
• Design files in HDL
• analyze (check synthax)

• elaborate (elaborate to gtech / b. box)

• read_file (analyze + elaborate)

• Technology library
• set_target_library, link, symbol

• Design constraints
• Covered later

• Compile and report:

• compile

• report_area / power / timing Adapted from Design Compiler User Guide

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Module Synthesis

Adapted from Design Compiler User Guide

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Technology Library

/* --------------- *
* Design : AND2X1 *
* --------------- */
cell (AND2X1) { Cell Name
area : 2.346500; Cell Area
cell_leakage_power : 15.6059;
pin(A) {
direction : input;
capacitance : 0.00229149; Electrical
rise_capacitance : 0.00229149; Characteristics
fall_capacitance : 0.00187144; of Input Pins
}
pin(B) {
direction : input;
capacitance : 0.00234289;
rise_capacitance : 0.00234289;
fall_capacitance : 0.00182664;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.137429;
Adapted from gscl45nm.lib function : "(A B)"; Pin Y Functionality
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DesignWare Library

• DC comes with DesignWare (DW) soft IPs.

• DC can choose from multiple implementation options for operators.
• Will optimize based on your design constraints.

Adapted from Synopsys Website

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Timing Terminology

• Clock Period
• 1/F
• Setup and Hold times
• Tsu & Th
• Slack
• Requirement – Arrival Time
• Clock Skew
• Delay from clock propagation
• Transition Time
• Signal transition time (rise / fall)

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DC Terminology

• Designs: TOP, REGFILE, ENCODER

• References: ENCODER, REGFILE, INV
• Cells: U1, U2, U3, U4

Adapted from Synopsys Website

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DC Terminology

• Designs: TOP, REGFILE, ENCODER

• References: ENCODER, REGFILE, INV
• Cells: U1, U2, U3, U4

Adapted from Synopsys Website

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Useful Commands

• get_cells cellname # for example, get_cells *

• get_nets netname
• get_ports portname
• get_clocks clockname # need to create_clock first
• all_inputs # lists all inputs of current design
• all_outputs # lists all outputs of current design

• analyze # basic checks (e.g., SV synthax)

• elaborate # elaborates RTL to generic “black boxes”
• read_file # analyze + elaborate
• current_design # set current design
• check_design # check for issues, e.g., mismatched ports, naming

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Specifying Clocks

• Define a Clock.
• Must define clock source, clock period.
• Can also define duty cycle, offset / skew, clock name.
• create_clock -name "CLK" -period 1.000 -waveform { 0.500 1.000 } { clk }
• Use report_clock to see that you have successfully defined a clock.
• Will have separate lecture on multiple clock domains.

Adapted from Synopsys Website

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I/O Delays

• Define a Clock. ✓
• Define I/O timing relative to clocks.

Adapted from Synopsys Website

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Input Delays

Adapted from Synopsys Website

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Input Delays

• Define a Clock. ✓
• Define I/O timing relative to clocks.
• DC calculates time constraints for internal logic.
• Use the set_input_delay command.
• set_input_delay -max 0.2 -clock CLK [get_ports inputA]

Adapted from Synopsys Website

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Input Delays

Adapted from Synopsys Website

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Output Delays

Adapted from Synopsys Website

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Output Delays

• Define a Clock. ✓
• Define I/O timing relative to clocks. ✓
• set_output_delay -max 0.3 -clock CLK [get_ports outputY]

Adapted from Synopsys Website

• Compile: compile -area_effort medium -map_effort medium

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More Useful Commands

• report_port –verbose # reports all constraints on all in/output

• report_clock # reports all clock attributes
• reset_design # resets all attributes and constraints
• report_timing # each path is timed twice! rise and fall

• set_clock_uncertainty 0.X clockname # set clock skew (post CTS)

• set_max_transition 0.X port # set signal transition time (slew)
• report_constraint -all_violators

• set_fix_hold clockname # fix hold violations

• list_lib # list libraries currently in DC memory
• report_lib libname # report attributes of library

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Timing Report

Adapted from Synopsys Website

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Design Vision

• Timing -> Path Slack.

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Environment Attributes

• Set operating conditions.

• list_lib
• report_lib libname
• set_operating_conditions –max conditionname
Operating Conditions:

Operating Condition Name : typical

Library : gscl45nm
Process : 1.00
Temperature : 27.00
Voltage : 1.10

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Timing Optimization Strategies

• Architectural / Micro-architectural
• E.g., more pipeline stages.
• RTL-level
• See lecture on RTL design for synthesis.
• Resource sharing.
• Operator ordering.
• Flatten design.
• Remove unnecessary glue logic.
• Compile Effort
• Incremental (Bottom-up) Strategy
• Compile + set_dont_touch
• Can individually succeed! Adapted from Synopsys Website

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